JP5291851B2 - Display device and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor display device capable of displaying a sharp and highly precise picture whose flicker, longitudinal stripes, lateral stripes and oblique stripes are scarcely viewed by an observer. SOLUTION: A video signal which is inputted from the outside is written in RAMs which are provided in the frame frequency converting part of this semiconductor display device and the written video signal is read out in turn by two times. A period when the video signal written in the RAMs is read out one time is shorter than a period when the video signal is written in the RAMs. Then, the potential of display signals to be inputted to respective pixels is inverted on the basis of the potential (counter potential) of counter electrodes in consecutive respective two frame periods and the same videos are displayed on a pixel part in the consecutive two frame periods.

Description

  The present invention relates to a driving method suitable for a semiconductor display device using a display medium such as liquid crystal or EL (electroluminescence), and a semiconductor display device that performs display using the driving method. The present invention also relates to an electronic device using the semiconductor display device.

  2. Description of the Related Art In recent years, a technique for manufacturing an element formed using a semiconductor thin film over an insulating substrate, for example, a thin film transistor (TFT) has been rapidly developed. This is because the demand for semiconductor display devices (typically, active matrix liquid crystal display devices) has increased.

  An active matrix liquid crystal display device displays an image by controlling charges applied to several tens to several millions of pixels arranged in a matrix by a switching element (pixel transistor) of a pixel formed of a transistor. Is.

  Note that a pixel in this specification refers to a switching element, a pixel electrode connected to the switching element, a counter electrode, and a passive element (liquid crystal, electroluminescence) provided between the pixel electrode and the counter electrode. And is mainly composed.

  A typical example of the display operation of the liquid crystal panel included in the active matrix liquid crystal display device will be briefly described below with reference to FIG. FIG. 26A is a top view of the liquid crystal panel, and FIG. 26B is a diagram showing an arrangement of pixels.

  The source signal line drive circuit 701 and the source signal lines S1 to S6 are connected. Further, the gate signal line driving circuit 702 and the gate signal lines G1 to G4 are connected. A plurality of pixels 703 are provided in a portion surrounded by the source signal lines S1 to S6 and the gate signal lines G1 to G4. The pixel 703 is provided with a pixel TFT 704 and a pixel electrode 705. Note that the number of source signal lines and gate signal lines is not limited to this value.

  A video signal is input to the source signal line driver circuit 701 from an IC (not shown) provided outside the panel.

  The video signal input to the source signal line driver circuit 701 is sampled and input to the source signal line S1 as a display signal. In addition, the gate signal line G1 is selected by a selection signal input to the gate signal line G1 from the gate signal line driver circuit 702, and all the pixel TFTs 704 whose gate electrodes are connected to the gate signal line G1 are turned on. The display signal input to the source signal line S1 is input to the pixel electrode 705 of the pixel (1, 1) through the pixel TFT 704. The liquid crystal is driven by the potential of the input display signal and the amount of transmitted light is controlled, so that a part of the image (image corresponding to the pixel (1, 1)) is displayed on the pixel (1, 1).

  Next, the video signal input to the source signal line driver circuit 701 is sampled at the next moment while the state in which the image is displayed on the pixel (1, 1) is held by a holding capacitor (not shown) or the like. Then, it is input to the source signal line S2 as a display signal. Note that the storage capacitor is a capacitor for holding the potential of the display signal input to the gate electrode of the pixel TFT 704 for a certain period.

  The gate signal line G1 remains selected, and the pixel TFT 704 of the pixel (1, 2) at the portion where the gate signal line G1 and the source signal line S2 intersect is in an on state. The display signal input to the source signal line S2 is input to the pixel electrode 705 of the pixel (1, 2) via the pixel TFT 704. The liquid crystal is driven by the potential of the input display signal, and the amount of transmitted light is controlled. Similarly to the pixel (1, 1), the pixel (1, 2) has a part of the image (pixel (1, 2). (Corresponding image) is displayed.

  Such display operation is sequentially performed, and all the pixels (1, 1) (1, 2) (1, 3) (1, 4) (1, 5) (1, 6) connected to the gate signal delay G1 are performed. ) Are displayed one after another. During this time, the gate signal line G1 continues to be selected by the selection signal input to the gate signal line G1.

  When a display signal is input to all the pixels connected to the gate signal line G1, the gate signal line G1 is not selected. Subsequently, the gate signal line G2 is selected by the selection signal input to the gate signal line G2. A part of the image is successively applied to all the pixels (2, 1) (2, 2) (2, 3) (2, 4) (2, 5) (2, 6) connected to the gate signal line G2. Is displayed. During this time, the gate signal line G2 continues to be selected.

  One operation is displayed on the pixel portion 706 by sequentially repeating the above-described operation for all the gate signal lines. This period during which one image is displayed is referred to as one frame period. The period in which one image is displayed on the pixel portion 706 and the vertical blanking period may be combined to form one frame period. All the pixels hold the state in which the image is displayed with a holding capacitor (not shown) or the like until the pixel TFT of each pixel is turned on again.

Problems to be solved by the invention

  In a liquid crystal panel using a TFT or the like as a normal switching element, in order to prevent deterioration of the liquid crystal, the polarity of the potential of the signal input to each pixel is inverted (AC drive) with reference to the potential of the counter electrode (counter potential). . Examples of AC driving methods include frame inversion driving, source line inversion driving, gate line inversion driving, and dot inversion driving. Below, each drive method is demonstrated.

  FIG. 27A shows a polarity pattern (hereinafter simply referred to as a polarity pattern) of a display signal input to each pixel in frame inversion driving. In the diagrams (FIGS. 27, 6, 7, 8, and 9) showing the polarity patterns in this specification, the potential of the display signal input to the pixel is positive with respect to the counter potential. The case is indicated by “+”, and the case where it is negative is indicated by “−”. The polarity pattern shown in FIG. 27 corresponds to the pixel arrangement shown in FIG.

  Note that in this specification, a display signal having a positive polarity means a display signal having a higher potential than the counter potential. A display signal having a negative polarity means a display signal having a potential lower than the counter potential.

  In addition, in the scanning method, in one screen (one frame), an interlace scan in which an odd-numbered gate signal line and an even-numbered gate signal line are scanned twice (two fields), and an odd-numbered and even-numbered gate signal line. Although there is non-interlaced scanning in which the second gate signal line is scanned in order without being divided, an example using non-interlaced scanning will be mainly described here.

  The feature of the frame inversion drive is that a display signal having the same polarity is input to all pixels within one arbitrary frame period (polarity pattern (1)), and is input to all pixels in the next one frame period. The display signal is displayed with the polarity of the display signal reversed (polarity pattern (2)). That is, when attention is paid only to the polarity pattern, two types of polarity patterns (polarity pattern (1) and polarity pattern (2)) are repeatedly displayed every frame period. Note that in this specification, the display signal is input to the pixel means that the display signal is input to the pixel electrode via the pixel TFT.

  Next, source line inversion driving will be described. FIG. 27B shows a pixel polarity pattern in source line inversion driving.

  As shown in FIG. 27B, the source line inversion drive is characterized in that display signals having the same polarity are input to all pixels connected to the same source signal line in any one frame period. That is, display signals having opposite polarities are inputted between pixels connected to adjacent source signal lines. Note that in this specification, a pixel connected to a source signal line means a pixel having a pixel TFT whose source region or drain region is connected to the source signal line.

  In the next one frame period, a display signal having a polarity opposite to that of the display signal input in the immediately preceding frame period is input to each source signal line. Therefore, if the polarity pattern in any one frame period is the polarity pattern (3), the polarity pattern in the next one frame period is the polarity pattern (4).

  Next, gate line inversion driving will be described. FIG. 27C shows a polarity pattern in gate line inversion driving.

  As shown in FIG. 27C, the gate line inversion drive is characterized in that display signals having the same polarity are input to all the pixels connected to the same gate signal line in any one frame period. That is, display signals having opposite polarities are inputted between pixels connected to adjacent gate signal lines. Note that in this specification, a pixel connected to a gate signal line indicates a pixel having a pixel TFT whose gate electrode is connected to the gate signal line.

  In the next frame period, a display signal having a polarity opposite to that of the display signal input in the immediately preceding frame period is input to the pixels connected to each gate signal line. Therefore, if the polarity pattern in any one frame period is the polarity pattern (5), the polarity pattern in the next one frame period is the polarity pattern (6).

  That is, similarly to the source line inversion driving, two types of polarity patterns (polarity pattern (5) and polarity pattern (6)) are repeatedly displayed every frame period.

  Next, dot inversion driving will be described. A polarity pattern in dot inversion driving is shown in FIG.

  As shown in FIG. 27D, dot inversion driving is a method of inverting the polarity of a display signal input to a pixel between all adjacent pixels. In any one frame period, a display signal having a polarity opposite to that of the display signal input in the immediately preceding one frame period is input to each pixel. Therefore, if the polarity pattern in any one frame period is the polarity pattern (7), the polarity pattern in the next one frame period is the polarity pattern (8). That is, this is a driving method in which two types of polarity patterns are repeatedly displayed every frame period.

  The alternating drive described above is a useful method for preventing the deterioration of the liquid crystal. However, when the AC drive described above is used, the screen may flicker or vertical stripes, horizontal stripes, or diagonal stripes may be visually recognized.

  This is because even if the same gradation display is performed in each pixel, the brightness of the screen is slightly different between the display when the polarity of the input display signal is positive and the display when it is negative. Conceivable. This phenomenon will be described in detail below by taking frame inversion driving as an example.

  FIG. 28 shows a timing chart when the active matrix liquid crystal display device shown in FIG. FIG. 28 is a timing chart when the active matrix type liquid crystal display device displays white when normally black and displays black when normally white. A period during which a selection signal is input to one gate signal line is defined as one line period, and a period from when the selection signal is input to all gate signal lines until one image is displayed is defined as one frame period.

  When a display signal is input to the source signal line S1 and a selection signal is input to the gate signal line G1, the pixel (1, 1) provided at the intersecting portion of the source signal line S1 and the gate signal line G1 is applied. A positive polarity display signal is input. In the pixel (1, 1), the potential applied to the pixel electrode by the input display signal is ideally held for one frame period by the holding capacitor or the like.

  However, actually, when the potential of the gate signal line G1 shifts to a potential for turning off the pixel TFT when one line period ends, the potential of the pixel electrode is also drawn by ΔV in the direction in which the potential of the gate signal delay G1 shifts. Sometimes. This phenomenon is called field through, and ΔV is called penetration voltage.

  The punch-through voltage ΔV is given by the following equation.

[Formula 1]
ΔV = V × Cgd / (Cgd + Clc + Cs)

  V is the amplitude of the potential of the gate electrode, Cgd is the capacitance between the gate electrode and the drain region of the pixel TFT, Clc is the capacitance of the liquid crystal between the pixel electrode and the counter electrode, and Cs is the capacitance of the storage capacitor.

  In the timing chart shown in FIG. 28, the actual potential of the pixel electrode in the pixel (1, 1) is indicated by a solid line, and the ideal potential of the pixel electrode not considering field through is indicated by a dotted line. In the first frame period, a display signal having a positive polarity is input to the pixel (1, 1). In the case of the first frame period shown in FIG. 28, the potential of the gate signal line changes in the negative direction simultaneously with the end of the first line period, and the potential of the pixel electrode of the pixel (1, 1) also actually penetrates. It changes in the negative direction by the voltage. In FIG. 28, the penetration voltage in the first frame period is shown as ΔV1.

  Next, in the first line period of the second frame period, a display signal having a negative polarity that is opposite to that of the first line period of the first frame period is input to the pixel (1, 1). When the first line period in the second frame period ends, the potential of the gate signal line G1 changes in the negative direction. At the same time, the potential of the pixel electrode of the pixel (1, 1) actually changes in the negative direction by the penetration voltage. In FIG. 28, the penetration voltage in the second frame period is shown as ΔV2.

  In FIG. 28, the drive voltage after the end of the first line period of the first frame period is indicated as V1, and the drive voltage after the end of the first line period of the second frame period is indicated as V2. In this specification, the driving voltage means a potential difference between the potential of the pixel electrode and the counter potential.

  The drive voltage V1 and the drive voltage V2 have a voltage difference of ΔV1 + ΔV2. For this reason, the brightness of the screen in the pixel (1, 1) differs between the first frame period and the second frame period.

  Therefore, a method of reducing the value of the counter potential so that the values of the drive voltage V1 and the drive voltage V2 are the same can be considered.

  However, the capacitance Cgd between the gate electrode and the drain region of the pixel TFT is the value when a display signal having a positive polarity is input to the pixel and when a display signal having a negative polarity is input to the pixel. Is different. Further, the capacitance Clc of the liquid crystal between the pixel electrode and the counter electrode also varies depending on the potential of the display signal input to the pixel. Therefore, since the values of Cgd and Clc are different for each frame period, the value of the piercing voltage ΔV is also different for each frame period. Therefore, even if the value of the counter potential is changed, the drive voltage in the pixel (1, 1) varies depending on the frame period, and as a result, the brightness of the screen varies.

  This is a phenomenon that can occur not only in the pixel (1, 1) but also in all pixels, and the brightness of the pixel can vary depending on the polarity of the display signal input to the pixel.

  Therefore, in the frame inversion driving, the brightness of the image displayed in the first frame period is different from the brightness of the image displayed in the second frame period, and the viewer visually recognizes the flicker. In particular, the flicker was remarkably confirmed in the halftone display.

  Similarly, in the case of source line inversion driving, gate line inversion driving, and dot inversion driving, the display brightness is the same for pixels that receive a display signal with a positive polarity and pixels that receive a display signal with a negative polarity. Is different.

  Therefore, vertical stripes are displayed on the screen in the source line inversion drive, and horizontal stripes are displayed in the gate line inversion drive. In the dot inversion driving, vertical stripes, horizontal stripes, or diagonal stripes may appear depending on the image displayed on the screen.

  It is considered effective to increase the frame frequency in order to prevent the screen from flickering due to AC driving or to prevent vertical stripes, horizontal stripes or diagonal stripes from being visually recognized.

  However, in order to increase the frame frequency, it is necessary to increase the frequency of the video signal input to the IC. When the frequency of the video signal is increased, it is necessary to increase the specifications of the electronic device that generates the video signal, which increases the cost. In addition, the drive frequency of the electronic device that generates the video signal cannot fully support the frequency of the video signal, which places a burden on the electronic device that generates the video signal. There could be difficulties.

  Therefore, in view of the above, the present invention uses a driving method of a semiconductor display device in which flickering, vertical stripes, horizontal stripes, and diagonal stripes are hardly visible to an observer, and can display a clear and high-definition image, and the driving method. An object is to provide a semiconductor display device.

Means for solving the problem

  In the present invention, the prescribed frame frequency of the video signal input to the semiconductor display device from the outside is increased in the frame rate conversion unit included in the semiconductor display device. In this specification, a frame rate conversion unit (frame-rate conversion) means a circuit that changes the frequency of an input signal and outputs it. Then, in each of the two consecutive frame periods, the potential of the display signal input to each pixel is inverted with reference to the potential of the counter electrode (the counter potential), and the same image is displayed on the pixel portion in the two consecutive frame periods. .

  With the above-described configuration, it is possible to display a clear and high-definition image in which flicker, vertical stripes, horizontal stripes, and diagonal stripes are hardly visible to an observer.

  Further, by using frame inversion in the present invention, it is possible to suppress the occurrence of a phenomenon fringe called disclination between adjacent pixels, and to prevent the brightness of the entire display screen from being reduced. Disclination is a phenomenon in which an electric field is generated between a pixel electrode to which a positive display signal is input and a pixel electrode to which a negative display signal is input, thereby disturbing the alignment of liquid crystal molecules. When the pixels are made higher in definition, the distance between the pixel electrodes of adjacent pixels is shortened, so that the electric field between the pixel electrodes is increased, and the apparent aperture ratio is significantly reduced due to disclination. Therefore, the use of frame inversion in the present invention is effective in that the brightness of the entire display screen is not reduced.

  The frame conversion unit in the semiconductor display device of the present invention has one or a plurality of RAMs. Then, the video signal input from the outside is written into one of the one or a plurality of RAMs, and the written video signal is sequentially read twice. With the above configuration, writing of video signals to the RAM and reading from the RAM can be performed simultaneously.

  It is also important in the present invention that the period in which the video signal written in the RAM is read once is shorter than the period in which the video signal is written in the RAM. With the above configuration, the frequency of the video signal after being read from the RAM can be made higher than the frequency of the video signal before being written to the RAM.

  Further, in the present invention, it is important that the potential of one of the two display signals generated using the video signal read out twice from the RAM is the potential of the counter electrode (the counter potential). Inverting as a reference, generating two display signals with reversed polarity. Therefore, the potential of the display signal input to each pixel is inverted with respect to the potential of the counter electrode (counter potential) in each of the two consecutive frame periods, and thus is the same as that of the pixel portion in the two consecutive frame periods. An image is displayed.

  Therefore, since the frame frequency can be increased without increasing the frequency of the video signal input to the IC, flicker, vertical stripes, horizontal stripes are given to the observer without imposing a burden on the electronic device generating the video signal. In addition, it is possible to display a clear and high-definition image in which the diagonal stripes are hardly visible.

  Further, by using frame inversion in the present invention, it is possible to suppress the occurrence of a phenomenon fringe called disclination between adjacent pixels, and to prevent the brightness of the entire display screen from being reduced.

  Then, the temporal average of the potential of the display signal input to each pixel is closer to the counter potential, which prevents the deterioration of the liquid crystal compared to the case where a different display signal is input to each pixel in each frame period. It is more effective.

  The present invention can be used for all AC driving such as frame inversion driving, source line inversion driving, gate line inversion driving, and dot inversion driving.

  In the present invention, the plurality of RAMs and the source signal line driver circuit may be provided on an IC substrate or on an active matrix substrate provided with a pixel portion. Further, a part of the source signal line driver circuit may be provided over the active matrix substrate and the rest may be provided over the IC substrate and connected by FPC or the like.

  Note that in the semiconductor device of the present invention, a transistor used for a pixel may be a transistor formed using single crystal silicon, or a thin film transistor using polycrystalline silicon or amorphous silicon. Further, a transistor using an organic semiconductor may be used.

  The configuration of the present invention is shown below.

According to the present invention,
In a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit,
Display signals are input to the plurality of pixel electrodes through the plurality of pixel TFTs,
All display signals input to the plurality of pixel electrodes have the same polarity with respect to the potential of the counter electrode during each frame period,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A semiconductor display device is provided that is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

According to the present invention,
In a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit,
Display signals input to the plurality of source signal lines are input to the plurality of pixel electrodes via the plurality of pixel TFTs,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines, and the plurality of source signal lines The display signal input to each has always the same polarity with respect to the potential of the counter electrode,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A semiconductor display device is provided that is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

According to the present invention,
In a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit,
Display signals input to the plurality of source signal lines are input to the plurality of pixel electrodes via the plurality of pixel TFTs,
During each line period, the display signals input to all of the plurality of source signal lines always have the same polarity with respect to the potential of the counter electrode,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A semiconductor display device is provided that is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

According to the present invention,
In a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit,
Display signals input to the plurality of source signal lines are input to the plurality of pixel electrodes via the plurality of pixel TFTs,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A semiconductor display device is provided that is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice each from one of the one RAM or the plurality of RAMs are both input to a source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
Writing a video signal to any one of the one RAM or the plurality of RAMs and writing a video signal to any one of the one RAM or the plurality of RAMs include the written video. There is provided a semiconductor display device characterized in that a signal is longer than a period for reading the first time and a period for reading the signal for the second time.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice from any one of the one RAM or the plurality of RAMs are both converted into analog by the D / A conversion circuit and then input to the source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice each from one of the one RAM or the plurality of RAMs are both input to a source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
All display signals input to the pixel electrode have the same polarity with respect to the potential of the counter electrode during each frame period,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice each from one of the one RAM or the plurality of RAMs are both converted to analog in the D / A conversion circuit and then input to the source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
All display signals input to the pixel electrode have the same polarity with respect to the potential of the counter electrode during each frame period,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice each from one of the one RAM or the plurality of RAMs are both input to a source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The generated two display signals are input to the pixel electrode through the plurality of source signal lines and the pixel TFT,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines, and the plurality of source signal lines The display signal input to each has always the same polarity with respect to the potential of the counter electrode,
A period during which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period during which the written video signal is read out for the first time and a period during which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice from any one of the one RAM or the plurality of RAMs are both converted into analog by the D / A conversion circuit and then input to the source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The generated two display signals are input to the pixel electrode through the plurality of source signal lines and the pixel TFT,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines, and the plurality of source signal lines The display signal input to each has always the same polarity with respect to the potential of the counter electrode,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice each from one of the one RAM or the plurality of RAMs are both input to a source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
During each line period, the display signals input to all of the plurality of source signal lines always have the same polarity with respect to the potential of the counter electrode,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice from any one of the one RAM or the plurality of RAMs are both converted into analog by the D / A conversion circuit and then input to the source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
During each line period, the display signals input to all of the plurality of source signal lines always have the same polarity with respect to the potential of the counter electrode,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice each from one of the one RAM or the plurality of RAMs are both input to a source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
A semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion portion,
The plurality of pixels each include a pixel TFT, a pixel electrode, and a counter electrode.
The frame rate conversion unit has one or more RAMs,
A video signal is written to any one of the one RAM or the plurality of RAMs,
The video signal written in any one of the one RAM or the plurality of RAMs is read twice,
Video signals read out twice from any one of the one RAM or the plurality of RAMs are both converted into analog by the D / A conversion circuit and then input to the source signal line driving circuit,
Two display signals are generated by the source signal line driving circuit,
The first two display signals have opposite polarities,
The two generated display signals are input to the pixel electrode through the pixel TFT,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
A period in which a video signal is written to any one of the one RAM or the plurality of RAMs is longer than a period in which the written video signal is read out for the first time and a period in which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention,
In a driving method of a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit,
Display signals are input to the plurality of pixel electrodes through the plurality of pixel TFTs,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. The method for driving a semiconductor display device is characterized in that the polarity is a signal obtained by inverting the polarity of the counter electrode with reference to the potential of the counter electrode.

According to the present invention,
In a driving method of a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit,
Display signals are input to the plurality of pixel electrodes through the plurality of pixel TFTs,
All display signals input to the plurality of pixel electrodes have the same polarity with respect to the potential of the counter electrode during each frame period,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A driving method of a semiconductor display device is provided, which is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

According to the present invention,
In a driving method of a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit,
Display signals input to the plurality of source signal lines are input to the plurality of pixel electrodes via the plurality of pixel TFTs,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines, and the plurality of source signal lines The display signal input to each has always the same polarity with respect to the potential of the counter electrode,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A driving method of a semiconductor display device is provided, which is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

According to the present invention,
In a driving method of a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit,
Display signals input to the plurality of source signal lines are input to the plurality of pixel electrodes via the plurality of pixel TFTs,
During each line period, the display signals input to all of the plurality of source signal lines always have the same polarity with respect to the potential of the counter electrode,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A driving method of a semiconductor display device is provided, which is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

According to the present invention,
In a driving method of a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit,
Display signals input to the plurality of source signal lines are input to the plurality of pixel electrodes via the plurality of pixel TFTs,
During each frame period, display signals having opposite polarities with respect to the potential of the counter electrode are input to adjacent source signal lines of the plurality of source signal lines,
In the adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are reversed with respect to the potential of the counter electrode,
The frame rate conversion unit operates in synchronization with the display signal,
Among any two adjacent frame periods, a display signal input to the plurality of pixel electrodes in a frame period that appears later is a display signal input to the plurality of pixel electrodes in a frame period that appears first. A driving method of a semiconductor display device is provided, which is a signal obtained by inverting the potential of the counter electrode with respect to the potential of the counter electrode.

  The present invention may be characterized in that the RAM is an SDRAM.

  The present invention includes a computer, a video camera, and a DVD player using the semiconductor display device.

  A frame rate conversion unit included in the semiconductor display device of the present invention will be described below with reference to FIG. In the present embodiment, a configuration using an SDRAM (Synchronous Dynamic Random Access Memory) as a RAM is shown. However, the present invention is not limited to the RAM, and other DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) can be used as long as high-speed data writing and reading are possible.

  The frame rate conversion unit 100 includes a control unit 101, a frame frequency conversion unit 102, and an address generator unit 106. The frame frequency conversion unit 102 includes a first SDRAM (SDRAM 1) 103, a second SDRAM (SDRAM 2) 104, and a data formatting unit 105. A D / A conversion circuit 107 converts the video signal output from the frame rate conversion unit 100 from digital to analog.

  In the present embodiment, the frame frequency conversion unit 102 has two SDRAMs (first SDRAM 103 and second SDRAM 104), but the number of SDRAMs is not limited to two, and any number is possible. In this embodiment, a case where the number of SDRAMs is two will be described in order to simplify the description.

  The Hsync signal, the Vsync signal, and the CLK signal are input to the control unit 101. The Hsync signal, the Vsync signal, and the CLK signal control the driving of the address generator control signal (address generator controll signal) that controls the driving of the address generator unit, and the driving of the first SDRAM 103 and the second SDRAM 104 from the control unit 101. SDRAM control signals (RAM CLK1, RAM CLK2) are output.

  The address generator unit 106 is driven by an address generator control signal input from the control unit 101, and determines a counter value that specifies the addresses of the memory addresses of the first SDRAM 103 and the second SDRAM 104. For example, when the counter value is 0, the address 0 of the memory address of the first SDRAM 103 and the second SDRAM 104 is designated, when the counter value is 1, the address 1 is specified, when the counter value is 2, the address 2 is specified, and the counter value is q Then, q address is designated respectively.

  Information on the counter value is input from the address generator unit 106 to the first SDRAM 103 and the second SDRAM 104 as a first counter signal (address count signal 1) and a second counter signal (address count signal 2), respectively. The counter value included in the first counter signal is referred to as a first counter value, and the counter value included in the second counter signal is referred to as a second counter value.

  A digital video signal is input to the data format unit 105 from the outside. The data format unit 105 is connected to an AC power supply (AC Cont).

  The digital video signal input to the data format unit 105 is sequentially written in the address specified by the first or second counter signal in the first or second SDRAM 103 or 104. Digital video signals are not written simultaneously to a plurality of SDRAMs, but are always written to only one SDRAM.

  The number of bits of the digital video signal input in the data format unit 105 may be increased and then written to the first SDRAM 103 or the second SDRAM 104.

  Next, the written video signal is sequentially read from the address designated by the first or second counter signal of the first or second SDRAM 103, 104. Digital video signals are not always read from a plurality of SDRAMs, but are always read from only one SDRAM.

  Note that the video signal is read out twice. The writing of the video signal to one SDRAM and the reading of the video signal from another SDRAM are performed in parallel.

  The operation of the frame frequency conversion unit 102 in FIG. 1 will be specifically described with reference to FIG. In FIG. 2A, the video signal is written in the first SDRAM 103, and at the same time, the video signal written in the second SDRAM 104 is read twice. In FIG. 2B, the video signal written in the first SDRAM 103 is read twice, and the video signal is written in the second SDRAM 104 at the same time.

  Although this embodiment shows an example using an SDRAM that can write only a video signal corresponding to one image, the present invention is not limited to this. A RAM that can write a video signal corresponding to one image or more may be used. If a RAM capable of writing video signals corresponding to two or more images is used, only one RAM may be used in the present invention. Conversely, when a RAM that can only write video signals corresponding to one image or less is used, a video signal corresponding to one image may be written using a plurality of RAMs.

  FIG. 3 shows video signal writing and reading timings in the first SDRAM 103 and the second SDRAM 104. A video signal is written to the first SDRAM 103 in the writing period p. Then, the video signal written in the first SDRAM 103 in the writing period p is read twice in the first reading period p and the second reading period p that appear next.

  In addition, a video signal is written to the second SDRAM 104 in the writing period (p−1). Then, the video signal written to the second SDRAM 104 in the writing period (p-1) is read twice in the first reading period (p-1) and the second reading period (p-1) that appear next.

  The writing period p and the first and second reading periods (p-1) appear simultaneously. That is, the video signal is read twice from the second SDRAM 104 in parallel with the video signal being written to the first SDRAM 103.

  The writing period (p + 1) and the first and second reading periods p appear simultaneously. That is, the video signal is read twice from the first SDRAM 103 in parallel with the video signal being written to the second SDRAM 104.

  When the first and second reading periods p are completed, a writing period (p + 2) appears, and a video signal is written to the first SDRAM 103 again. In parallel with this, the first and second readout periods (p + 1) appear, and the video signal is read out from the second SDRAM 104 twice.

  The read video signal is input to the data format unit 105. In the data format unit 105, data processing is performed so that when one of the video signals read out twice is converted into analog, the polarity is inverted with reference to the potential of the counter electrode of the liquid crystal. Is done. Then, two video signals, that is, a video signal that has been subjected to data processing and a video signal that has not been subjected to data processing, are output from the data formatting unit 105 as processed video signals (Processed video signals).

  The two video signals output from the data format unit 105 are input to the D / A conversion circuit 107 and converted to analog. The D / A conversion circuit 107 is constantly supplied with two power supply voltages, high and low, and the D / A conversion circuit 107 outputs two analog video signals whose polarities are inverted with reference to the potential of the counter electrode. Is done. The two video signals converted into analog are sequentially input to the source signal line driver circuit.

  Note that the data format unit 105 may serial-parallel convert the video signal to divide the video signal by the number of division driving divisions, and then input the video signal to the D / A conversion circuit 107.

  The division driving is a driving method for suppressing the driving frequency of the source signal line driving circuit without reducing the image display speed. Specifically, this is a driving method in which source signal lines are divided into m groups, and display signals are simultaneously input to m source signal lines during one line period.

  FIG. 4 shows a configuration of a pixel portion of an active matrix liquid crystal display device in which the driving method of the present invention is used. FIG. 4A is a circuit diagram of a pixel portion, and FIG. 4B is a diagram showing an arrangement of pixels.

  Reference numeral 110 denotes a pixel portion. Source signal lines S1 to Sx connected to the source signal line driver circuit and gate signal lines G1 to Gy connected to the gate signal line driver circuit are provided in the pixel portion 110. In the pixel portion 110, a pixel 111 is provided in a portion surrounded by the source signal lines S1 to Sx and the gate signal lines G1 to Gy. The pixel 111 is provided with a pixel TFT 112 and a pixel electrode 113.

  A selection signal is input to the gate signal lines G1 to Gy from the gate signal line driving circuit, and the switching of the pixel TFT 112 is controlled by the selection signal. In this specification, controlling the switching of the TFT means selecting whether to turn the TFT on or off.

  The gate signal line G1 is selected by the selection signal input to the gate signal line G1 from the gate signal line driving circuit, and the pixel (1, 1), () of the portion where the gate signal line G1 and the source signal line S1 intersect 1, 2),..., (1, x) pixel TFTs 112 are turned on.

  Two analog video signals with inverted polarities input to the source signal line driving circuit are sampled sequentially in accordance with a sampling signal from a shift register or the like in the source signal line driving circuit, and source signal lines S1 to Sx are respectively displayed as display signals. Is input.

  The display signals input to the source signal lines S1 to Sx are input to the pixel electrodes 113 of the pixels (1, 1), (1, 2),..., (1, x) via the pixel TFT 112. The liquid crystal is driven by the potential of the input display signal and the amount of transmitted light is controlled, so that a part of the image (pixel (1 (1), (1, 2),..., (1, x)) 1), (1,2),..., (1, x)).

  When a display signal is input to all the pixels connected to the gate signal line G1, the gate signal line G1 is not selected. Subsequently, the state in which the image is displayed on the pixels (1, 1), (1, 2),..., (1, x) is input to the gate signal line G2 while being held by a holding capacitor (not shown). The gate signal line G2 is selected by the selected signal. Note that the storage capacitor is a capacitor for holding the potential of the display signal input to the gate electrode of the pixel TFT 112 for a certain period. Similarly, a part of the image is displayed one after another on all the pixels (2, 1) (2, 2),..., (2, x) connected to the gate signal line G2. During this time, the gate signal line G2 continues to be selected.

  By sequentially repeating the above-described operation for all the gate signal lines, one image is displayed on the pixel portion 110. This period during which one image is displayed is referred to as one frame period. A period in which one image is displayed on the pixel portion 110 and a vertical blanking period may be combined to form one frame period. All the pixels hold the state in which the image is displayed with a holding capacitor (not shown) or the like until the pixel TFT of each pixel is turned on again.

  Note that the polarities of the two video signals are inverted, and the polarities of the display signals sampled and input to the source signal lines are also inverted. FIG. 5 shows a timing chart of selection signals and display signals input to the gate signal lines and the source signal lines in the active matrix liquid crystal display device shown in FIG.

  The line period indicates a period in which one gate signal line is selected, and a period until all the line periods (L1 to Ly) appear corresponds to one frame period. Alternatively, all the line periods (L1 to Ly) and the vertical blanking period may be combined to form one frame period. The active matrix liquid crystal display device of the present invention has a first frame period (previous frame) and a second frame period (following frame) for displaying the same image.

  In the first half frame period, an image is displayed based on the video signal read from the SDRAM in the first readout period. In the second frame period, an image is displayed based on the video signal read from the SDRAM in the second read period. Therefore, the displayed image is the same in the first half frame period and the second half frame period, but the polarity of the display signal input to each source signal line is inverted.

  FIG. 6 shows the polarity of the display signal input to the pixel electrode of each pixel when frame inversion driving is performed. In FIG. 6, the first, third, and fifth frame periods correspond to the first half frame period, and the second and fourth frame periods correspond to the second half frame period.

  In all the frame periods, the polarities of the display signals input to the pixel electrodes of all the pixels are the same. The polarity of the display signal input to each pixel is inverted between the first half frame period and the second half frame period.

  The displayed images are the same in the first frame period and the second frame period. Further, the displayed images are the same in the third frame period and the fourth frame period. Although the sixth frame period is not illustrated, the displayed images are the same in the fifth frame period and the sixth frame period.

  Next, FIG. 7 shows the polarity of a display signal input to the pixel electrode of each pixel when source line inversion driving is performed. In FIG. 7, the first, third, and fifth frame periods correspond to the first half frame period, and the second and fourth frame periods correspond to the second half frame period.

  In all the frame periods, the polarities of the display signals input to the pixel electrodes of the pixels connected to the source signal lines are all the same. Further, the polarity of the display signal input to the pixel electrode of the pixel connected to the adjacent source signal line is inverted. The polarity of the display signal input to each pixel is inverted between the first half frame period and the second half frame period.

  The displayed images are the same in the first frame period and the second frame period. Further, the displayed images are the same in the third frame period and the fourth frame period. Although the sixth frame period is not illustrated, the displayed images are the same in the fifth frame period and the sixth frame period.

  Next, FIG. 8 shows the polarity of the display signal input to the pixel electrode of each pixel when gate line inversion driving is performed. In FIG. 8, the first, third, and fifth frame periods correspond to the first half frame period, and the second and fourth frame periods correspond to the second half frame period.

  In all frame periods, the polarities of the display signals input to the pixel electrodes of the pixels connected to the gate signal lines are all the same. The polarity of the display signal input to the pixel electrode of the pixel connected to the adjacent gate signal line is inverted. The polarity of the display signal input to each pixel is inverted between the first half frame period and the second half frame period.

  The displayed images are the same in the first frame period and the second frame period. Further, the displayed images are the same in the third frame period and the fourth frame period. Although the sixth frame period is not illustrated, the displayed images are the same in the fifth frame period and the sixth frame period.

  Next, FIG. 9 shows the polarity of a display signal input to the pixel electrode of each pixel when dot inversion driving is performed. In FIG. 9, the first, third, and fifth frame periods correspond to the first half frame period, and the second and fourth frame periods correspond to the second half frame period.

  In all the frame periods, the polarities of the display signals input to the pixel electrodes of adjacent pixels are all inverted. The polarity of the display signal input to each pixel is inverted between the first half frame period and the second half frame period.

  The displayed images are the same in the first frame period and the second frame period. Further, the displayed images are the same in the third frame period and the fourth frame period. Although the sixth frame period is not illustrated, the displayed images are the same in the fifth frame period and the sixth frame period.

  According to the present invention, the frequency of the video signal after being read from the SDRAM can be made higher than the frequency of the video signal before being written to the SDRAM. Therefore, the frame frequency can be increased inside the active matrix liquid crystal display device without increasing the frequency of the video signal input from the outside, which places a burden on the electronic device that generates the video signal. In addition, it is possible to display a clear and high-definition image in which flicker, vertical stripes, horizontal stripes, and diagonal stripes are not easily seen by an observer.

  Further, in the present invention, it is important that the potential of one of the video signals read out twice from the SDRAM is inverted with respect to the potential of the counter electrode (counter potential) as a reference. Is to enter. Therefore, in each of two consecutive frame periods, the potential of the display signal input to each pixel is inverted with reference to the potential of the counter electrode (counter potential), and the same image is displayed on the pixel portion. With the above configuration, the temporal average of the potential of the display signal input to each pixel is closer to the counter potential, and the liquid crystal is deteriorated compared to the case where a different display signal is input to each pixel in each frame period. It is more effective in preventing the flicker, vertical stripes, horizontal stripes, and diagonal stripes from being visually recognized by the observer.

  Further, by using frame inversion in the present invention, it is possible to suppress the occurrence of a phenomenon fringe called disclination between adjacent pixels, and to prevent the brightness of the entire display screen from being reduced.

  Although the above-described driving method has been described with an example using non-interlaced scanning, the scanning method of the present invention is not limited to this. The scanning method may be interlaced scanning.

  Further, in this embodiment, two analog video signals with reversed polarities are output from the D / A conversion circuit by constantly supplying two high and low power supply voltages to the D / A conversion circuit. Either one is selected by an analog switch or the like. However, the method of inverting the polarity of the video signal is not limited to this, and a known method can be used. For example, before input to the D / A conversion circuit, the polarities reversed from each other may be included as information in two digital video signals. Further, by controlling the level of the power supply voltage applied to the D / A conversion circuit, the polarities of the two analog video signals continuously output from the D / A conversion circuit may be reversed. .

  Examples of the present invention will be described below.

Example 1
In this embodiment, an example different from FIG. 3 will be described with respect to video signal writing and reading timings in the first SDRAM 103 and the second SDRAM 104 in FIG.

  In this embodiment, the first and second reading periods are shorter than the writing period. After the first and second reading periods are finished, before the next writing period is started, a blank period in which neither writing nor reading of the video signal is performed is provided.

  FIG. 10 shows video signal writing and reading timings in the first SDRAM 103 and the second SDRAM 104. A video signal is written to the first SDRAM 103 in the writing period p. Then, the video signal written in the first SDRAM 103 in the writing period p is read twice in the first reading period p and the second reading period p.

  In addition, a video signal is written to the second SDRAM 104 in the writing period (p−1). The video signal written to the second SDRAM 104 in the writing period (p-1) is read twice in the first reading period (p-1) and the second reading period (p-1).

  The writing period p and the first and second reading periods (p-1) appear simultaneously. That is, the video signal is read twice from the second SDRAM 104 in parallel with the video signal being written to the first SDRAM 103.

  The writing period (p + 1) and the first and second reading periods p appear simultaneously. That is, the video signal is read twice from the first SDRAM 103 in parallel with the video signal being written to the second SDRAM 104.

  When the first and second read periods p are finished, a blank period appears. The blank period is a period in which neither writing nor reading of the video signal is performed. When the blank period ends, a writing period (p + 2) appears, and the video signal is written to the first SDRAM 103 again. In parallel with this, the first and second readout periods (p + 1) appear, and the video signal is read out from the second SDRAM 104 twice.

  The length of the blank period needs to be longer than the length obtained by subtracting the first and second reading periods from the writing period. Any number of blank periods may be provided as long as the image does not flicker. By providing a blank period, a video signal is not written to two or more SDRAMs, and a video signal is not read from two or more SDRAMs.

  Note that the blank period may be provided between the writing period and the first reading period, or may be provided between the second reading period and the writing period. Further, it may be provided between the first readout period and the second readout period.

  The video signal read twice is input to the data format unit 105.

(Example 2)
In this embodiment, an example different from FIGS. 3 and 10 will be described with respect to video signal writing and reading timings in the first SDRAM 103 and the second SDRAM 104 in FIG.

  In this embodiment, the first and second reading periods are longer than the writing period. Then, after the writing period ends, before the next first reading period is started, a blank period in which neither writing nor reading of the video signal is performed is provided.

  FIG. 11 shows video signal writing and reading timings in the first SDRAM 103 and the second SDRAM 104. A video signal is written to the first SDRAM 103 in the writing period p. When the writing period p ends, a blank period appears. The blank period is a period in which neither writing nor reading of the video signal is performed.

  After the blank period, the video signal written in the first SDRAM 103 in the writing period p is read twice in the first reading period p and the second reading period p.

  In addition, a video signal is written to the second SDRAM 104 in the writing period (p−1). When the writing period (p-1) ends, a blank period appears. After the blank period, the video signal written in the second SDRAM 104 in the writing period (p−1) is read twice in the first reading period (p−1) and the second reading period (p−1).

  The writing period p and the first and second reading periods (p-1) appear simultaneously. That is, the video signal is read twice from the second SDRAM 104 in parallel with the video signal being written to the first SDRAM 103.

  The writing period (p + 1) and the first and second reading periods p appear simultaneously. That is, the video signal is read twice from the first SDRAM 103 in parallel with the video signal being written to the second SDRAM 104.

  When the first and second reading periods p are completed, a writing period (p + 2) appears, and the video signal is written to the first SDRAM 103 again. In parallel with this, the first and second readout periods (p + 1) appear, and the video signal is read out from the second SDRAM 104 twice.

  The length of the blank period needs to be longer than the length obtained by subtracting the writing period from the length obtained by adding the first reading period and the second reading period. Any number of blank periods may be provided as long as the image does not flicker. By providing a blank period, a video signal is not written to two or more SDRAMs, and a video signal is not read from two or more SDRAMs.

  Note that the blank period may be provided between the writing period and the first reading period, or may be provided between the second reading period and the writing period. Further, it may be provided between the first readout period and the second readout period.

  The video signal read twice is input to the data format unit 105.

  Note that this embodiment can be freely combined with Embodiment 1.

(Example 3)
In this embodiment, an example different from that in FIG. 1 of the frame rate conversion unit included in the semiconductor display device of the present invention will be described with reference to FIG.

  In the present embodiment, the frame rate conversion unit has three SDRAMs.

  The frame rate conversion unit 200 includes a control unit 201, a frame frequency conversion unit 202, and an address generator unit 206. The frame frequency conversion unit 202 includes a first SDRAM (SDRAM 1) 203, a second SDRAM (SDRAM 2) 204, a third SDRAM (SDRAM 3) 207, and a data formatting unit 205. A D / A conversion circuit 208 converts the video signal output from the frame rate conversion unit 200 from digital to analog.

  In this embodiment, the frame frequency conversion unit 202 has three SDRAMs (first SDRAM 203, second SDRAM 204, and third SDRAM 207), but the number of SDRAMs is not limited to three.

  The Hsync signal, the Vsync signal, and the CLK signal are input to the control unit 201. The Hsync signal, the Vsync signal, and the CLK signal from the control unit 201, an address generator control signal that controls the driving of the address generator unit, the first SDRAM 203, the second SDRAM 204, and the third SDRAM 207. SDRAM control signals (RAM CLK1, RAM CLK2, and RAM CLK3) for controlling the driving of are output.

  The address generator unit 206 is driven by an address generator control signal input from the control unit 201, and determines a counter value that specifies the addresses of the memory addresses of the first SDRAM 203, the second SDRAM 204, and the third SDRAM 207. For example, if the counter value is 0, the memory address of the first SDRAM 203, the second SDRAM 204, and the third SDRAM 207 is designated as address 0. If the counter value is 1, the address is 1, and if the counter value is 2, the address is 2. When the counter value is q, address q is designated. The counter value information includes a first counter signal (address count signal 1), a second counter signal (address count signal 2), and a third counter signal (address count signal 3) from the address generator unit 206 to the first SDRAM 203 and the first counter signal. The second SDRAM 204 and the third SDRAM 207 are input.

  The counter value included in the first counter signal is referred to as a first counter value, the counter value included in the second counter signal is referred to as a second counter value, and the counter value included in the third counter signal is referred to as a third counter value.

  A digital video signal (Video Signal) is input to the data format unit 205. The data format unit 205 is connected to an AC power supply (AC Cont).

  The digital video signal input to the data format unit 205 is sequentially written in the designated address of the first SDRAM 203, the second SDRAM 204, or the third SDRAM 207. Digital video signals are not written simultaneously to a plurality of SDRAMs, but are always written to only one SDRAM.

  Alternatively, the data format unit 205 may increase the number of bits of the input digital video signal and then write the data to the first SDRAM 203, the second SDRAM 204, or the third SDRAM 207.

  Next, the written video signal is sequentially read from the designated address of the first SDRAM 203, the second SDRAM 204, or the third SDRAM 207. Digital video signals are not always read from a plurality of SDRAMs, but are always read from only one SDRAM.

  Note that the video signal is read out twice. The writing of the video signal to one SDRAM and the reading of the video signal from another SDRAM are performed in parallel.

  FIG. 13 shows video signal writing and reading timings in the first SDRAM 203, the second SDRAM 204, and the third SDRAM 207.

  A video signal is written to the first SDRAM 203 in the writing period p. Then, the video signal written in the first SDRAM 203 in the writing period p is read twice in the first reading period p and the second reading period p.

  In addition, a video signal is written to the second SDRAM 204 in the writing period (p−1). Then, the video signal written in the second SDRAM 204 in the writing period (p−1) is read twice in the first reading period (p−1) and the second reading period (p−1).

  In addition, a video signal is written to the third SDRAM 207 in the writing period (p + 1). Then, the video signal written in the third SDRAM 207 in the writing period (p + 1) is read twice in the first reading period (p + 1) and the second reading period (p + 1).

  The writing period p and the first and second reading periods (p-1) appear simultaneously. That is, the video signal is read twice from the second SDRAM 204 in parallel with the video signal being written to the first SDRAM 203.

  The writing period (p + 1) and the first and second reading periods p appear simultaneously. That is, the video signal is read twice from the first SDRAM 203 in parallel with the video signal being written to the third SDRAM 207.

  The writing period (p + 2) and the first and second reading periods (p + 1) appear simultaneously. That is, the video signal is read twice from the third SDRAM 207 in parallel with the video signal being written to the second SDRAM 204.

  When the first and second readout periods p are finished, a blank period appears. During the blank period of the first SDRAM 203, the second SDRAM 204 is in the writing period (p + 2), and the third SDRAM 207 is in the first and second reading periods (p + 1).

  A blank period appears when the first and second readout periods (p-1) are completed. During the blank period of the second SDRAM 204, the third SDRAM 207 is in the write period (p + 1), and the first SDRAM 203 is in the first and second read periods p.

  When the first and second reading periods (p + 1) are finished, a blank period appears. During the blank period of the third SDRAM 207, the first SDRAM 203 is in the writing period (p + 3), and the second SDRAM 204 is in the first and second reading periods (p + 2).

  In the first SDRAM 203, the second SDRAM 204, and the third SDRAM 207, when the blank period ends, the next writing period starts.

  The video signal read twice is input to the data format unit 205. In the data format unit 205, data processing is performed so that one of the video signals read out twice is inverted in polarity with respect to the potential of the counter electrode of the liquid crystal when converted into analog. Is done. Then, two video signals, a video signal that has been subjected to data processing and a video signal that has not been subjected to data processing, are output from the data formatting unit 205.

  The two video signals output from the data format unit 205 are input to the D / A conversion circuit 208 and converted to analog. The polarities of the two video signals converted to analog are inverted with reference to the potential of the counter electrode. The two video signals converted into analog are sequentially input to the source signal line driver circuit.

  Note that the data format unit 205 may serial-parallel convert the video signal to divide the video signal by the number of division driving divisions, and then input the video signal to the D / A conversion circuit 208.

  Since the structure of the active matrix liquid crystal display device using the driving method of the present invention and the polarity of the display signal input to the pixel portion are the same as those shown in FIGS. Description is omitted.

  In this embodiment, video signal writing and reading in the first SDRAM 203, the second SDRAM 204, and the third SDRAM 207 in FIG. 12 are not necessarily performed at the timing shown in FIG. The first and second reading periods may be longer or shorter than the writing period. However, it is important to adjust the length of the blank period so that a video signal is not written to two or more SDRAMs and a video signal is not read from two or more SDRAMs. .

  The blank period may be provided between the writing period and the first reading period, or may be provided between the second reading period and the writing period. Further, it may be provided between the first readout period and the second readout period.

  The video signal read twice is input to the data format unit 205.

Example 4
In this embodiment, a detailed structure of a semiconductor display device of the present invention driven by an analog method will be described. FIG. 14 is a block diagram showing an example of the semiconductor display device of the present invention driven in an analog manner.

  Reference numeral 301 denotes a source signal line driver circuit, 302 denotes a gate signal line driver circuit, and 303 denotes a pixel portion. In this embodiment, one source signal line driving circuit and one gate signal line driving circuit are provided, but the present invention is not limited to this configuration. Two source signal line driver circuits may be provided, or two gate signal line driver circuits may be provided.

  The source signal line driver circuit 301 includes a shift register 301_1, a level shift 301_2, and a sampling circuit 301_3. Note that the level shift 301_2 may be used as necessary, and is not necessarily used. In this embodiment, the level shift 301_2 is provided between the shift register 301_1 and the sampling circuit 301_3; however, the present invention is not limited to this configuration. A configuration may be adopted in which the level shift 301_2 is incorporated in the shift register 301_1.

  In the pixel portion 303, the source signal line 304 connected to the source signal line driver circuit 301 and the gate signal line 306 connected to the gate signal line driver circuit 302 intersect. In a region surrounded by the source signal line 304 and the gate signal line 306, a thin film transistor (pixel TFT) 307 of the pixel 305, a liquid crystal cell 308 with a liquid crystal sandwiched between the counter electrode and the pixel electrode, a storage capacitor 309, Is provided. Note that although a structure in which the storage capacitor 309 is provided is shown in this embodiment, the storage capacitor 309 is not necessarily provided.

  The gate signal line driver circuit 302 includes a shift register and a buffer (both not shown). Moreover, you may have a level shift.

  A source clock signal (S-CLK) and a source start pulse signal (S-SP), which are panel control signals, are input to the shift register 301_1. A sampling signal for sampling the display signal is output from the shift register 301_1. The output sampling signal is input to the level shift 301_2, and the potential amplitude is increased and output.

  The sampling signal output from the level shift 301_2 is input to the sampling circuit 301_3. At the same time, a video signal is input to the sampling circuit 301_3 through a video signal line (not shown).

  In the sampling circuit 301_3, the input video signal is sampled by the sampling signal and input to the source signal line 304 as a display signal.

  The pixel TFT 307 is turned on by a selection signal input from the gate signal line driver circuit 302 via the gate signal line 306. The display signal sampled and input to the source signal line 304 is input to the pixel electrode of the predetermined pixel 305 through the pixel TFT 307 in the on state.

  The liquid crystal is driven by the potential of the input display signal and the amount of transmitted light is controlled to display a part of the image (an image corresponding to each pixel) on the pixel 305.

  In addition, a present Example can be freely combined with Examples 1-3.

(Example 5)
In this embodiment, a detailed circuit configuration of the source signal line driver circuit 301 shown in Embodiment 4 will be described. Note that the source signal line driver circuit shown in Embodiment 4 is not limited to the structure shown in this embodiment.

  FIG. 15 is a circuit diagram of the source signal line driving circuit of this embodiment. Reference numeral 301_1 denotes a shift register, 301_2 denotes a level shift, and 301_3 denotes a sampling circuit.

  The source clock signal S-CLK, the source start pulse signal S-SP, and the drive direction switching signal SL / R are respectively input to the shift register 301_1 from the wirings illustrated in the drawing. The video signal is input to the sampling circuit 301_3 through the video signal line 310. In this embodiment, an example in which the driving is divided into four is shown. Therefore, there are four video signal lines 310. However, the present embodiment is not limited to this configuration, and the number of divisions can be arbitrarily determined.

  The video signal input to each video signal 310 is sampled by the sampling circuit 301_3 by the sampling signal input from the level shift 301_2. Specifically, the video signal is sampled by the analog switch 311 included in the sampling circuit 301_3 and is simultaneously input to the corresponding source signal lines 304_1 to 304_4.

  By repeating the above operation, display signals are input to all source signal lines.

  FIG. 16A shows an equivalent circuit diagram of the analog switch 311. The analog switch 311 has an n-channel TFT and a p-channel TFT. A video signal is input as Vin from the wiring shown in the figure. A sampling signal output from the level shift 301_2 and a signal having a polarity opposite to that of the sampling signal are input from IN or INb, respectively. The video signal is sampled by this sampling signal and is output from Vout as a display signal.

  FIG. 16B shows an equivalent circuit diagram of the level shift 301_2. A sampling signal output from the shift register 301_1 and a signal having a polarity opposite to that of the sampling signal are input from Vin or Vinb, respectively. Vddh indicates application of a positive voltage, and Vss indicates application of a negative voltage. The level shift 301_2 is designed so that a signal obtained by increasing the voltage of the signal input to Vin and inverting it is output from Voutb. That is, when Hi is input to Vin, a signal corresponding to Vss is output from Voutb, and when Lo is input, a signal corresponding to Vddh is output from Voutb.

  In addition, a present Example can be freely combined with Examples 1-4.

(Example 6)
Hereinafter, a frame rate conversion unit included in the semiconductor display device of the present invention will be described with reference to FIG.

  Since the frame rate conversion unit 100 shown in FIG. 17 is the same as that shown in FIG. 1, refer to the embodiment for the detailed operation and description of the configuration. However, in this embodiment, the video signal output from the frame rate conversion unit 100 is input to the source signal line drive circuit as it is, without being input to the D / A conversion circuit.

  Note that the number of SDRAMs is not limited to two, and any number may be used as long as it is two or more.

  A semiconductor display device driven by a digital method used in this embodiment will be described with reference to FIG.

  FIG. 18 shows a block diagram of a semiconductor display device of the present invention driven in a digital manner. Here, a 4-bit digital drive type semiconductor display device is taken as an example. Note that the digital drive type semiconductor display device used in this embodiment is not limited to the structure shown in FIG. The semiconductor display device may have any structure as long as display can be performed using a digital video signal.

  As shown in FIG. 18, the digital drive type semiconductor display device is provided with a source signal line drive circuit 412, a gate signal line drive circuit 409, and a pixel portion 413.

  The source signal line driver circuit 412 is provided with a shift register 401, a latch 1 (LAT 1) 403, a latch 2 (LAT 2) 404, and a D / A conversion circuit 406. A digital video signal is input from the frame rate conversion unit 100 to the address lines 402 (a to d).

  The address lines 402 (a to d) are connected to the latch 1 (LAT1) 403. A latch pulse line 405 is connected to the latch 2 (LAT2) 404. A gradation voltage line 407 is connected to the D / A conversion circuit 406.

  In the present embodiment, the latch 1 403 and the latch 2 404 (LAT 1 and LAT 2) are each shown by 4 latches for convenience.

  A source signal line 408 connected to the D / A conversion circuit 406 of the source signal line driver circuit 412 and a gate signal line 410 connected to the gate signal line driver circuit 409 are provided in the pixel portion 413.

  In the pixel portion 413, a pixel 415 is provided at a portion where the source signal line 408 and the gate signal line 410 intersect with each other, and the pixel 415 includes a pixel TFT 411 and a liquid crystal cell 414.

  The digital video signals supplied to the address lines 402 (a to d) are sequentially written in all the LAT1 403 by the timing signal from the shift register 401. In the present specification, all LAT1 403 are collectively referred to as LAT1 group.

  A period until digital video signal writing to the LAT1 group is completed is called one line period. That is, a period from when writing of the digital video signal to the leftmost LAT1 is started until when writing of the digital video signal to the rightmost LAT1 is completed is one line period. It should be noted that a period until writing of digital video signals to the LAT1 group is completed and a horizontal blanking period may be combined into one line period.

  After the writing of the digital video signal to the LAT1 group is completed, the digital video signal written to the LAT1 group is transmitted to all the LAT2 404 and written by the latch signal input to the latch pulse line 405. . In this specification, all LAT2s are collectively referred to as LAT2 group.

  After the digital video signal is transmitted to the LAT2 group, the second line period is started. Therefore, the digital video signals supplied to the address lines 402 (a to d) are sequentially written again to the LAT1 group by the timing signal from the shift register 401.

  The digital video signals written in the LAT2 group are simultaneously input to the D / A conversion circuit 406 at the start of the second line period. The input digital video signals are input to the D / A conversion circuit 406 all at once. The input digital video signal is converted into an analog display signal having a voltage corresponding to the image information of the digital video signal by the D / A conversion circuit 406 and input to the source signal line 408.

  The corresponding pixel TFT 411 is switched by the selection signal output from the gate signal line driver circuit 409, and the liquid crystal molecules are driven by the analog display signal input to the source signal line 408.

  In this embodiment, the polarity of the analog display signal output from the D / A conversion circuit 406 is changed by changing the value of the video signal input to the address line 402 for each frame period.

  In addition, a present Example can be freely combined with Examples 1-3.

(Example 7)
An example of a method for manufacturing a liquid crystal display device which is one of the semiconductor display devices of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing the pixel TFT and the storage capacitor of the pixel portion and the TFTs of the source signal line driver circuit and the gate signal line driver circuit provided in the periphery of the pixel portion will be described in detail according to the process.

In FIG. 19A, a glass substrate such as barium borosilicate glass or alumino borosilicate glass represented by Corning # 7059 glass or # 1737 glass, a quartz substrate, or the like is used for the substrate 501. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, a base film 502 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 501 where the TFT is to be formed in order to prevent impurity diffusion from the substrate 501. For example, a silicon oxynitride film 502a formed from SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method has a thickness of 10 to 200 nm (preferably 50 to 100 nm), and is similarly formed from SiH ₄ and N ₂ O. A silicon hydride film 502b is formed to have a thickness of 50 to 200 nm (preferably 100 to 150 nm). Although the base film 502 is shown as a two-layer structure here, the base film 502 may be formed as a single-layer film or a stack of two or more layers of the insulating film.

The silicon oxynitride film 502a is formed by a parallel plate type plasma CVD method. The silicon oxynitride film 502a is introduced into the reaction chamber with SiH ₄ as 10 SCCM, NH ₃ as 100 SCCM, and N ₂ O as 20 SCCM. The substrate temperature is 325 ° C., the reaction pressure is 40 Pa, the discharge power density is 0.41 W / cm ² , the discharge frequency. 60 MHz. On the other hand, the silicon oxynitride silicon film 502b is introduced into the reaction chamber with SiH ₄ as 5 SCCM, N ₂ O as 120 SCCM, and H ₂ as 125 SCCM, the substrate temperature is 400 ° C., the reaction pressure is 20 Pa, and the discharge power density is 0.41 W / cm. ² , formed under conditions of a discharge frequency of 60 MHz. These films can be formed continuously only by changing the substrate temperature and switching the reaction gas.

The silicon oxynitride film 502a thus manufactured has a density of 9.28 × 10 ²² / cm ³ , 7.13% ammonium hydrogen fluoride (NH ₄ HF ₂ ), and ammonium fluoride (NH ₄ F). ) Is a dense and hard film having a slow etching rate of about 63 nm / min at 20 ° C. in a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa). When such a film is used for the base film, it is effective to prevent the alkali metal element from the glass substrate from diffusing into the semiconductor layer formed thereon.

Next, an amorphous semiconductor layer 503a having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a method such as plasma CVD or sputtering. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In the case where an amorphous silicon film is formed as the amorphous semiconductor layer 503a by a plasma CVD method, the base film 502 and the amorphous semiconductor layer 503a can be formed continuously. For example, as described above, after the silicon oxynitride film 502a and the silicon oxynitride film 502b are continuously formed by the plasma CVD method, the reaction gas is changed from SiH ₄ , N ₂ O, H ₂ to SiH ₄ and H ₂ or If switched to only SiH _{4, the} film can be continuously formed without being exposed to the air atmosphere once. As a result, contamination of the surface of the silicon oxynitride silicon film 502b can be prevented, and variation in characteristics and threshold voltage of the manufactured TFT can be reduced.

  Then, a crystallization step is performed to form a crystalline semiconductor layer 503b from the amorphous semiconductor layer 503a. As the method, a laser annealing method, a thermal annealing method (solid phase growth method), or a rapid thermal annealing method (RTA method) can be applied. When using a glass substrate or a plastic substrate with poor heat resistance as described above, it is particularly preferable to apply a laser annealing method. In the RTA method, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, the crystalline semiconductor layer 503b can be formed by a crystallization method using a catalytic element in accordance with the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. In the crystallization step, it is preferable to first release hydrogen contained in the amorphous semiconductor layer, and heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen contained to 5 atom% or less before crystallization. This is good because it can prevent the film surface from being rough.

Further, in the step of forming the amorphous silicon film by the plasma CVD method, if SiH ₄ and argon (Ar) are used as the reaction gas and the substrate temperature during film formation is set to 400 to 450 ° C., the amorphous silicon film The hydrogen concentration can be reduced to 5 atomic% or less. In such a case, heat treatment for releasing hydrogen is not necessary.

When crystallization is performed by laser annealing, a pulse oscillation type or continuous oscillation type excimer laser or argon laser is used as the light source. In the case of using a pulse oscillation type excimer laser, laser annealing is performed by processing laser light into a linear shape. The laser annealing conditions are appropriately selected by the practitioner. For example, the laser pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 300 to 400 mj / cm ² ). Then, the linear beam is irradiated over the entire surface of the substrate, and the linear beam superposition ratio (overlap ratio) at this time is set to 50 to 90%. In this manner, a crystalline semiconductor layer 503b can be obtained as shown in FIG.

Then, using the first photomask (PM1) over the crystalline semiconductor layer 503b, a resist pattern is formed using a photolithography technique, and the crystalline semiconductor layer is divided into islands by dry etching, so that FIG. C), island-like semiconductor layers 504 to 508 are formed. A mixed gas of CF ₄ and O ₂ is used for dry etching of the crystalline silicon film.

In order to control the threshold voltage (Vth) of the TFT, such an island-shaped semiconductor layer is doped with an impurity element imparting p-type at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ^3. It may be added to the entire surface of the semiconductor layer. As an impurity element imparting p-type to a semiconductor, elements of Group 13 of the periodic table such as boron (B), aluminum (Al), and gallium (Ga) are known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for processing a large area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. Such implantation of the impurity element is not always necessary and may be omitted. However, this is a technique that is particularly suitable for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 509 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 nm. In addition, a silicon oxynitride film manufactured by adding O ₂ to SiH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. A silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ is preferable because the interface defect density of the gate insulating film can be reduced. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density of 0. It can be formed by discharging at 5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter. (Fig. 19 (C))

Then, as shown in FIG. 19D, a heat resistant conductive layer 511 for forming a gate electrode over the first shape gate insulating film 509 is formed to a thickness of 200 to 400 nm (preferably 250 to 350 nm). Form. The heat-resistant conductive layer 511 may be formed as a single layer, or may have a stacked structure including a plurality of layers such as two layers or three layers as necessary. The heat resistant conductive layer includes an element selected from Ta, Ti, and W, an alloy containing the element as a component, or an alloy film combining the elements. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained in order to reduce the resistance. Particularly, the oxygen concentration is preferably 30 ppm or less. In this embodiment, the W film is formed with a thickness of 300 nm. The W film may be formed by sputtering using W as a target, or may be formed by thermal CVD using tungsten hexafluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, when sputtering is used, a W film having a purity of 99.9999% or 99.99% is used, and a W film is formed with sufficient consideration so that impurities are not mixed in the vapor phase during film formation. Thus, a resistivity of 9 to 20 μΩcm can be realized.

  On the other hand, when a Ta film is used for the heat resistant conductive layer 511, it can be similarly formed by sputtering. The Ta film uses Ar as a sputtering gas. In addition, when an appropriate amount of Xe or Kr is added to the gas during sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. Since the TaN film has a crystal structure close to an α phase, an α phase Ta film can be easily obtained by forming a TaN film under the Ta film. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm below the heat-resistant conductive layer 511. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, the alkali metal element contained in a trace amount in the heat-resistant conductive layer 511 diffuses into the gate insulating film 509 having the first shape. Can be prevented. In any case, the heat resistant conductive layer 511 preferably has a resistivity in the range of 10 to 50 μΩcm.

Next, resist masks 512 to 517 are formed by using a second photomask (PM2) and using a photolithography technique. Then, a first etching process is performed. In this embodiment, an ICP etching apparatus is used, Cl ₂ and CF ₄ are used as etching gases, and plasma is formed by applying 3.2 W / cm ² RF (13.56 MHz) power at a pressure of 1 Pa. 224 mW / cm ² of RF (13.56 MHz) power is also applied to the substrate side (sample stage), thereby applying a substantially negative self-bias voltage. Under this condition, the etching rate of the W film is about 100 nm / min. In the first etching process, the time during which the W film was just etched was estimated based on this etching rate, and the time when the etching time was increased by 20% was used as the etching time.

  Conductive layers 518 to 523 having a first tapered shape are formed by the first etching treatment. The angles of the tapered portions of the conductive layers 518 to 523 are formed to be 15 to 30 °. In order to perform etching without leaving a residue, overetching that increases the etching time at a rate of about 10 to 20% is performed. Since the selection ratio of the silicon oxynitride film (first shape gate insulating film 509) to the W film is 2 to 4 (typically 3), the surface on which the silicon oxynitride film is exposed by the over-etching process is A second shape gate insulating film 580 having a tapered shape is formed in the vicinity of the ends of the conductive layers 518 to 523 having a first tapered shape etched by about 20 to 50 nm.

Then, a first doping process is performed to add an impurity element of one conductivity type to the island-shaped semiconductor layer. Here, a step of adding an impurity element imparting n-type is performed. The mask 512-517 on which the first shape conductive layer is formed is left as it is, and an impurity element imparting n-type is added by ion doping in a self-aligned manner using the first tapered conductive layers 518-523 as a mask. To do. In order to add the impurity element imparting n-type through the tapered portion at the end of the gate electrode and the second shape gate insulating film 580 so as to reach the semiconductor layer located thereunder, the dose amount is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 80 to 160 keV. As an impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but phosphorus (P) is used. By such an ion doping method, an impurity element imparting n-type is added to the first impurity regions 524 to 528 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / cm ³ , and below the tapered portion. In the formed second impurity regions (A) 529 to 533, an impurity element which imparts n-type in a concentration range of 1 × 10 ¹⁷ to 1 × 10 ²⁰ atomic / cm ³ is not necessarily uniform in the region. Added. (FIG. 20 (A))

  In this step, in the second impurity regions (A) 529 to 533, the change in the concentration of the impurity element imparting n-type contained in at least the portion overlapping with the first shape conductive layers 518 to 523 is caused by the taper portion. Reflects changes in film thickness. That is, the concentration of phosphorus (P) added to the second impurity regions (A) 529 to 533 is inward from the end portions of the conductive layers in the regions overlapping the first shape conductive layers 518 to 523. The concentration gradually decreases. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes due to the difference in film thickness of the tapered portion.

Next, a second etching process is performed as shown in FIG. The etching process is performed similarly by ICP etching device, using a mixed gas of CF ₄ and Cl ₂ as etching gas, RF power 3.2W / cm ² (13.56MHz), bias power 45mW / cm ² (13.56MHz), pressure Etching is performed at 1.0 Pa. Conductive layers 540 to 545 having the second shape formed under these conditions are formed. A tapered portion is formed at the end, and a taper shape is formed in which the thickness gradually increases from the end toward the inside. Compared to the first etching process, the ratio of isotropic etching is increased by reducing the bias power applied to the substrate side, and the angle of the tapered portion is 30 to 60 °. The masks 512 to 517 are etched to scrape the end portions to become masks 534 to 539. Further, the surface of the second shape gate insulating film 580 is etched by about 40 nm, and a third shape gate insulating film 570 is newly formed.

Then, an impurity element imparting n-type conductivity is doped under a condition of a high acceleration voltage with a dose amount lower than that in the first doping treatment. For example, the acceleration voltage is set to 70 to 120 keV and the dose is 1 × 10 ¹³ / cm ² , and the impurity concentration in the region overlapping with the conductive layers 540 to 545 having the second shape is set to 1 × 10 ¹⁶ to 1 × 10 ^18. atoms / cm ³ . In this manner, second impurity regions (B) 546 to 550 are formed.

Then, impurity regions 556 and 557 having a conductivity type opposite to the one conductivity type are formed in the island-shaped semiconductor layers 504 and 506 forming the p-channel TFT. Also in this case, an impurity element imparting p-type is added using the second shape conductive layers 540 and 542 as masks, and impurity regions are formed in a self-aligning manner. At this time, the island-like semiconductor layers 505, 507, and 508 forming the n-channel TFT are covered with a resist mask 551 to 553 using a third photomask (PM3). The impurity regions 556 and 557 formed here are formed by an ion doping method using diborane (B ₂ H ₆ ). The concentration of the impurity element imparting p-type in the impurity regions 556 and 557 is set to 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ³ .

However, the impurity regions 556 and 557 can be divided into three regions containing an impurity element imparting n-type in detail. The third impurity regions 556a and 557a include an impurity element imparting n-type at a concentration of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , and the fourth impurity regions (A) 556b and 557b are 1 × 10 The fourth impurity regions (B) 556c and 557c contain an impurity element imparting n-type at a concentration of ¹⁷ to 1 × 10 ²⁰ atoms / cm ^3. The fourth impurity regions (B) 556c and 557c have a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . And an impurity element which imparts n-type. However, the concentration of the impurity element imparting p-type in these impurity regions 556b, 556c, 557b, and 557c is set to 1 × 10 ¹⁹ atoms / cm ³ or more, and in the third impurity regions 556a and 557a, p By making the concentration of the impurity element imparting the type 1.5 to 3 times the concentration of the impurity element imparting the n-type, the third impurity region serves as a source region and a drain region of the p-channel TFT. There is no problem to function. Further, the fourth impurity regions (B) 556c and 557c are formed so as to partly overlap with the conductive layer 540 or 542 having a second tapered shape.

After that, as shown in FIG. 21A, a first interlayer insulating film 558 is formed over the conductive layers 540 to 545 and the gate insulating film 570 having the second shape. The first interlayer insulating film 558 may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film including a combination thereof. In any case, the first interlayer insulating film 558 is formed of an inorganic insulating material. The thickness of the first interlayer insulating film 558 is 100 to 200 nm. In the case where a silicon oxide film is used as the first interlayer insulating film 558, TEOS and O ₂ are mixed by a plasma CVD method to a reaction pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (13.56 MHz) power density. It can be formed by discharging at 0.5 to 0.8 W / cm ² . In the case where a silicon oxynitride film is used as the first interlayer insulating film 558, a silicon oxynitride film manufactured from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method, or SiH ₄ and N ₂ O is used. What is necessary is just to form with the silicon oxynitride film | membrane produced. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² . Alternatively, a silicon oxynitride silicon film formed using SiH ₄ , N ₂ O, and H ₂ may be used as the first interlayer insulating film 558. Similarly, the silicon nitride film can be formed from SiH ₄ and NH ₃ by plasma CVD.

  Then, a step of activating the impurity element imparting n-type or p-type added at each concentration is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this example, the temperature is 550 ° C. for 4 hours. Heat treatment was performed. In the case where a plastic substrate having a low heat resistant temperature is used as the substrate 501, it is preferable to apply a laser annealing method.

Subsequent to the activation step, the step of hydrogenating the island-like semiconductor layer by changing the atmospheric gas and performing heat treatment at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen. Do. This step is a step of terminating dangling bonds of 10 ¹⁶ to 10 ¹⁸ / cm ^{3 in} the island-like semiconductor layer by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. In any case, it is desirable that the defect density in the island-shaped semiconductor layers 504 to 508 be 10 ¹⁶ / cm ³ or less, and hydrogen may be applied to about 0.01 to 0.1 atomic% for that purpose.

  Then, a second interlayer insulating film 559 made of an organic insulating material is formed with an average film thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, when using a type of polyimide that is thermally polymerized after being applied to the substrate, it is formed by baking at 300 ° C. in a clean oven. When acrylic is used, a two-component type is used, and after mixing the main material and the curing agent, applying the entire surface of the substrate using a spinner, preheating at 80 ° C. for 60 seconds with a hot plate. It can be formed by baking at 250 ° C. for 60 minutes in a clean oven.

  In this manner, by forming the second interlayer insulating film 559 with an organic insulating material, the surface can be satisfactorily planarized. Moreover, since the organic resin material generally has a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and not suitable as a protective film, it is preferably used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 558 as in this embodiment. .

Thereafter, a resist mask having a predetermined pattern is formed using a fourth photomask (PM4), and contact holes reaching impurity regions which are formed in the respective island-like semiconductor layers and serve as source regions or drain regions are formed. The contact hole is formed by a dry etching method. In this case, the second interlayer insulating film 559 made of an organic resin material is first etched using a mixed gas of CF ₄ , O ₂ , and He as an etching gas, and then the first etching gas is changed to CF ₄ and O ₂ . The interlayer insulating film 558 is etched. Further, in order to increase the selectivity with respect to the island-shaped semiconductor layer, the contact hole can be formed by etching the third shape gate insulating film 570 while switching the etching gas to CHF ₃ .

Then, a conductive metal film is formed by sputtering or vacuum vapor deposition, a resist mask pattern is formed by a fifth photomask (PM5), and source lines 560 to 564 and drain lines 565 to 568 are formed by etching. . The pixel electrode 569 is formed together with the drain line. A pixel electrode 571 represents a pixel electrode belonging to an adjacent pixel. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with an impurity region that forms a source or drain region of the island-like semiconductor layer, and the Ti film. Aluminum (Al) was formed to a thickness of 300 to 400 nm so as to be stacked thereon, and a transparent conductive film was formed thereon to a thickness of 80 to 120 nm. Indium zinc oxide alloy (In ₂ O ₃ —ZnO) and zinc oxide (ZnO) are also suitable materials for the transparent conductive film, and gallium (Ga) is added to increase the transmittance and conductivity of visible light. Zinc oxide (ZnO: Ga) or the like can be preferably used.

  In this manner, a substrate having TFTs of a driver circuit (a source signal line driver circuit and a gate signal line driver circuit) and a pixel TFT of a pixel portion can be completed on the same substrate by using five photomasks. A first p-channel TFT 600, a first n-channel TFT 601, a second p-channel TFT 602, a second n-channel TFT 603 are formed in the driver circuit, and a pixel TFT 604 and a storage capacitor 605 are formed in the pixel portion. Yes. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

  In the first p-channel TFT 600, a conductive layer having a second taper shape functions as the gate electrode 620, and the island-shaped semiconductor layer 504 functions as a channel formation region 606, a source region, or a drain region. A third impurity region 607a, a fourth impurity region (A) 607b that forms an LDD region that does not overlap with the gate electrode 620, and a fourth impurity region (B) 607c that forms an LDD region that partially overlaps the gate electrode 620. It has a structure.

  In the first n-channel TFT 601, a conductive layer having a second taper shape functions as the gate electrode 621, and the island-shaped semiconductor layer 505 functions as a channel formation region 608, a source region, or a drain region. 1 impurity region 609a, a second impurity region (A) 609b for forming an LDD region that does not overlap with the gate electrode 621, and a second impurity region (B) 609c for forming an LDD region that partially overlaps the gate electrode 621. It has a structure. For the channel length of 2 to 7 μm, the length of the portion where the second impurity region (B) 609 c overlaps with the gate electrode 621 is 0.1 to 0.3 μm. The length of Lov is controlled from the thickness of the gate electrode 621 and the angle of the tapered portion. By forming such an LDD region in an n-channel TFT, a high electric field generated in the vicinity of the drain region can be relaxed, hot carrier generation can be prevented, and TFT deterioration can be prevented.

  Similarly, in the second p-channel TFT 602 of the driver circuit, the second tapered conductive layer functions as the gate electrode 622, and the island-shaped semiconductor layer 506 includes a channel formation region 610, a source region, or a drain region. A third impurity region 611 a that functions as a fourth impurity region (A) 611 b that forms an LDD region that does not overlap with the gate electrode 622, and a fourth impurity region that forms an LDD region that partially overlaps with the gate electrode 622 ( B) The structure has 611c.

  In the second n-channel TFT 603 of the driver circuit, a conductive layer having a second taper shape functions as the gate electrode 623, and the island-shaped semiconductor layer 507 includes a channel formation region 612, a source region, and a drain region. A first impurity region 613 a that functions, a second impurity region (A) 613 b that forms an LDD region that does not overlap with the gate electrode 623, and a second impurity region that forms an LDD region that partially overlaps the gate electrode 623 (B ) 613c. Similar to the second n-channel TFT 601, the length of the portion where the second impurity region (B) 613 c overlaps with the gate electrode 623 is 0.1 to 0.3 μm.

  The drive circuit includes a logic circuit such as a shift register and a buffer, a sampling circuit formed by an analog switch, and the like. In FIG. 21B, the TFT for forming these is shown as a single gate structure in which one gate electrode is provided between a pair of source and drain, but a multi-gate in which a plurality of gate electrodes are provided between a pair of source and drain. A gate structure is also acceptable.

  In the pixel TFT 604, a conductive layer having a second taper shape functions as the gate electrode 624, and the island-shaped semiconductor layer 508 has a first impurity functioning as a channel formation region 614a, 614b, a source region, or a drain region. Regions 615a, 616, and 617a, a second impurity region (A) 615b that forms an LDD region that does not overlap with the gate electrode 624, and a second impurity region (B) 615c that forms an LDD region that partially overlaps the gate electrode 624 It has the structure which has. The length of the portion where the second impurity region (B) 613c overlaps with the gate electrode 624 is 0.1 to 0.3 μm. Further, the semiconductor includes a second impurity region (A) 619b, a second impurity region (B) 619c, and a region 618 to which an impurity element for determining a conductivity type is not added, which extends from the first impurity region 617. A storage capacitor 605 is formed from a layer, an insulating layer formed in the same layer as the gate insulating film having a third shape, and a capacitor wiring 625 formed from a conductive layer having a second tapered shape.

  The gate electrode 624 of the pixel TFT 604 intersects with the island-like semiconductor layer 508 via the gate insulating film 570, and further extends over a plurality of island-like semiconductor layers to serve as a gate signal line. The storage capacitor 605 is formed in a region where the capacitor wiring 625 overlaps with the semiconductor layer extending from the drain region 617 a of the pixel TFT 604 and the gate insulating film 570. In this structure, an impurity element for the purpose of valence electron control is not added to the semiconductor layer 618.

  The configuration as described above makes it possible to optimize the structure of the TFT constituting each circuit in accordance with the specifications required by the pixel TFT and the drive circuit, and to improve the operation performance and reliability of the semiconductor display device. Further, the LDD region, the source region, and the drain region are easily activated by forming the gate electrode from a heat-resistant conductive material. Further, when forming the LDD region overlapping the gate electrode through the gate insulating film, the impurity element added for the purpose of controlling the conductivity type is provided with a concentration gradient to form the LDD region, particularly in the vicinity of the drain region. It can be expected that the electric field relaxation effect will increase.

  In the case of an active matrix liquid crystal display device, the first p-channel TFT 600 and the first n-channel TFT 601 are used to form a shift register, a buffer, a level shift, etc. that place importance on high-speed operation. FIG. 21B illustrates these circuits as logic circuit portions. The second impurity region (B) 609c of the first n-channel TFT 601 has a structure that places importance on measures against hot carriers. Further, in order to increase the breakdown voltage and stabilize the operation, the TFT of the logic circuit portion may have a double gate structure in which two gate electrodes are provided between a pair of source and drain. A TFT having a double gate structure can be similarly manufactured using the process of this embodiment.

  In addition, a second p-channel TFT 602 and a second n-channel TFT 603 having a structure similar to that of the logic circuit portion can be applied to the sampling circuit including analog switches. Since the sampling circuit emphasizes countermeasures against hot carriers and low off-current operation, the second p-channel TFT 602 in the sampling circuit section has a triple gate structure in which three gate electrodes are provided between a pair of source and drain regions. Such a TFT may be similarly manufactured using the process of this embodiment. The channel length is 3 to 7 μm, the LDD region overlapping with the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

  As described above, the practitioner determines whether the gate electrode configuration of the TFT has a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of source and drain according to the characteristics of the circuit. You just have to choose.

  Next, as shown in FIG. 22A, spacers made of columnar spacers are formed on the active matrix substrate in the state of FIG. The spacer may be provided by dispersing particles of several μm, but here, a method of forming a resin film on the entire surface of the substrate and then patterning it is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Co. is used, and after applying with a spinner, a predetermined pattern is formed by exposure and development processing. Furthermore, it is cured by heating at 150 to 200 ° C. using a clean oven or the like. The spacers produced in this way can have different shapes depending on the conditions of exposure and development processing, but preferably, the spacers are columnar and the top is flat, so that the opposite substrate is When combined, the mechanical strength of the liquid crystal panel can be ensured. The shape is not particularly limited, such as a conical shape or a pyramid shape. For example, when the shape is conical, specifically, the height is 1.2 to 5 μm, the average radius is 5 to 7 μm, the average radius and the bottom radius The ratio is 1 to 1.5. At this time, the taper angle of the side surface is ± 15 ° or less.

  The arrangement of the spacers may be arbitrarily determined. Preferably, as shown in FIG. 22A, in the pixel portion, a columnar spacer 656 is formed so as to overlap with the contact portion 631 of the pixel electrode 569 so as to cover the portion. Good. Since the flatness of the contact portion 631 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 656 is formed in this manner by filling the resin for the spacer in the contact portion 631, so that the electric field in the vicinity of the spacer 656 is formed. It is possible to prevent the disorder of the alignment of the liquid crystal molecules due to the disorder. Further, spacers 655a to 655e are also formed on the TFT of the driver circuit. This spacer may be formed over the entire surface of the driver circuit portion, or may be provided so as to cover the source line and the drain line as shown in FIG.

  Thereafter, an alignment film 657 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The region that is not rubbed in the rubbing direction from the end of the columnar spacer 656 provided in the pixel portion is set to 2 μm or less. In the rubbing process, generation of static electricity is often a problem, but the effect of protecting the TFT from static electricity can be obtained by the spacers 655a to 655e formed on the TFT of the driving circuit. Although not shown in the drawing, the spacers 656 and 655a to 655e may be formed after the alignment film 657 is formed first.

  A light shielding film 652, a transparent conductive film 653, and an alignment film 654 are formed on the counter substrate 651 on the counter side. As the light shielding film 652, a Ti film, a Cr film, an Al film, or the like is formed with a thickness of 150 to 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 658. A filler (not shown) is mixed in the sealant 658, and two substrates are bonded to each other with a uniform interval by the filler and the spacers 656 and 655a to 655e. Thereafter, a liquid crystal material 659 is injected between both the substrates. A known liquid crystal material may be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance continuously changes with respect to the electric field can be used. Some thresholdless antiferroelectric mixed liquid crystals exhibit V-shaped electro-optic response characteristics. In this way, the active matrix liquid crystal display device shown in FIG. 22B is completed.

  A TFT formed by using the manufacturing method shown in this embodiment has high crystallinity of a semiconductor layer, so that it is extremely effective to be used for a semiconductor display device of the present invention which requires a high response speed.

  The manufacturing method of the semiconductor display device of the present invention is not limited to the manufacturing method described in this embodiment. The semiconductor display device of the present invention can be manufactured using a known method.

  In addition, a present Example can be freely combined with Examples 1-5.

(Example 8)
The present invention can be used for various liquid crystal panels. That is, the present invention can be applied to all semiconductor display devices (electronic devices) in which these liquid crystal panels (active matrix type liquid crystal displays) are incorporated as display media.

  Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), game consoles, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones) Or an electronic book). An example of them is shown in FIG.

  FIG. 23A illustrates a display, which includes a housing 2001, a support base 2002, a display portion 2003, and the like. The present invention can be applied to the display portion 2003.

  FIG. 23B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display portion 2102.

  FIG. 23C shows a part (right side) of a head-mounted display, which includes a main body 2201, a signal cable 2202, a head fixing band 2203, a screen portion 2204, an optical system 2205, a display portion 2206, and the like. The present invention can be applied to the display portion 2206.

  FIG. 23D shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2301, a recording medium (DVD or the like) 2302, an operation switch 2303, a display portion (a) 2304, a display portion. (B) 2305 and the like are included. The display portion (a) 2304 mainly displays image information, and the display portion (b) 2305 mainly displays character information. The semiconductor display device of the present invention is used for these display portions (a) 2304 and (b) 2305. be able to. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.

  FIG. 23E illustrates a personal computer, which includes a main body 2401, a video input portion 2402, a display portion 2403, and a keyboard 2404. The present invention can be applied to the video input unit 2402 and the display unit 2403.

  FIG. 23F illustrates a goggle type display which includes a main body 2501, a display portion 2502, and an arm portion 2503. The present invention can be applied to the display portion 2502.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-7.

Example 9
The present invention can be applied to a projector (rear type or front type). Examples of these are shown in FIGS.

  FIG. 24A shows a front projector, which includes a light source optical system, a display device 7601, and a screen 7602. The present invention can be applied to the display device 7601.

  FIG. 24B shows a rear projector, which includes a main body 7701, a light source optical system and display device 7702, a mirror 7703, a mirror 7704, and a screen 7705. The present invention can be applied to the display device 7702.

  Note that FIG. 24C illustrates an example of the structure of the light source optical system and the display devices 7601 and 7702 in FIGS. 24A and 24B. The light source optical system and display devices 7601 and 7702 are composed of a light source optical system 7801, mirrors 7802 and 7804 to 7806, a dichroic mirror 7803, an optical system 7807, a display device 7808, a phase difference plate 7809, and a projection optical system 7810. The projection optical system 7810 includes a plurality of optical lenses provided with a projection lens. This configuration is called a three-plate type because three display devices 7808 are used. In addition, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like in the optical path indicated by an arrow in FIG.

  FIG. 24D illustrates an example of the structure of the light source optical system 7801 in FIG. In this embodiment, the light source optical system 7801 includes a reflector 7811, a light source 7812, lens arrays 7813 and 7814, a polarization conversion element 7815, and a condenser lens 7816. Note that the light source optical system illustrated in FIG. 24D is an example, and the present invention is not limited to this structure. For example, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like in the light source optical system.

  FIG. 24C shows an example of a three-plate type, while FIG. 25A shows an example of a single-plate type. The light source optical system and display device shown in FIG. 25A includes a light source optical system 7901, a display device 7902, a projection optical system 7903, and a phase difference plate 7904. The projection optical system 7903 is composed of a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in FIG. 25A can be applied to the light source optical system and the display devices 7601 and 7702 in FIGS. 24A and 24B. The light source optical system 7901 may be the light source optical system shown in FIG. Note that the display device 7902 is provided with a color filter (not shown) to colorize a display image.

  The light source optical system and display device shown in FIG. 25B is an application example of FIG. 25A. Instead of providing a color filter, a display image is displayed using an RGB rotating color filter disc 7905. Colored. The light source optical system and the display device illustrated in FIG. 25B can be applied to the light source optical system and the display devices 7601 and 7702 in FIGS. 24A and 24B.

  The light source optical system and display device shown in FIG. 25C are called a color filterless single plate type. In this method, a microlens array 7915 is provided in a display device 7916, and a display image is colored using a dichroic mirror (green) 7912, a dichroic mirror (red) 7913, and a dichroic mirror (blue) 7914. The projection optical system 7917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and the display device illustrated in FIG. 25C can be applied to the light source optical system and the display devices 7601 and 7702 in FIGS. 24A and 24B. As the light source optical system 7911, an optical system using a coupling lens and a collimator lens in addition to the light source may be used.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-7.

Effect of the invention

  According to the present invention, since the frame frequency can be increased without increasing the frequency of the video signal input to the IC with the above-described configuration, it is possible for the observer without imposing a burden on the electronic device that generates the video signal. It is possible to display a clear and high-definition image in which flickering, vertical stripes, horizontal stripes, and diagonal stripes are hardly visible.

  Further, by using frame inversion in the present invention, it is possible to suppress the occurrence of a phenomenon fringe called disclination between adjacent pixels, and to prevent the brightness of the entire display screen from being reduced.

  Further, in each of the two consecutive frame periods, the potential of the display signal input to each pixel is inverted with respect to the potential of the counter electrode (counter potential), so that the same image is displayed on the pixel portion. With the above configuration, the temporal average of the potential of the display signal input to each pixel is closer to the counter potential, and the liquid crystal is deteriorated compared to the case where a different display signal is input to each pixel in each frame period. It is more effective to prevent.

  4 is a block diagram of a frame rate conversion unit included in the semiconductor display device of the present invention. FIG.   The block diagram of a frame frequency conversion part.   The figure which shows the timing of writing and reading of the video signal of SDRAM.   FIG. 6 is a diagram of a pixel portion and a driver circuit and a pixel pattern diagram of a semiconductor display device of the present invention.   6 is a timing chart of a selection signal and a display signal in the pixel portion.   The pattern diagram which shows the polarity of the display signal input into the pixel part at the time of frame inversion drive.   FIG. 6 is a pattern diagram showing the polarity of a display signal input to a pixel portion during source line inversion driving.   The pattern diagram which shows the polarity of the display signal input into the pixel part at the time of gate line inversion drive.   The pattern diagram which shows the polarity of the display signal input into the pixel part at the time of dot inversion drive.   The figure which shows the timing of writing and reading of the video signal of SDRAM.   The figure which shows the timing of writing and reading of the video signal of SDRAM.   4 is a block diagram of a frame rate conversion unit included in the semiconductor display device of the present invention. FIG.   The figure which shows the timing of writing and reading of the video signal of SDRAM.   FIG. 6 is a diagram of a pixel portion and a driving circuit of an analog driving semiconductor display device of the present invention.   FIG. 6 is a circuit diagram of a source signal line driver circuit.   Circuit diagram of analog switch and level shift.   4 is a block diagram of a frame rate conversion unit included in the semiconductor display device of the present invention. FIG.   FIG. 4 is a diagram of a pixel portion and a driving circuit of a digital drive semiconductor display device of the present invention.   10A and 10B illustrate a manufacturing process of a semiconductor display device.   10A and 10B illustrate a manufacturing process of a semiconductor display device.   10A and 10B illustrate a manufacturing process of a semiconductor display device.   10A and 10B illustrate a manufacturing process of a semiconductor display device.   The figure of the electronic device to which this invention is applied.   The figure of the projector to which this invention is applied.   The figure of the projector to which this invention is applied.   The top view of an active-matrix liquid crystal display device and the figure which shows arrangement | positioning of a pixel.   The figure which shows the polar pattern in alternating drive.   FIG. 6 is a timing chart of conventional frame inversion driving.

Claims (7)

An address generator section, a data format section, and a frame rate conversion section having a RAM;
A D / A conversion circuit;
A source signal line driving circuit;
A plurality of pixels;
From the address generator unit, a counter signal having a counter value designating an address of a memory address is input to the RAM,
The digital video signal is input to the data format part,
From the data format unit, the digital video signal is written to the address specified by the counter signal of the RAM,
The digital video signal written in the RAM is read twice from the address specified by the counter signal,
The digital video signal read twice from the RAM is input to the data format unit,
In the data format unit, one of the digital video signals read twice is subjected to data processing so that the polarity is reversed with reference to the potential of the counter electrode when converted into analog,
Two of the one of the digital video signal that has been data processed and the other of the digital video signal that has not been data processed are output from the data format unit to the D / A conversion circuit, converted into an analog video signal,
The two analog video signals output from the D / A conversion circuit and having opposite polarities are input to the source signal line driving circuit, and input from the source signal line driving circuit to the pixel electrodes of the plurality of pixels. ,
A blank period is provided between a period during which the digital video signal is written to the RAM and a period during which the digital video signal is read from the RAM .
The RAM includes a first RAM and a second RAM,
Period in which the digital video signal to said first RAM of the RAM is written, and the blank period of time and said second RAM in which the digital video signal from said second RAM of the RAM is read out twice It is a period of addition,
In the period in which the digital video signal is written once in the first RAM, the second RAM is provided with a blank period and a period in which the digital video signal is read twice.
The write control of the first RAM, the read of the second RAM, and the drive control of the blank period of the second RAM are independently input to each of the first and second RAMs. Performed by a RAM control signal,
The period during which the digital video signal is written into the first RAM and the period during which the digital video signal is read out from the second RAM start at the same time, or the period during which the digital video signal is written into the first RAM. The display device , wherein the blank period of the second RAM starts at the same time .
An address generator section, a data format section, and a frame rate conversion section having a RAM;
A D / A conversion circuit;
A source signal line driving circuit;
A plurality of pixels;
From the address generator unit, a counter signal having a counter value designating an address of a memory address is input to the RAM,
The digital video signal is input to the data format part,
From the data format unit, the digital video signal is written to the address specified by the counter signal of the RAM,
The digital video signal written in the RAM is read twice from the address specified by the counter signal,
The digital video signal read twice from the RAM is input to the data format unit,
In the data format unit, one of the digital video signals read twice is subjected to data processing so that the polarity is reversed with reference to the potential of the counter electrode when converted into analog,
Two of the one of the digital video signal that has been data processed and the other of the digital video signal that has not been data processed are output from the data format unit to the D / A conversion circuit, converted into an analog video signal,
The two analog video signals output from the D / A conversion circuit and having opposite polarities are input to the source signal line driving circuit, and input from the source signal line driving circuit to the pixel electrodes of the plurality of pixels. ,
A blank period is provided between a period during which the digital video signal is written to the RAM and a period during which the digital video signal is read from the RAM .
The RAM includes a first RAM and a second RAM,
The period during which the digital video signal is read twice from the first RAM of the RAM includes a period during which the digital video signal is written into the second RAM of the RAM and a blank period of the second RAM. It is a period of addition,
In the period in which the digital video signal is read twice from the first RAM, the second RAM is provided with the blank period and the period in which the digital video signal is written once.
The read control of the first RAM, the write of the second RAM, and the drive control of the blank period of the second RAM are independently input to each of the first and second RAMs. Performed by a RAM control signal,
The period during which the digital video signal is read from the first RAM and the period during which the digital video signal is written into the second RAM start at the same time, or the period during which the digital video signal is read from the first RAM The display device , wherein the blank period of the second RAM starts at the same time .
In claim 1 or claim 2 ,
The data format unit increases the number of bits of the digital video signal, and the digital video signal with the increased number of bits is written into the RAM.
In any one of Claims 1 thru | or 3 ,
The display device characterized in that the RAM is SRAM, DRAM or SDRAM.
In any one of Claims 1 thru | or 4 ,
The display device according to claim 1, wherein images displayed on the plurality of pixels are the same based on the two analog video signals having opposite polarities.
An electronic apparatus using the display device according to any one of claims 1 to 5 .
The electronic device according to claim 6 is a display, a camera, an image reproducing device, a computer, or a projector.

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