JP2002108313A - Semiconductor display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor display device capable of displaying a sharp and highly precise picture whose flicker, longitudinal stripes, lateral stripes and oblique stripes are scarcely viewed by an observer. SOLUTION: A video signal which is inputted from the outside is written in RAMs which are provided in the frame frequency converting part of this semiconductor display device and the written video signal is read out in turn by two times. A period when the video signal written in the RAMs is read out one time is shorter than a period when the video signal is written in the RAMs. Then, the potential of display signals to be inputted to respective pixels is inverted on the basis of the potential (counter potential) of counter electrodes in consecutive respective two frame periods and the same videos are displayed on a pixel part in the consecutive two frame periods.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method suitable for a semiconductor display device using a display medium such as a liquid crystal or an EL (electroluminescence), and a semiconductor display device for performing display using the driving method. In addition, the present invention relates to an electronic device using the semiconductor display device.

[0002]

2. Description of the Related Art In recent years, an element formed by using a semiconductor thin film on an insulating substrate, for example, a thin film transistor (TFT)
The technology for making is rapidly developing. The reason is that demand for semiconductor display devices (typically, active matrix liquid crystal display devices) has been increasing.

An active matrix type liquid crystal display device is
An image is displayed by controlling charges applied to tens to millions of pixels arranged in a matrix by a switching element (pixel transistor) of a pixel including a transistor.

[0004] In this specification, a pixel means a switching element, a pixel electrode connected to the switching element, a counter electrode, and a passive element (liquid crystal, liquid crystal, or the like) provided between the pixel electrode and the counter electrode. (Electroluminescence).

A typical example of a display operation of a liquid crystal panel included in an active matrix type liquid crystal display device will be briefly described below with reference to FIG. FIG. 26A is a top view of a liquid crystal panel, and FIG. 26B is a diagram illustrating an arrangement of pixels.

[0006] The source signal line driving circuit 701 is connected to the source signal lines S1 to S6. Further, the gate signal line driving circuit 702 and the gate signal lines G1 to G4 are connected. Then, the source signal lines S1 to S6 and the gate signal line G
A plurality of pixels 703 are provided in a portion surrounded by 1 to G4. The pixel 703 is provided with a pixel TFT 704 and a pixel electrode 705. Note that the number of source signal lines and gate signal lines is not limited to this value.

A video signal is input to the source signal line driving circuit 701 from an IC (not shown) provided outside the panel.

The video signal input to the source signal line drive circuit 701 is sampled and input to the source signal line S1 as a display signal. Also, the gate signal line driving circuit 7
The gate signal line G1 is selected by a selection signal input to the gate signal line G1 from 02, and all the pixel TFTs 704 whose gate electrodes are connected to the gate signal line G1 are turned on. Then, the display signal input to the source signal line S1 is input to the pixel electrode 705 of the pixel (1, 1) via the pixel TFT 704. The liquid crystal is driven by the potential of the input display signal, the amount of transmitted light is controlled, and a part of an image (an image corresponding to the pixel (1, 1)) is displayed on the pixel (1, 1).

Next, while the state in which an image is displayed on the pixel (1, 1) is held by a holding capacitor (not shown) or the like, at the next moment, the image input to the source signal line driving circuit 701 is displayed. The signal is sampled and input to the source signal line S2 as a display signal. Note that the storage capacitor is the pixel TFT 7
This is a capacitor for holding the potential of the display signal input to the gate electrode 04 for a certain period.

The gate signal line G1 remains selected, and the pixel TFT 704 of the pixel (1, 2) at the portion where the gate signal line G1 intersects with the source signal line S2 is on. Then, the display signal input to the source signal line S2 is input to the pixel electrode 705 of the pixel (1, 2) via the pixel TFT 704. The liquid crystal is driven by the potential of the input display signal, and the amount of transmitted light is controlled so that the pixel (1, 2) has a part of the image (pixel (1, 2)) like the pixel (1, 1). Corresponding image) is displayed.

Such a display operation is sequentially performed, and all the pixels (1, 1) (1,...) Connected to the gate signal line G1.
2) Part of the image is sequentially displayed on (1, 3), (1, 4), (1, 5), (1, 6). During this time, the gate signal line G1 is continuously selected by the selection signal input to the gate signal line G1.

When the display signal is input to all the pixels connected to the gate signal line G1, the gate signal line G1 is not selected. Subsequently, the gate signal line G2 is selected by a selection signal input to the gate signal line G2. Then, all the pixels (2, 1) (2, 2) (2, 3) (2, 4) (2,
5) Part of the image is displayed one after another in (2, 6). During this time, the gate signal line G2 continues to be selected.

One image is displayed on the pixel portion 706 by sequentially repeating the above-described operation on all the gate signal lines. The period during which this one image is displayed is called one frame period. A period in which one image is displayed in the pixel portion 706 and a vertical blanking period may be combined into one frame period. And all the pixels are again the pixels T of each pixel.
Until the FT is turned on, the state in which the image is displayed is held by a storage capacitor (not shown) or the like.

[0014]

Normally, in a liquid crystal panel using a TFT or the like as a switching element, in order to prevent deterioration of the liquid crystal, the polarity of the potential of a signal input to each pixel is set to the potential of a counter electrode (counter potential). Invert (AC drive) as a reference. As a method of AC drive, frame inversion drive, source line inversion drive, gate line inversion drive,
Dot inversion driving is exemplified. Hereinafter, each driving method will be described.

FIG. 27A shows a polarity pattern of a display signal input to each pixel in the frame inversion driving (hereinafter, referred to as a pattern).
(Referred to simply as a polarity pattern). In addition, the figure which showed the polarity pattern in this specification [FIG. 27, FIG. 6, FIG. 7, FIG.
In FIG. 9], when the potential of the display signal input to the pixel is positive with respect to the opposing potential, it is indicated by “+”, and when it is negative, it is indicated by “−”. The polarity pattern shown in FIG. 27 corresponds to the pixel arrangement shown in FIG.

In this specification, a display signal having a positive polarity means a display signal having a higher potential than the opposite potential. Further, a display signal having a negative polarity means a display signal having a potential lower than the opposite potential.

In addition, in the scanning method, in one screen (one frame), an odd-numbered gate signal line and an even-numbered gate signal line are divided into two scans (two fields), and interlaced scan is performed. There is a non-interlace scan in which the first and even-numbered gate signal lines are sequentially scanned without any separation. Here, an example using non-interless scan will be mainly described.

The feature of the frame inversion drive is that a display signal of the same polarity is input to all the pixels within an arbitrary one frame period (polarity pattern), and is input to all the pixels during the next one frame period. (Polarity pattern) where the display is performed with the polarity of the display signal being inverted. That is, when focusing only on the polarity pattern, this is a driving method in which two types of polarity patterns (a polarity pattern and a polarity pattern) are repeatedly displayed every frame period. In this specification, inputting a display signal to a pixel means that the display signal is input to a pixel electrode via a pixel TFT.

Next, source line inversion driving will be described. FIG. 27B shows a polarity pattern of a pixel in source line inversion driving.

As shown in FIG. 27 (B), the feature of the source line inversion driving is that, in an arbitrary one frame period,
The display signal of the same polarity is input to all the pixels connected to the same source signal line, and the display signals of the opposite polarity are input to the pixels connected to the adjacent source signal lines. is there. Note that in this specification, a pixel connected to a source signal line refers to a pixel T whose source or drain region is connected to the source signal line.
It shows a pixel having FT.

In the next one frame period, a display signal having a polarity opposite to that of the display signal input in the immediately preceding frame period is input to each source signal line. Therefore, if the polarity pattern in any one frame period is a polarity pattern, the polarity pattern in the next one frame period is a polarity pattern.

Next, the gate line inversion driving will be described. FIG. 27C shows a polarity pattern in the gate line inversion driving.

As shown in FIG. 27C, the feature of the gate line inversion drive is that in any one frame period,
Display signals of the same polarity are input to all pixels connected to the same gate signal line, and display signals of the opposite polarity are input to pixels connected to adjacent gate signal lines. is there. Note that in this specification, a pixel connected to a gate signal line refers to a pixel having a pixel TFT whose gate electrode is connected to the gate signal line.

In the next one frame period, a display signal having a polarity opposite to that of the display signal input in the immediately preceding frame period is input to the pixels connected to each gate signal line. Therefore, if the polarity pattern in any one frame period is a polarity pattern, the polarity pattern in the next one frame period is a polarity pattern.

That is, similar to the above-described source line inversion driving, this is a driving method in which two types of polarity patterns (a polarity pattern and a polarity pattern) are repeatedly displayed every frame period.

Next, the dot inversion driving will be described. FIG. 27D shows a polarity pattern in the dot inversion drive.

As shown in FIG. 27D, the dot inversion drive is a method of inverting the polarity of a display signal input to a pixel between all adjacent pixels. In one arbitrary frame period, a display signal having a polarity opposite to that of the display signal input in the immediately preceding one frame period is input to each pixel. Therefore, if the polarity pattern in any one frame period is a polarity pattern, the polarity pattern in the next one frame period is a polarity pattern. That is, this is a driving method in which two types of polarity patterns are repeatedly displayed every frame period.

The AC driving described above is a useful method for preventing the deterioration of the liquid crystal. However, when the above-described AC drive is used, the screen may flicker, or vertical stripes, horizontal stripes, or oblique stripes may be visually recognized.

This means that even if the same gradation display is performed in each pixel, the brightness of the screen is slightly different between the display when the polarity of the input display signal is positive and the display when the polarity is negative. It is thought to be a reason. Hereinafter, this phenomenon will be described in detail by taking frame inversion driving as an example.

FIG. 28 is a timing chart when the active matrix type liquid crystal display device shown in FIG. 26 is driven by frame inversion. FIG. 28 is a timing chart in the case where the active matrix type liquid crystal display device displays white when normally black, and displays black when normally white. A period during which the selection signal is input to one gate signal line is defined as one line period, and a period from when the selection signal is input to all gate signal lines until one image is displayed is defined as one frame period.

When a display signal is inputted to the source signal line S1 and a selection signal is inputted to the gate signal line G1, the pixels (1,...) Provided at the intersection of the source signal line S1 and the gate signal line G1 are provided. In 1), a display signal having a positive polarity is input. Then, in the pixel (1, 1), the potential given to the pixel electrode by the input display signal is ideally kept for one frame period by a storage capacitor or the like.

However, in practice, when the potential of the gate signal line G1 shifts to a potential for turning off the pixel TFT at the end of one line period, the potential of the pixel electrode is also changed to the potential of the gate signal line G.
In some cases, the potential of 1 is pulled by ΔV in the direction in which the potential shifts. This phenomenon is called field through, and ΔV
Is called a penetration voltage.

The penetration voltage ΔV is given by the following equation.

[0034]

Equation 1 ΔV = V × Cgd / (Cgd + Clc + Cs)

V is the amplitude of the potential of the gate electrode; Cgd is the capacitance between the gate electrode and the drain region of the pixel TFT;
c is the capacity of the liquid crystal between the pixel electrode and the counter electrode, and Cs is the capacity of the storage capacitor.

In the timing chart shown in FIG. 28, the actual potential of the pixel electrode in the pixel (1, 1) is shown by a solid line, and the ideal potential of the pixel electrode without considering the field-through is shown by a dotted line. In the first frame period, a display signal having a positive polarity is input to the pixel (1, 1). FIG.
In the case of the first frame period shown in FIG. 2, the potential of the gate signal line changes in the negative direction at the same time as the end of the first line period, and the potential of the pixel electrode of the pixel (1, 1) is actually It changes in the negative direction by the minute. Note that FIG.
8, the penetration voltage in the first frame period is ΔV
Shown as 1.

Next, in the first line period of the second frame period, a display signal having a negative polarity which is the opposite polarity to the first line period of the first frame period is input to the pixel (1, 1). . Then, when the first line period in the second frame period ends, the potential of the gate signal line G1 changes in the negative direction. At the same time, the potential of the pixel electrode of the pixel (1, 1) actually changes in the negative direction by the penetration voltage. In FIG. 28, the piercing voltage in the second frame period is shown as ΔV2.

Referring to FIG. 28, in the first frame period, the first
The drive voltage after the end of the line period is V1, and the drive voltage after the end of the first line period in the second frame period is V2.
As shown. Note that in this specification, a driving voltage means a potential difference between a potential of a pixel electrode and a counter potential.

The drive voltage V1 and the drive voltage V2 are ΔV1 +
It will have a voltage difference of ΔV2. Therefore, the brightness of the screen at the pixel (1, 1) is different between the first frame period and the second frame period.

Therefore, a method of lowering the value of the opposing potential so that the values of the driving voltage V1 and the driving voltage V2 become the same can be considered.

However, the capacitance Cgd between the gate electrode and the drain region of the pixel TFT differs between when a display signal having a positive polarity is input to the pixel and when a display signal having a negative polarity is input to the pixel. , Their values are different. Further, the capacitance Clc of the liquid crystal between the pixel electrode and the counter electrode also varies depending on the potential of the display signal input to the pixel. for that reason,
Since the values of Cgd and Clc are different for each frame period, the values of the penetration voltage ΔV are also different for each frame period. Therefore, even if the value of the opposing potential is changed, the driving voltage in the pixel (1, 1) differs depending on the frame period, and as a result, the brightness of the screen changes.

This is a phenomenon that can occur not only in the pixel (1, 1) but also in all the pixels. The brightness of the pixel may vary depending on the polarity of the display signal input to the pixel.

Therefore, in the frame inversion driving, the brightness of the image displayed in the first frame period and the brightness of the image displayed in the second frame period are different, and the image is visually recognized as a flicker by an observer. In particular, remarkable flicker was confirmed in the halftone display.

Similarly, in the case of the source line inversion drive, the gate line inversion drive, and the dot inversion drive, the pixel to which the display signal of the positive polarity is input and the pixel to which the display signal of the negative polarity is input are displayed. Brightness is different.

Therefore, vertical stripes were displayed on the screen by the source line inversion drive, and horizontal stripes were displayed by the gate line inversion drive. In the dot inversion driving, vertical stripes, horizontal stripes, or oblique stripes may appear depending on an image displayed on a screen.

It is considered effective to increase the frame frequency in order to prevent the screen from flickering or the vertical stripes, horizontal stripes, or oblique stripes from being visually recognized by the AC drive.

However, in order to increase the frame frequency, it was necessary to increase the frequency of the video signal input to the IC. When the frequency of the video signal is increased, it is necessary to increase the specifications of the electronic device that generates the video signal,
The cost increases. In addition, the driving frequency of the electronic device that generates the video signal cannot correspond to the frequency of the video signal, which places a burden on the electronic device that generates the video signal, and the operation becomes impossible or the reliability is reduced. Difficulty could come out.

In view of the above, the present invention is directed to a method of driving a semiconductor display device which makes it difficult for an observer to see flickers, vertical stripes, horizontal stripes and oblique stripes and can display a clear and high-definition image, and a method of driving the same. An object of the present invention is to provide a semiconductor display device using the same.

[0049]

According to the present invention, a specified frame frequency of a video signal input from the outside to a semiconductor display device is increased in a frame rate conversion section of the semiconductor display device. In this specification, a frame-rate conversion unit refers to a circuit that changes the frequency of an input signal and outputs the changed signal. In two successive frame periods, the potential of the display signal input to each pixel is inverted with reference to the potential of the counter electrode (counter potential), and the same image is displayed on the pixel portion in two successive frame periods. .

According to the above configuration, it is possible to display a clear and high-definition image in which flickers, vertical stripes, horizontal stripes and oblique stripes are hardly visually recognized by an observer.

In particular, by using frame inversion in the present invention, it is possible to suppress the occurrence of a phenomenon stripe called disclination between adjacent pixels and to prevent the brightness of the entire display screen from being reduced. . Disclination is a phenomenon in which an electric field is generated between a pixel electrode to which a positive display signal is input and a pixel electrode to which a negative display signal is input, and the orientation of liquid crystal molecules is disturbed. When the definition of a pixel is increased, the distance between pixel electrodes of adjacent pixels is shortened. Therefore, the electric field between the pixel electrodes is increased, and the apparent aperture ratio is significantly reduced due to disclination. Therefore, the use of frame inversion in the present invention is particularly effective in that the brightness of the entire display screen is not reduced.

The frame converter in the semiconductor display device of the present invention has one or a plurality of RAMs. Then, the video signal input from the outside is written into one of the one or the plurality of RAMs, and the written video signal is sequentially read twice each. With the above configuration, writing of the video signal to the RAM and reading from the RAM can be performed simultaneously.

It is important in the present invention that the period during which the video signal written to the RAM is read once is shorter than the period during which the video signal is written to the RAM. With the above configuration, the frequency of the video signal read from the RAM is
It can be higher than the frequency of the video signal before it is written to the RAM.

Further important in the present invention is the RAM
Out of the two display signals generated using the video signal read twice from
The inversion is based on the potential of the counter electrode (counter potential) as a reference to generate two display signals whose polarity is inverted. Therefore, in each of two consecutive frame periods,
Since the potential of the display signal input to each pixel is inverted with reference to the potential of the counter electrode (counter potential), the same image is displayed on the pixel portion in two consecutive frame periods.

Therefore, since the frame frequency can be increased without increasing the frequency of the video signal input to the IC, it is possible to reduce the load on the electronic device that generates the video signal and to provide the viewer with flicker and flicker. It is possible to display a clear and high-definition image in which vertical stripes, horizontal stripes, and oblique stripes are hardly visually recognized.

In particular, by using frame inversion in the present invention, it is possible to suppress the occurrence of a phenomenon stripe called disclination between adjacent pixels and to prevent the brightness of the entire display screen from being reduced. .

Then, the temporal average of the potential of the display signal input to each pixel becomes closer to the opposite potential, and the deterioration of the liquid crystal is reduced as compared with the case where different display signals are input to each pixel in each frame period. It is more effective to prevent

The present invention can be used for any AC drive such as frame inversion drive, source line inversion drive, gate line inversion drive, dot inversion drive, and the like.

In the present invention, the plurality of RAMs and the source signal line driving circuit may be provided on an IC substrate or on an active matrix substrate provided with a pixel portion. A part of the source signal line driver circuit is provided on an active matrix substrate, and the rest is provided on an IC substrate.
The connection may be made by the above method.

In the semiconductor device of the present invention, the transistor used for the pixel may be a transistor formed using single crystal silicon, or a thin film transistor using polycrystalline silicon or amorphous silicon. Further, a transistor using an organic semiconductor may be used.

The structure of the present invention will be described below.

According to the present invention, in a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion section, the plurality of pixels TF
Display signals are input to the plurality of pixel electrodes via T, and all display signals input to the plurality of pixel electrodes have the same polarity with respect to the potential of the counter electrode during each frame period. The frame rate conversion unit operates in synchronization with the display signal, and is input to the plurality of pixel electrodes in a frame period that appears later in any two adjacent frame periods. A semiconductor display device is provided, wherein the display signal is a signal obtained by inverting a potential of a display signal input to the plurality of pixel electrodes in a frame period which appears earlier with reference to a potential of the counter electrode. You.

According to the present invention, a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines,
In a semiconductor display device having a frame rate conversion unit, a display signal input to the plurality of source signal lines is:
Input to the plurality of pixel electrodes via the plurality of pixel TFTs, and during each frame period, adjacent source signal lines of the plurality of source signal lines have opposite polarities with respect to the potential of the counter electrode. Display signals are input, and the display signals input to each of the plurality of source signal lines always have the same polarity with reference to the potential of the counter electrode, and the frame rate conversion unit A display signal operating in synchronization with a display signal and input to the plurality of pixel electrodes in a frame period appearing later of any two adjacent frame periods,
A semiconductor display device is provided which is a signal obtained by inverting a potential of a display signal input to the plurality of pixel electrodes in a previously appearing frame period with reference to a potential of the counter electrode.

According to the present invention, a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines,
In a semiconductor display device having a frame rate conversion unit, a display signal input to the plurality of source signal lines is:
Display signals that are input to the plurality of pixel electrodes via the plurality of pixel TFTs and input to all of the plurality of source signal lines during each line period always have the same polarity with reference to the potential of the counter electrode. In the adjacent line period, the polarities of the display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode, and the frame rate conversion unit The display signals that operate in synchronization with the display signal and are input to the plurality of pixel electrodes in a later appearing frame period of any two adjacent frame periods are different in the earlier appearing frame period. A semiconductor display device is provided which is a signal obtained by inverting a potential of a display signal input to the plurality of pixel electrodes with reference to a potential of the counter electrode.

According to the present invention, a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines,
In a semiconductor display device having a frame rate conversion unit, a display signal input to the plurality of source signal lines is:
Input to the plurality of pixel electrodes via the plurality of pixel TFTs, and during each frame period, adjacent source signal lines of the plurality of source signal lines have opposite polarities with respect to the potential of the counter electrode. Display signal is input, and in adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode, and the frame rate The converter operates in synchronization with the display signal,
A display signal input to the plurality of pixel electrodes in a later appearing frame period of any two adjacent frame periods is a display signal inputted to the plurality of pixel electrodes in a preceding appearing frame period. Is a signal obtained by inverting the potential of the semiconductor device with reference to the potential of the counter electrode.

According to the present invention, there is provided a semiconductor display device including a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion, wherein the plurality of pixels include a pixel TFT, a pixel electrode, , The counter electrode, and the frame rate conversion unit has one or a plurality of RAMs, and a video signal is written to any one of the one RAM or the plurality of RAMs. , The video signal written to any one of the one RAM or the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The output video signals are both input to a source signal line driving circuit, and two display signals are generated by the source signal line driving circuit, and the two display signals have opposite polarities. The two generated display signals are input to the pixel electrode via the pixel TFT, and the video signal is written to the one RAM or one of the plurality of RAMs and the one RAM. RA
M or a period during which the video signal is written to any one of the plurality of RAMs is longer than a period during which the written video signal is read for the first time and a period during which the video signal is read for the second time. An apparatus is provided.

According to the present invention, there is provided a semiconductor display device including a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion, wherein the plurality of pixels include a pixel TFT, a pixel electrode, , The counter electrode, and the frame rate conversion unit has one or a plurality of RAMs, and a video signal is written to any one of the one RAM or the plurality of RAMs. , The video signal written to any one of the one RAM or the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The output video signals are both D
The signal is converted into an analog signal by the / A conversion circuit and then input to the source signal line drive circuit. The two display signals are generated by the source signal line drive circuit. The two generated display signals are input to the pixel electrode via the pixel TFT, and the period during which the video signal is written to the one RAM or any one of the plurality of RAMs is the written video signal. Is longer than a period during which the first is read and a period during which the second is read.

According to the present invention, there is provided a semiconductor display device including a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion, wherein the plurality of pixels include a pixel TFT, a pixel electrode, , The counter electrode, and the frame rate conversion unit has one or a plurality of RAMs, and a video signal is written to any one of the one RAM or the plurality of RAMs. , The video signal written to any one of the one RAM or the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The output video signals are both input to a source signal line driving circuit, and two display signals are generated by the source signal line driving circuit, and the two display signals have opposite polarities. And, two display signals the generated is input to the pixel electrode via the pixel TFT, all display signal input to the pixel electrode,
During each frame period, the video signal has the same polarity with reference to the potential of the counter electrode, and a period during which a video signal is written to the one RAM or any one of the plurality of RAMs is the written video signal. Is longer than a period during which the first is read and a period during which the second is read.

According to the present invention, there is provided a semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion, wherein the plurality of pixels are a pixel TFT, a pixel electrode, , The counter electrode, and the frame rate conversion unit has one or a plurality of RAMs, and a video signal is written to any one of the one RAM or the plurality of RAMs. , The video signal written to any one of the one RAM or the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The output video signals are both D /
The analog signal is converted into an analog signal by the A conversion circuit, and then input to the source signal line driving circuit. The source signal line driving circuit generates two display signals, and the two display signals have opposite polarities. The two display signals thus input are input to the pixel electrode via the pixel TFT, and all display signals input to the pixel electrode have the same polarity with respect to the potential of the counter electrode during each frame period. The period during which the video signal is written to the one RAM or any one of the plurality of RAMs is longer than the period during which the written video signal is read for the first time and the period at which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention, there is provided a semiconductor display device including a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion section, wherein the plurality of pixels are: A pixel TFT, a pixel electrode, and a counter electrode; and the frame rate conversion unit has one or more RAMs, and one of the one RAM or the plurality of RAMs.
And the video signal written to the one RAM or any one of the plurality of RAMs is read out twice, and any one of the one RAM or the plurality of RAMs is read out. The video signals read out one by two times are input to a source signal line drive circuit, and two display signals are generated by the source signal line drive circuit. The two display signals are inverted in polarity from each other. The two display signals thus generated are input to the pixel electrodes via the plurality of source signal lines and the pixel TFT, and during each frame period, a source signal line adjacent to the plurality of source signal lines is Display signals having polarities opposite to each other with respect to the potential of the counter electrode are input, and the display signals input to each of the plurality of source signal lines are The video signal always has the same polarity with reference to the potential of the electrode, and during the period in which the video signal is written to the one RAM or any one of the plurality of RAMs, the written video signal is read out for the first time. A semiconductor display device is provided which is longer than a period and a period read for the second time.

According to the present invention, there is provided a semiconductor display device including a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion section, wherein the plurality of pixels are: A pixel TFT, a pixel electrode, and a counter electrode; and the frame rate conversion unit has one or more RAMs, and one of the one RAM or the plurality of RAMs.
And the video signal written to the one RAM or any one of the plurality of RAMs is read out twice, and any one of the one RAM or the plurality of RAMs is read out. The video signals read out one by two times are converted into analog signals by a D / A conversion circuit and then input to a source signal line driving circuit, where two display signals are generated by the source signal line driving circuit. , The two display signals have inverted polarities with each other,
The two generated display signals are input to the pixel electrode via the plurality of source signal lines and the pixel TFT, and during each frame period, the source signal lines adjacent to the plurality of source signal lines are Display signals having polarities opposite to each other with respect to the potential of the counter electrode are input,
The display signal input to each of the plurality of source signal lines always has the same polarity with reference to the potential of the counter electrode, and is applied to one of the one RAM or the plurality of RAMs. A period in which the video signal is written is longer than a period in which the written video signal is read for the first time and a period in which the video signal is read for the second time.

According to the present invention, there is provided a semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion section, wherein the plurality of pixels are: A pixel TFT, a pixel electrode, and a counter electrode; and the frame rate conversion unit has one or more RAMs, and one of the one RAM or the plurality of RAMs.
And the video signal written to the one RAM or any one of the plurality of RAMs is read out twice, and any one of the one RAM or the plurality of RAMs is read out. The video signals read out one by two times are input to a source signal line drive circuit, and two display signals are generated by the source signal line drive circuit. The two display signals are inverted in polarity from each other. The two display signals thus generated are input to the pixel electrodes via the pixel TFTs. During each line period, the display signals input to all of the plurality of source signal lines are equal to the potential of the counter electrode. Have the same polarity as a reference, and in the adjacent line periods, the polarity of the display signal input to the plurality of source signal lines is based on the potential of the counter electrode. It is inverted to have said one of R
A semiconductor display characterized in that a period during which a video signal is written to an AM or any one of the plurality of RAMs is longer than a period during which the written video signal is read for the first time and a period during which the video signal is read for the second time. An apparatus is provided.

According to the present invention, there is provided a semiconductor display device including a pixel portion having a plurality of pixels, a source signal line driving circuit, and a frame rate conversion portion, wherein the plurality of pixels include a pixel TFT, a pixel electrode, , The counter electrode, and the frame rate conversion unit has one or a plurality of RAMs, and a video signal is written to any one of the one RAM or the plurality of RAMs. , The video signal written to any one of the one RAM or the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The output video signals are both D
The signal is converted into an analog signal by the / A conversion circuit and then input to the source signal line drive circuit. The two display signals are generated by the source signal line drive circuit. The two generated display signals are input to the pixel electrodes via the pixel TFTs. During each line period, the display signals input to all of the plurality of source signal lines are based on the potential of the counter electrode. Always have the same polarity, and in adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode, and the one RAM, or the plurality of Rs
A semiconductor display device is provided in which a period during which a video signal is written to any one of the AMs is longer than a period during which the written video signal is read for the first time and a period during which the video signal is read for the second time.

According to the present invention, there is provided a semiconductor display device including a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion section, wherein the plurality of pixels are: A pixel TFT, a pixel electrode, and a counter electrode; and the frame rate conversion unit has one or more RAMs, and one of the one RAM or the plurality of RAMs.
And the video signal written to the one RAM or any one of the plurality of RAMs is read out twice, and any one of the one RAM or the plurality of RAMs is read out. The video signals read out one by two times are input to a source signal line drive circuit, and two display signals are generated by the source signal line drive circuit. The two display signals are inverted in polarity from each other. The two generated display signals are input to the pixel electrode via the pixel TFT, and during each frame period, the potential of the counter electrode is applied to a source signal line adjacent to the plurality of source signal lines. Display signals having polarities opposite to each other are input as a reference, and the polarities of the display signals input to the plurality of source signal lines in the adjacent line periods are opposite to each other. Are mutually inverted relative to the electrode potential, the one RAM or the plurality of RAM,
The period in which the video signal is written to any one of the above is longer than the period in which the written video signal is read for the first time and the period in which the video signal is read for the second time.

According to the present invention, there is provided a semiconductor display device having a pixel portion having a plurality of pixels, a source signal line driving circuit, a plurality of source signal lines, and a frame rate conversion section, wherein the plurality of pixels are: A pixel TFT, a pixel electrode, and a counter electrode; and the frame rate conversion unit has one or more RAMs, and one of the one RAM or the plurality of RAMs.
And the video signal written to the one RAM or any one of the plurality of RAMs is read out twice, and any one of the one RAM or the plurality of RAMs is read out. The video signals read out one by two times are converted into analog signals by a D / A conversion circuit and then input to a source signal line driving circuit, where two display signals are generated by the source signal line driving circuit. , The two display signals have inverted polarities with each other,
The two generated display signals are input to the pixel electrodes via the pixel TFTs, and during each frame period, the source signal lines adjacent to the plurality of source signal lines are set with reference to the potential of the counter electrode. Display signals having polarities opposite to each other are input, and in adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode. The period during which the video signal is written to the one RAM or any one of the plurality of RAMs is longer than the period during which the written video signal is read for the first time and the period during which the video signal is read for the second time. A semiconductor display device is provided.

According to the present invention, in a method for driving a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit, the plurality of pixel TFTs are provided via the plurality of pixel TFTs. A display signal is input to the electrode, and the frame rate conversion unit is operating in synchronization with the display signal, and, in any two adjacent frame periods, the plurality of frames in a later appearing frame period. The display signal input to the pixel electrode is a signal obtained by inverting the polarity of the display signal input to the plurality of pixel electrodes with respect to the potential of the counter electrode during a frame period that appears earlier. A method for driving a semiconductor display device is provided.

According to the present invention, in a method for driving a semiconductor display device having a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit, the plurality of pixel TFTs are provided via the plurality of pixel TFTs. A display signal is input to the electrode, and all display signals input to the plurality of pixel electrodes have the same polarity with respect to the potential of the counter electrode during each frame period, and the frame rate conversion is performed. The unit operates in synchronization with the display signal, and a display signal input to the plurality of pixel electrodes in a later appearing frame period of any two adjacent frame periods appears earlier. A semiconductor signal which is obtained by inverting a potential of a display signal input to the plurality of pixel electrodes in a frame period with reference to a potential of the counter electrode. The driving method of the device is provided.

According to the present invention, a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines,
And a display signal input to the plurality of source signal lines is input to the plurality of pixel electrodes via the plurality of pixel TFTs, and the display signal is input to the plurality of pixel electrodes during each frame period. Display signals having polarities opposite to each other with respect to the potential of the counter electrode are input to source signal lines adjacent to the plurality of source signal lines, and input to each of the plurality of source signal lines. Display signal always has the same polarity with reference to the potential of the counter electrode, the frame rate conversion unit operates in synchronization with the display signal, and any two adjacent frame periods The display signal input to the plurality of pixel electrodes in a later appearing frame period is input to the plurality of pixel electrodes in the earlier appearing frame period. The driving method of a semiconductor display device, characterized in that the potential of the display signal is a signal obtained by inverting the potential of the counter electrode as a reference that is provided.

According to the present invention, a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines,
In the method for driving a semiconductor display device having a frame rate conversion unit, a display signal input to the plurality of source signal lines is input to the plurality of pixel electrodes via the plurality of pixel TFTs, and during each line period, The display signal input to all of the plurality of source signal lines always has the same polarity with reference to the potential of the counter electrode, and is input to the plurality of source signal lines during an adjacent line period. The polarity of the display signal to be displayed is inverted with respect to the potential of the counter electrode, and the frame rate conversion unit operates in synchronization with the display signal, and is connected to any two adjacent frame periods. The display signal input to the plurality of pixel electrodes in the later appearing frame period is input to the plurality of pixel electrodes in the earlier appearing frame period. The driving method of a semiconductor display device which is a signal obtained by inverting the potential of the display signal based on the potential of the opposing electrode.

According to the present invention, a plurality of pixel TFTs, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines,
And a display signal input to the plurality of source signal lines is input to the plurality of pixel electrodes via the plurality of pixel TFTs, and the display signal is input to the plurality of pixel electrodes during each frame period. A display signal having polarities opposite to each other with respect to the potential of the counter electrode is input to a source signal line adjacent to the plurality of source signal lines. The polarity of the display signal input to the signal line is inverted with respect to the potential of the counter electrode, the frame rate conversion unit operates in synchronization with the display signal, and any adjacent Of the two frame periods, the display signal input to the plurality of pixel electrodes in the later appearing frame period is the display signal inputted in the earlier appearing frame period. The driving method of a semiconductor display device, characterized in that the potential of the display signal input to the pixel electrode is a signal obtained by inverting the potential of the counter electrode as a reference is provided.

The present invention may be characterized in that the RAM is an SDRAM.

The present invention includes a computer, a video camera, and a DVD player using the semiconductor display device.

[0083]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A frame rate conversion section of a semiconductor display device according to the present invention will be described below with reference to FIG. In this embodiment, SDRAM is used as RAM.
M (Synchronous Dynamic Random Access Memory)
Is shown. However, the present invention is not limited to a RAM, and other DRAMs (Dynamic Random Access Memory) can be used as long as high-speed data writing and reading can be performed.
emory) and SRAM (StaticRandom Access Memor)
y) can also be used.

The frame rate conversion section 100 includes the control section 1
01, a frame frequency converter 102, and an address generator 106. The frame frequency conversion unit 102 includes a first SDRAM (SDRAM1) 103,
A second SDRAM (SDRAM2) 104 and a data format unit 105 are provided. A D / A conversion circuit 107 converts a video signal output from the frame rate conversion unit 100 from digital to analog.

In the present embodiment, frame frequency conversion section 102 uses two SDRAMs (first SDRAM 10
3, the second SDRAM 104), but the SDR
The number of AMs is not limited to two, but may be any number. In this embodiment, the number of SDRAMs is two for simplicity.
Two cases will be described.

The Hsync signal, the Vsync signal, and C
The LK signal is input to the control unit 101. The control unit 10 is controlled by the Hsync signal, the Vsync signal, and the CLK signal.
1 to an address generator control signal (address generator control signal) for controlling the driving of the address generator section.
ll signal), the first SDRAM 103 and the second SD
An SDRAM control signal (RA
M CLK1 and RAM CLK2) are output.

The address generator 106 is driven by the address generator control signal input from the controller 101, and is driven by the first SDRAM 103 and the second SDRAM.
A counter value specifying the address of the memory address of the AM 104 is determined. For example, if the counter value is 0, the first SDR
The address 0 of the memory address of the AM 103 and the second SDRAM 104 is designated, the address 1 is designated if the counter value is 1, the address 2 is designated if the counter value is 2, and the q address is designated if the counter value is q.

The information of the counter value is the first counter signal (ad
dress count signal 1), second counter signal (address
As the count signal 2), the address generator 10
6 to the first SDRAM 103 and the second SDRAM 10
4 respectively. The counter value of the first counter signal is called a first counter value, and the counter value of the second counter signal is called a second counter value.

A digital video signal (Video Signal) is externally input to the data format unit 105.
The data format unit 105 is connected to an AC power supply (AC Con
t) is connected.

The digital video signal input to the data format unit 105 is the first or second SDRAM 1
03 and 104 are sequentially written to addresses designated by the first or second counter signal. A digital video signal is not always written to a plurality of SDRAMs at the same time, but is always written to only one SDRAM.

After increasing the number of bits of the digital video signal input in the data format section 105, the first SDRAM 103 or the second SDRAM 1
04 may be written.

Next, the written video signal is read out sequentially from the address specified by the first or second counter signal of the first or second SDRAM 103, 104. The digital video signal is not read from a plurality of SDRAMs at the same time, but is always read from only one SDRAM.

Note that the reading of the video signal is performed twice.
Then, the writing of the video signal to one SDRAM and the reading of the video signal from another SDRAM are performed in parallel.

The operation of the frame frequency converter 102 shown in FIG. 1 will be specifically described with reference to FIG. FIG. 2 (A)
In the example, the video signal is written to the first SDRAM 103, and the video signal written to the second SDRAM 104 is read twice at the same time. In FIG. 2B, the video signal written in the first SDRAM 103 is read twice, and at the same time, the second SDRAM 10
4 is written with a video signal.

Although the present embodiment shows an example using an SDRAM to which only a video signal corresponding to one image can be written, the present invention is not limited to this. A configuration may be employed in which a RAM capable of writing a video signal corresponding to one image or more is used. RA capable of writing video signals equivalent to two or more images
If M is used, only one RAM may be used in the present invention. Conversely, when using a RAM to which only a video signal corresponding to one image or less can be written, a video signal corresponding to one image may be written by using a plurality of RAMs.

FIG. 3 shows the timing of writing and reading of a video signal in the first SDRAM 103 and the second SDRAM 104. In the writing period p, the first
The video signal is written to the SDRAM 103. Then, the video signal written in the first SDRAM 103 in the writing period p is used in the next first reading period p.
Is read twice in the second read period p.

In the writing period (p-1), the second
The video signal is written to the SDRAM 104 of the. Then, in the writing period (p-1), the second SDRAM 10
The video signal written in No. 4 is read twice in the first readout period (p-1) and the second readout period (p-1) which appear next.

The writing period p and the first and second reading periods (p-1) appear at the same time. That is,
The video signal is read twice from the second SDRAM 104 in parallel with the video signal being written to the first SDRAM 103.

The write period (p + 1) and the first and second read periods p appear at the same time. That is, the video signal is read from the first SDRAM 103 twice in parallel with the writing of the video signal to the second SDRAM 104.

When the first and second read periods p end, a write period (p + 2) appears, and again the first SD
The video signal is written to the RAM 103. In parallel, the first and second readout periods (p + 1) appear, and the video signal is read out twice from the second SDRAM 104.

[0101] The read video signal is input to the data format unit 105. Then, in the data format unit 105, when one of the video signals read twice is converted to analog, the polarity is inverted with reference to the potential of the counter electrode of the liquid crystal,
Data is processed. Then, the two video signals, that is, the video signal subjected to the data processing and the video signal not subjected to the data processing, are output from the data format unit 105 as a processed video signal (Processed video signal).

[0102] The two video signals output from the data format unit 105 are input to the D / A conversion circuit 107 and are converted into analog signals. The D / A conversion circuit 10
7, two high and low power supply voltages are constantly applied, and two analog video signals whose polarities are inverted with respect to the potential of the counter electrode are output from the D / A conversion circuit 107. The two video signals converted to analog are sequentially input to the source signal line driving circuit.

Note that the video signal may be serial-parallel converted by the data format unit 105 and divided by the number of divisions of the division driving before input to the D / A conversion circuit 107.

The division driving is a driving method for suppressing the driving frequency of the source signal line driving circuit without lowering the image display speed. Specifically, the source signal line is set to m
This is a driving method in which display signals are divided into groups and display signals are simultaneously input to m source signal lines during one line period.

FIG. 4 shows a configuration of a pixel portion of an active matrix liquid crystal display device using the driving method of the present invention. FIG. 4A is a circuit diagram of a pixel portion, and FIG.
FIG. 3 is a diagram showing an arrangement of pixels.

Reference numeral 110 denotes a pixel portion. Source signal lines S1 to Sx connected to the source signal line drive circuit, and gate signal lines G1 to G connected to the gate signal line drive circuit
y are provided in the pixel portion 110. And the pixel unit 1
In 10, a pixel 111 is provided in a portion surrounded by source signal lines S1 to Sx and gate signal lines G1 to Gy. The pixel 111 is provided with a pixel TFT 112 and a pixel electrode 113.

The gate signal line G is supplied from the gate signal line driving circuit.
A selection signal is input to 1 to Gy, and the switching of the pixel TFT 112 is controlled by the selection signal. Note that controlling the switching of the TFT in this specification means selecting whether to turn the TFT on or off.

From the gate signal line drive circuit to the gate signal line G
1, the gate signal line G1 is selected by the selection signal, and the pixels (1, 1), (1, 2),... At the intersection of the gate signal line G1 and the source signal line S1.
The (1, x) pixel TFT 112 is turned on.

The two analog video signals having inverted polarities input to the source signal line driving circuit are sampled in order according to sampling signals from a shift register or the like in the source signal line driving circuit, and are respectively displayed as display signals on the source signal line. Input to S1 to Sx.

The display signals input to the source signal lines S1 to Sx are applied to the pixels (1,
1), (1, 2),..., (1, x). The liquid crystal is driven by the potential of the input display signal, the amount of transmitted light is controlled, and the pixels (1, 1),
(1, 2),..., (1, x) are part of the image (pixels (1,
1), (1, 2),..., (1, x).

When a display signal is input to all the pixels connected to the gate signal line G1, the gate signal line G1 is not selected. Subsequently, pixels (1, 1), (1,
2) The gate signal line G2 is selected by the selection signal input to the gate signal line G2 while the state in which the image is displayed in (1, x) is held by a storage capacitor (not shown) or the like. You. Note that the storage capacitor is a capacitor for holding the potential of the display signal input to the gate electrode of the pixel TFT 112 for a certain period. Then, all the pixels (2, 1) (2, 2),..., (2,
In x), parts of the image are similarly displayed one after another. During this time,
The gate signal line G2 continues to be selected.

The above operation is sequentially repeated for all the gate signal lines, whereby one image is displayed on the pixel portion 110. The period during which this one image is displayed is called one frame period. A period in which one image is displayed in the pixel portion 110 and a vertical blanking period may be combined into one frame period. And all the pixels are again the pixels T of each pixel.
Until the FT is turned on, the state in which the image is displayed is held by a storage capacitor (not shown) or the like.

The polarities of the two video signals are inverted, and the polarities of the sampled display signals input to the respective source signal lines are also inverted. FIG. 5 shows a timing chart of a selection signal and a display signal input to the gate signal line and the source signal line in the active matrix liquid crystal display device shown in FIG.

The line period indicates a period in which one gate signal line is selected, and all the line periods (L1
To Ly) corresponds to one frame period. Alternatively, all the line periods (L1 to Ly) and the vertical retrace period may be combined into one frame period. In the case of the active matrix type liquid crystal display device of the present invention, the former frame period (previous frame) for displaying the same image
And a latter-half frame period (following frame).

In the first half frame period, an image is displayed based on the video signal read from the SDRAM in the first read period. Then, in the latter frame period, an image is displayed based on the video signal read from the SDRAM in the second read period. Therefore, the displayed image is the same between the first and second frame periods, but the polarity of the display signal input to each source signal line is inverted.

FIG. 6 shows the polarity of the display signal input to the pixel electrode of each pixel when the frame inversion drive is performed. In FIG. 6, the first, third, and fifth frame periods correspond to the first frame period, and the second and fourth frame periods correspond to the second frame period.

In all the frame periods, the polarities of the display signals input to the pixel electrodes of all the pixels are the same.
The polarity of the display signal input to each pixel is inverted between the first frame period and the second frame period.

The displayed image is the same between the first frame period and the second frame period. The displayed image is the same between the third frame period and the fourth frame period. Although the sixth frame period is not shown, the displayed image is the same in the fifth frame period and the sixth frame period.

Next, FIG. 7 shows the polarity of the display signal input to the pixel electrode of each pixel when the source line inversion drive is performed. In FIG. 7, the first, third, and fifth frame periods correspond to the first frame period, and the second and fourth frame periods correspond to the second frame period.

In all the frame periods, the polarities of the display signals input to the pixel electrodes of the pixels connected to each source signal line are all the same. The polarity of the display signal input to the pixel electrode of the pixel connected to the adjacent source signal line is inverted. The polarity of the display signal input to each pixel is inverted between the first half frame period and the second half frame period.

The displayed image is the same in the first frame period and the second frame period. The displayed image is the same between the third frame period and the fourth frame period. Although the sixth frame period is not shown, the displayed image is the same in the fifth frame period and the sixth frame period.

Next, FIG. 8 shows the polarity of the display signal input to the pixel electrode of each pixel when the gate line inversion drive is performed. In FIG. 8, the first, third, and fifth frame periods correspond to the first frame period, and the second and fourth frame periods correspond to the second frame period.

In all the frame periods, the polarities of the display signals input to the pixel electrodes of the pixels connected to each gate signal line are all the same. The polarity of the display signal input to the pixel electrode of the pixel connected to the adjacent gate signal line is inverted. The polarity of the display signal input to each pixel is inverted between the first half frame period and the second half frame period.

The displayed image is the same between the first frame period and the second frame period. The displayed image is the same between the third frame period and the fourth frame period. Although the sixth frame period is not shown, the displayed image is the same in the fifth frame period and the sixth frame period.

Next, FIG. 9 shows the polarity of the display signal input to the pixel electrode of each pixel when the dot inversion drive is performed. In FIG. 9, the first, third, and fifth frame periods correspond to the first frame period, and the second and fourth frame periods correspond to the second frame period.

In all the frame periods, the polarities of the display signals input to the pixel electrodes of the adjacent pixels are all inverted. The polarity of the display signal input to each pixel is inverted between the first half frame period and the second half frame period.

The displayed image is the same in the first frame period and the second frame period. The displayed image is the same between the third frame period and the fourth frame period. Although the sixth frame period is not shown, the displayed image is the same in the fifth frame period and the sixth frame period.

According to the present invention, the frequency of the video signal read from the SDRAM can be made higher than the frequency of the video signal before being written to the SDRAM by the above configuration. Therefore, the frame frequency can be increased inside the active matrix type liquid crystal display device without increasing the frequency of the video signal input from the outside, so that a burden is imposed on the electronic device that generates the video signal. In addition, it is possible to display a clear and high-definition image in which a flicker, vertical stripes, horizontal stripes, and oblique stripes are hardly visually recognized by an observer.

Further important in the present invention is SDR
In other words, the potential of one of the video signals read out twice from the AM is inverted with reference to the potential of the counter electrode (counter potential) and input to the source signal line drive circuit. Therefore, in two consecutive frame periods, the potential of the display signal input to each pixel is inverted with reference to the potential of the counter electrode (counter potential), and the same image is displayed in the pixel portion. With the above structure, the temporal average of the potential of the display signal input to each pixel becomes closer to the opposite potential, and the deterioration of the liquid crystal is reduced as compared with the case where different display signals are input to each pixel in each frame period. It is more effective to prevent such a phenomenon, and it is difficult for an observer to visually recognize flickers, vertical stripes, horizontal stripes and oblique stripes.

Further, by using frame inversion in the present invention, it is possible to suppress the occurrence of a phenomenon stripe called disclination between adjacent pixels and to prevent the brightness of the entire display screen from being reduced. .

Although the above-described driving method has been described using an example using non-interlace scanning, the scanning method of the present invention is not limited to this. The scanning method may be interlace scanning.

Also, in this embodiment, two high and low power supply voltages are constantly given to the D / A conversion circuit,
Two analog video signals with inverted polarities are output from the D / A conversion circuit, and one of them is selected by an analog switch or the like. However, the method of inverting the polarity of the video signal is not limited to this, and a known method can be used. For example, before input to the D / A conversion circuit, the inverted polarities may be included as information in two digital video signals. Also, by controlling the height of the power supply voltage applied to the D / A conversion circuit, the polarities of two analog video signals continuously output from the D / A conversion circuit may be inverted. .

[0133]

Embodiments of the present invention will be described below.

(Embodiment 1) In this embodiment, an example different from that of FIG. 3 will be described with respect to the timing of writing and reading of the video signal in the first SDRAM 103 and the second SDRAM 104 of FIG.

In this embodiment, the first and second read periods are shorter than the write period. Then, after the first and second reading periods are completed, before the next writing period is started, a blank period in which neither writing nor reading of a video signal is performed is provided.

FIG. 10 shows the first SDRAM 103 and the second
2 shows the timing of writing and reading of a video signal in the SDRAM 104 of FIG. A video signal is written to the first SDRAM 103 in the writing period p. Then, the video signal written to the first SDRAM 103 in the writing period p is read twice in the first reading period p and the second reading period p.

In the writing period (p-1), the second
The video signal is written to the SDRAM 104 of the. Then, in the writing period (p-1), the second SDRAM 10
4 is written in the first readout period (p−
1) and two times during the second read period (p-1).

The writing period p and the first and second reading periods (p-1) appear at the same time. That is,
The video signal is read twice from the second SDRAM 104 in parallel with the video signal being written to the first SDRAM 103.

Further, the writing period (p + 1) and the first and second reading periods p appear at the same time. That is, the video signal is read from the first SDRAM 103 twice in parallel with the writing of the video signal to the second SDRAM 104.

When the first and second readout periods p end, a blank period appears. The blank period is a period during which neither writing nor reading of a video signal is performed. When the blank period ends, a write period (p + 2) appears, and the video signal is written to the first SDRAM 103 again. At the same time, the first and second readout periods (p
+1) appears, and the video signal is read twice from the second SDRAM 104.

The length of the blank period needs to be longer than the length obtained by subtracting the first and second read periods from the write period. Any number of blank periods may be provided as long as the image does not flicker. By providing a blank period, a video signal is not written to two or more SDRAMs, and a video signal is not read from two or more SDRAMs.

The blank period is the same as the write period and the first period.
It may be provided between the reading period or between the second reading period and the writing period. Further, it may be provided between the first reading period and the second reading period.

The video signal read twice is input to the data format unit 105.

(Embodiment 2) In this embodiment, the timings of writing and reading video signals in the first SDRAM 103 and the second SDRAM 104 of FIG. 1 will be described, which are different from those shown in FIGS.

In this embodiment, the first and second read periods are longer than the write period. Then, after the writing period ends, before the next first reading period starts, a blank period in which neither writing nor reading of the video signal is performed is provided.

FIG. 11 shows the first SDRAM 103 and the second
2 shows the timing of writing and reading of a video signal in the SDRAM 104 of FIG. A video signal is written to the first SDRAM 103 in the writing period p. When the writing period p ends, a blank period appears. The blank period is a period during which neither writing nor reading of a video signal is performed.

After the blank period ends, the video signal written to the first SDRAM 103 in the writing period p is read twice in the first reading period p and the second reading period p.

In the writing period (p-1), the second
The video signal is written to the SDRAM 104 of the. When the writing period (p-1) ends, a blank period appears. After the blanking period, the video signal written to the second SDRAM 104 in the writing period (p-1) is read twice in the first reading period (p-1) and the second reading period (p-1).

The writing period p and the first and second reading periods (p-1) appear at the same time. That is,
The video signal is read twice from the second SDRAM 104 in parallel with the video signal being written to the first SDRAM 103.

Further, the writing period (p + 1) and the first and second reading periods p appear at the same time. That is, the video signal is read from the first SDRAM 103 twice in parallel with the writing of the video signal to the second SDRAM 104.

When the first and second reading periods p end, a writing period (p + 2) appears, and a video signal is written into the first SDRAM 103 again. In parallel, the first and second readout periods (p + 1) appear, and the video signal is read out twice from the second SDRAM 104.

It is necessary that the length of the blank period is longer than the length obtained by subtracting the write period from the sum of the first read period and the second read period. Any number of blank periods may be provided as long as the image does not flicker. By providing a blank period, a video signal is not written to two or more SDRAMs, and a video signal is not read from two or more SDRAMs.

The blank period is the same as the write period and the first period.
It may be provided between the reading period or between the second reading period and the writing period. Further, it may be provided between the first reading period and the second reading period.

The video signal read twice is input to the data format unit 105.

This embodiment can be freely combined with Embodiment 1.

(Embodiment 3) In this embodiment, an example of a frame rate conversion section included in the semiconductor display device of the present invention, which is different from FIG. 1, will be described with reference to FIG.

In this embodiment, the frame rate converter has three SDRAMs.

The frame rate conversion section 200 includes the control section 2
01, a frame frequency conversion unit 202, and an address generator unit 206. The frame frequency conversion unit 202 includes a first SDRAM (SDRAM1) 203,
Second SDRAM (SDRAM2) 204, Third SD
A RAM (SDRAM 3) 207 and a data format unit 205 are provided. A D / A conversion circuit 208 converts a video signal output from the frame rate conversion unit 200 from digital to analog.

In this embodiment, the frame frequency converter 2
02 has three SDRAMs (the first SDRAM 203, the second SDRAM 204, and the third SDRAM 207), but the number of SDRAMs is not limited to three.

The Hsync signal, the Vsync signal, and C
The LK signal is input to the control unit 201. The control unit 20 is controlled by the Hsync signal, the Vsync signal, and the CLK signal.
1 to an address generator control signal (address generator control signal) for controlling the driving of the address generator section.
ll signal), the first SDRAM 203 and the second SD
SDRAM control signals (RAM CLK1, RAM CLK2, RAM CLK) for controlling the driving of the RAM 204 and the third SDRAM 207.
3) is output.

The address generator unit 206 is driven by an address generator control signal input from the control unit 201, and is driven by the first SDRAM 203 and the second SDRAM.
A counter value for specifying the address of the memory address of the AM 204 and the third SDRAM 207 is determined. For example, if the counter value is 0, the first SDRAM 203 and the second SDRA
The memory address of the M204 and the third SDRAM 207 is specified as address 0, the address 1 is specified when the counter value is 1, the address 2 when the counter value is 2, and the address q when the counter value is q. The information on the counter value includes a first counter signal (addresscount signal 1) and a second counter signal (a
ddress count signal 2), third counter signal (address
address signal 2 as count signal 3)
06 to the first SDRAM 203 and the second SDRAM 2
04 and the third SDRAM 207.

The counter value of the first counter signal is called the first counter value, the counter value of the second counter signal is called the second counter value, and the counter value of the third counter signal is called the third counter value.

A digital video signal (Video Signal) is input to the data format section 205. The data format unit 205 is connected to an AC power supply (AC Cont).

The digital video signal input to the data format unit 205 is transmitted to the first SDRAM 203,
Are sequentially written to designated addresses of the SDRAM 204 or the third SDRAM 207. A digital video signal is not always written to a plurality of SDRAMs at the same time, but is always written to only one SDRAM.

In the data format unit 205, after increasing the number of bits of the input digital video signal, the first SDRAM 203 and the second SDRAM
The data may be written to the second SDRAM 204 or the third SDRAM 207.

The video signal written next is the first SD
RAM 203, second SDRAM 204 or third S
The data is sequentially read from the designated address of the DRAM 207. The digital video signal is not read from a plurality of SDRAMs at the same time, but is always read from only one SDRAM.

The reading of the video signal is performed twice.
Then, the writing of the video signal to one SDRAM and the reading of the video signal from another SDRAM are performed in parallel.

FIG. 13 shows the first SDRAM 203 and the second SDRAM 203.
The timing of writing and reading of video signals in the SDRAM 204 and the third SDRAM 207 are shown.

In the writing period p, the first SDRAM
A video signal is written to 203. Then, the video signal written to the first SDRAM 203 in the writing period p is read twice in the first reading period p and the second reading period p.

In the writing period (p-1), the second
The video signal is written into the SDRAM 204. Then, in the writing period (p-1), the second SDRAM 20
4 is written in the first readout period (p−
1) and two times during the second read period (p-1).

In the writing period (p + 1), the third
The video signal is written to the SDRAM 207 of the. Then, in the writing period (p + 1), the third SDRAM 20
The video signal written in the first readout period (p +
1) and the second read period (p + 1) is read twice.

The writing period p and the first and second reading periods (p-1) appear simultaneously. That is,
The video signal is read twice from the second SDRAM 204 in parallel with the video signal being written to the first SDRAM 203.

The write period (p + 1) and the first and second read periods p appear at the same time. That is, the video signal is read twice from the first SDRAM 203 in parallel with the video signal being written to the third SDRAM 207.

The writing period (p + 2) and the first and second reading periods (p + 1) appear simultaneously. That is, the video signal is read from the third SDRAM 207 twice in parallel with the video signal being written to the second SDRAM 204.

When the first and second readout periods p end, a blank period appears. During the blank period of the first SDRAM 203, the second SDRAM 204 is in the writing period (p + 2), and the third SDRAM 207 is in the first and second reading periods (p + 1).

When the first and second read-out periods (p-1) end, a blank period appears. Second SDRAM 2
04 during the blank period, the third SDRAM 207 is in the write period (p + 1), and the first SDRAM 203
During the first and second readout periods p.

When the first and second readout periods (p + 1) are completed, a blank period appears. Third SDRAM 2
07, the first SDRAM 203 is in the writing period (p + 3), and the second SDRAM 204 is in the writing period (p + 3).
During the first and second readout periods (p + 2).

First SDRAM 203, Second SDRA
In the M204 and the third SDRAM 207, when the blank period ends, the next write period starts.

The video signal read twice is input to the data format unit 205. Then, in the data format unit 205, one of the video signals read out twice is subjected to data processing so that the polarity is inverted with respect to the potential of the counter electrode of the liquid crystal when converted into analog. Is done. Then, two video signals, a video signal subjected to data processing and a video signal not subjected to data processing, are output from the data format unit 205.

The two video signals output from the data format unit 205 are input to a D / A conversion circuit 208 and are converted into analog signals. The two video signals converted into analog have inverted polarities with reference to the potential of the counter electrode. The two video signals converted to analog are sequentially input to the source signal line driving circuit.

Note that the data format section 205 may perform serial-parallel conversion on the video signal, divide the video signal by the number of divisions of the division drive, and then input the divided signal to the D / A conversion circuit 208.

The structure of the active matrix type liquid crystal display device using the driving method of the present invention and the polarity of the display signal input to the pixel portion are the same as those shown in FIGS. The description is omitted in the embodiment.

In this embodiment, the first SD shown in FIG.
RAM 203, second SDRAM 204, and third SDR
Writing and reading of a video signal in the AM 207 are performed as follows.
It is not always performed at the timing shown in FIG. The first and second read periods may be longer or shorter than the write period. However, two or more SD
Video signals are written to RAM, and two or more S
It is important to adjust the length of the blank period so that the video signal is not read from the DRAM.

The blank period includes the writing period and the first period.
It may be provided between the reading period or between the second reading period and the writing period. Further, it may be provided between the first reading period and the second reading period.

The video signal read twice is input to the data format unit 205.

(Embodiment 4) In this embodiment, a detailed configuration of a semiconductor display device of the present invention driven by an analog system will be described. FIG. 14 is a block diagram showing an example of a semiconductor display device of the present invention driven by an analog method.

Reference numeral 301 denotes a source signal line driving circuit, 302 denotes a gate signal line driving circuit, and 303 denotes a pixel portion.
In this embodiment, one source signal line driving circuit and one gate signal line driving circuit are provided, but the present invention is not limited to this configuration. Two source signal line driving circuits may be provided,
Two gate signal line driver circuits may be provided.

[0188] The source signal line driver circuit 301 includes a shift register 301_1, a level shift 301_2, and a sampling circuit 301_3. Level shift 3
01_2 may be used as needed and need not be used. In the present embodiment, the level shift 301
_2 is the shift register 301_1 and the sampling circuit 3
01_3, the present invention is not limited to this configuration. A structure in which the level shift 301_2 is incorporated in the shift register 301_1 may be employed.

[0189] In the pixel portion 303, a source signal line 304 connected to the source signal line driver circuit 301 and a gate signal line 306 connected to the gate signal line driver circuit 302 intersect. In a region surrounded by the source signal line 304 and the gate signal line 306, a thin film transistor (pixel TFT) 307 of the pixel 305, a liquid crystal cell 308 having liquid crystal interposed between a counter electrode and a pixel electrode, and a storage capacitor 309 Is provided. Note that this embodiment shows a configuration in which the storage capacitor 309 is provided; however, the storage capacitor 309 is not necessarily provided.

The gate signal line driving circuit 302 has a shift register and a buffer (both not shown). Further, a level shift may be provided.

A source clock signal (S-CLK) and a source start pulse signal (S-SP), which are panel control signals, are input to the shift register 301_1. A sampling signal for sampling the display signal is output from the shift register 301_1. The output sampling signal is input to the level shift 301_2, and is output with its potential amplitude increased.

The sampling signal output from the level shift 301_2 is input to a sampling circuit 301_3. At the same time, a video signal is input to the sampling circuit 301_3 via a video signal line (not shown).

In the sampling circuit 301_3, the input video signal is sampled by the sampling signal, and the source signal line 304 is displayed as a display signal.
Is input to

The pixel TFT 307 is turned on by a selection signal input from the gate signal line driving circuit 302 via the gate signal line 306. The display signal sampled and input to the source signal line 304 is input to the pixel electrode of a predetermined pixel 305 via the pixel TFT 307 in an ON state.

The liquid crystal is driven by the potential of the input display signal, the amount of transmitted light is controlled, and a part of an image (an image corresponding to each pixel) is displayed on the pixel 305.

This embodiment can be freely combined with Embodiments 1 to 3.

Embodiment 5 In this embodiment, a detailed circuit configuration of the source signal line driving circuit 301 shown in Embodiment 4 will be described. Note that the source signal line driver circuit described in Embodiment 4 is not limited to the configuration described in Embodiment 4.

FIG. 15 is a circuit diagram of the source signal line driving circuit of this embodiment. 301_1 is a shift register, 301
_2 indicates a level shift, and 301_3 indicates a sampling circuit.

A source clock signal S-CLK, a source start pulse signal S-SP, and a drive direction switching signal SL / R are input to the shift register 301_1 from the wirings shown in the figure. The video signal is input to the sampling circuit 301_3 through the video signal line 310. In the present embodiment, an example in the case of divided driving with four divisions is shown. Therefore, there are four video signal lines 310. However, the present embodiment is not limited to this configuration, and the number of divisions can be arbitrarily determined.

The video signal input to each video signal 310 is sampled in a sampling circuit 301_3 by a sampling signal input from a level shift 301_2. Specifically, the video signal is sampled by the analog switch 311 included in the sampling circuit 301_3, and is simultaneously input to the corresponding source signal lines 304_1 to 304_4.

By repeating the above operation, display signals are input to all the source signal lines.

FIG. 16A is an equivalent circuit diagram of the analog switch 311. The analog switch 311 has an n-channel TFT and a p-channel TFT. A video signal is input as Vin from the wiring shown in the figure. Then, a sampling signal output from the level shift 301_2 and a signal having a polarity opposite to that of the sampling signal are input from IN or INb, respectively. The video signal is sampled by this sampling signal,
It is output from Vout as a display signal.

FIG. 16B is an equivalent circuit diagram of the level shift 301_2. A sampling signal output from the shift register 301_1 and a signal having a polarity opposite to that of the sampling signal are input from Vin or Vinb, respectively. Vddh is a plus voltage, Vss
Indicates the application of a negative voltage. Level shift 3
01_2 is designed so that a signal obtained by increasing the voltage of the signal input to Vin and inverting the signal is output from Voutb. That is, when Hi is input to Vin, Vou
When a signal corresponding to Vss is input from tb, when Vo is input, Vo
utb outputs a signal corresponding to Vddh.

This embodiment can be freely combined with Embodiments 1 to 4.

(Embodiment 6) A frame rate converter provided in a semiconductor display device of the present invention will be described below with reference to FIG.

A frame rate conversion unit 100 shown in FIG.
Is the same as that shown in FIG. 1, and therefore, the detailed description of the operation and configuration will refer to the embodiment. However,
In the present embodiment, the video signal output from the frame rate conversion unit 100 is not input to the D / A conversion circuit, but is input digitally to the source signal line drive circuit.

Note that the number of SDRAMs is not limited to two.
Any number of two or more may be used.

A semiconductor display device driven by a digital method used in this embodiment will be described with reference to FIG.

FIG. 18 is a block diagram of a semiconductor display device of the present invention driven by a digital method. Here, a 4-bit digital drive type semiconductor display device is taken as an example. The digital drive type semiconductor display device used in this embodiment is not limited to the structure shown in FIG. The semiconductor display device may have any structure as long as display can be performed using a digital video signal.

[0210] As shown in FIG. 18, a digital drive type semiconductor display device includes a source signal line drive circuit 412, a gate signal line drive circuit 409, and a pixel portion 413.

[0211] The source signal line driving circuit 412 includes a shift register 401, a latch 1 (LAT1) 403, and a latch 2
(LAT2) 404 and a D / A conversion circuit 406 are provided. A digital video signal is input from the frame rate conversion unit 100 to the address lines 402 (a to d).

The address lines 402 (a to d) are connected to the latch 1
(LAT1) 403. A latch pulse line 405 is connected to the latch 2 (LAT2) 404. Further, a gradation voltage line 407 is connected to the D / A conversion circuit 406.

In this embodiment, each of the latches 1 403 and 2 404 (LAT1 and LAT2) has four latches collectively shown for convenience.

The D / D of the source signal line driving circuit 412
A source signal line 408 connected to the A conversion circuit 406,
A gate signal line 410 connected to the gate signal line driver circuit 409 is provided in the pixel portion 413.

In the pixel portion 413, the source signal line 40
8 and the gate signal line 410 intersect with the pixel 41
5 is provided, and the pixel 415 has a pixel TFT 411 and a liquid crystal cell 414.

The digital video signals supplied to the address lines 402 (a to d) are sequentially written to all the LATs 403 according to the timing signal from the shift register 401. In this specification, all LAT1
403 is generally referred to as LAT1 group.

The period until the writing of the digital video signal to the LAT1 group is completely completed is called one line period. That is, after the writing of the digital video signal to the leftmost LAT 1 is started, the rightmost LA
The period up to the end of the writing of the digital video signal to T1 is one line period. Note that the period until the writing of the digital video signal to the LAT1 group is completely completed and the horizontal retrace period may be combined into one line period.

After the writing of the digital video signal to the LAT1 group is completed, the digital video signal written to the LAT1 group is transmitted to all the LAT2 404 simultaneously by the latch signal input to the latch pulse line 405. Is written. In this specification, all LAT2s are collectively referred to as a LAT2 group.

After transmitting the digital video signal to the LAT2 group, the second line period starts. Therefore, the timing signal from the shift register 401 causes L
Digital video signals supplied to the address lines 402 (a to d) are sequentially written to the AT1 group.

At the start of the second-order one-line period, the digital video signal written to the LAT2 group is
/ A conversion circuit 406. Then, the input digital video signal is input to the D / A conversion circuit 406 all at once. The input digital video signal is converted in a D / A conversion circuit 406 into an analog display signal having a voltage corresponding to image information of the digital video signal, and input to a source signal line 408.

The switching of the corresponding pixel TFT 411 is performed by the selection signal output from the gate signal line driving circuit 409, and the liquid crystal molecules are driven by the analog display signal input to the source signal line 408.

In this embodiment, the polarity of the analog display signal output from the D / A conversion circuit 406 is changed by changing the value of the video signal input to the address line 402 for each frame period. .

This embodiment can be freely combined with Embodiments 1 to 3.

(Embodiment 7) One of the semiconductor display devices of the present invention
One example of a method for manufacturing a liquid crystal display device is shown in FIG.
This will be described with reference to FIGS. Here, a pixel TFT and a storage capacitor of a pixel portion and a TFT of a source signal line driver circuit and a gate signal line driver circuit provided around the pixel portion are provided.
Will be described in detail according to the steps.

In FIG. 19A, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass, a quartz substrate, or the like is used as a substrate 501. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, a base film 502 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 501 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 501. For example,
A silicon oxynitride film 502a formed from SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method is hydrogenated from 10 to 200 nm (preferably 50 to 100 nm), and similarly is a hydrogen oxynitride formed from SiH ₄ and N ₂ O. Silicon film 502b
It is formed to have a thickness of 200 nm (preferably 100 to 150 nm). Here, the base film 502 is shown as having a two-layer structure, but may be formed as a single-layer film of the insulating film or a stack of two or more layers.

The silicon oxynitride film 502a is formed by using a parallel plate type plasma CVD method. The silicon oxynitride film 502a is made of 10 SCCM for SiH ₄ and 100 SC for NH ₃ .
CM and N ₂ O were introduced into the reaction chamber at 20 SCCM, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm.
^{2. The} discharge frequency was 60 MHz. On the other hand, the hydrogenated silicon nitride oxide film 502b is an SiH ₄ 5 SCCM, the N ₂ O 120
SCCM, was introduced into the reaction chamber of H ₂ as a 125 SCCM, a substrate temperature of 400 ° C., a reaction pressure 20 Pa, discharge power density 0.41W /
It was formed under the conditions of cm ² and a discharge frequency of 60 MHz. These films can be continuously formed only by changing the substrate temperature and switching the reaction gas.

The silicon oxynitride film 502a thus manufactured has a density of 9.28 × 10 ²² / cm ³ , 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride (NH ₄ HF ₂ ). 20% of a mixed solution containing 15.4% of NH ₄ F) (trade name: LAL500, manufactured by Stella Chemifa).
The etching rate at a temperature of ° C is as low as about 63 nm / min, and the film is dense and hard. The use of such a film as a base film is effective in preventing an alkali metal element from a glass substrate from diffusing into a semiconductor layer formed thereover.

Next, 25 to 80 nm (preferably 30 to 6 nm)
Amorphous semiconductor layer 50 having an amorphous structure with a thickness of 0 nm).
3a is formed by a method such as a plasma CVD method or a sputtering method. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Amorphous semiconductor layer 503 by plasma CVD
When an amorphous silicon film is formed as a, both the base film 502 and the amorphous semiconductor layer 503a can be formed continuously. For example, as described above, the silicon oxynitride film 502a and the hydrogenated silicon oxynitride film 502b
Is continuously formed by a plasma CVD method, and then the reaction gas is Si.
H _4, N ₂ O, be switched from H ₂ only SiH ₄ and H ₂ or SiH _4, once can be continuously formed without exposure to the atmosphere. As a result, the hydrogenated silicon oxynitride film 502b
To prevent contamination of the surface of the TFT
Characteristic variation and fluctuations in the threshold voltage can be reduced.

Then, a crystallization step is performed to form a crystalline semiconductor layer 503b from the amorphous semiconductor layer 503a. Laser annealing, thermal annealing (solid phase growth), or rapid thermal annealing (RTA)
Law) can be applied. When a glass substrate or a plastic substrate having low heat resistance as described above is used, it is particularly preferable to apply a laser annealing method. RT
In the method A, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652, the crystalline semiconductor layer 50 is formed by a crystallization method using a catalytic element.
3b can also be formed. First, in the crystallization process,
It is preferable to release the hydrogen contained in the amorphous semiconductor layer, and heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen contained to 5 atom% or less. It is good because it can be prevented.

In the step of forming an amorphous silicon film by plasma CVD, SiH ₄ and argon (Ar) are used as reaction gases, and the substrate temperature during film formation is 400 to 450 ° C.
When formed, the hydrogen concentration in the amorphous silicon film can be reduced to 5 atomic% or less. In such a case, heat treatment for releasing hydrogen is unnecessary.

When crystallization is performed by laser annealing, a pulse oscillation type or continuous oscillation type excimer laser or argon laser is used as the light source. When a pulse oscillation type excimer laser is used, laser annealing is performed by processing a laser beam into a linear shape. Laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 30 to
0 to 400 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 50 to 90%. In this way, as shown in FIG.
03b can be obtained.

The first semiconductor layer is formed on the crystalline semiconductor layer 503b.
Using a photomask (PM1), a resist pattern is formed using photolithography technology, and the crystalline semiconductor layer is divided into islands by dry etching.
As shown in FIG. 9C, island-shaped semiconductor layers 504 to 508 are formed. CF for dry etching of crystalline silicon film
A mixed gas of ₄ and O ₂ is used.

In order to control the threshold voltage (Vth) of the TFT, an impurity element imparting a p-type is added to such an island-shaped semiconductor layer in an amount of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . The concentration may be added to the entire surface of the island-shaped semiconductor layer. The impurity element imparting p-type to the semiconductor includes boron (B),
Elements of Group 13 of the periodic table, such as aluminum (Al) and gallium (Ga), are known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for treating a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

[0234] The gate insulating film 509 is formed of a silicon-containing insulating film with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, 120
It is formed from a silicon oxynitride film with a thickness of nm. Also, S
A silicon oxynitride film formed by adding O ₂ to iH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. In addition, SiH ₄
A silicon oxynitride film formed from N ₂ O and H ₂ is preferable because the interface defect density of the gate insulating film can be reduced. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, TEO is
Mixing S (Tetraethyl Orthosilicate) and O ₂ , reacting at a pressure of 40 Pa, a substrate temperature of 300 to 400 ° C., and discharging at a high frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ^2. Can be. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C. (FIG. 19C)

Then, as shown in FIG.
A heat-resistant conductive layer 511 for forming a gate electrode is formed with a thickness of 200 to 400 nm (preferably 250 to 350 nm) on the gate insulating film 509 having the shape of FIG. The heat-resistant conductive layer 511 may be formed as a single layer, or may have a stacked structure including a plurality of layers such as two layers or three layers as necessary. The heat-resistant conductive layer includes an element selected from Ta, Ti, and W, an alloy containing the above element, or an alloy film combining the above elements. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained therein in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. In this embodiment, a W film is formed to a thickness of 300 nm. The W film may be formed by sputtering using W as a target, or may be formed by thermal CVD using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, the crystallization is inhibited and the resistance is increased. From this, in the case of using the sputtering method, a W target having a purity of 99.9999% or 99.99% is used, and furthermore, it is necessary to pay sufficient attention to prevent impurities from being mixed in the gas phase during film formation.
By forming a film, a resistivity of 9 to 20 μΩcm can be realized.

On the other hand, when a Ta film is used for the heat-resistant conductive layer 511, it can be similarly formed by a sputtering method. The Ta film uses Ar as a sputtering gas. Also, if an appropriate amount of Xe or Kr is added to the gas during sputtering,
The internal stress of the film to be formed can be relaxed to prevent the film from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode.
The resistivity of the film was about 180 μΩcm, and was not suitable for use as a gate electrode. Since the TaN film has a crystal structure close to the α-phase, if a TaN film is formed under the Ta film, an α-phase Ta film can be easily obtained. Although not shown, phosphorus (P) having a thickness of about 2 to 20 nm is formed under the heat-resistant conductive layer 511.
It is effective to form a silicon film doped with a. Accordingly, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the heat-resistant conductive layer 511 diffuses into the first shape gate insulating film 509. Can be prevented. In any case, the heat-resistant conductive layer 511 has a resistivity of 10 to 50 μΩ.
It is preferred to be within the range of cm.

Next, using the second photomask (PM2), resist masks 512 to 517 are formed by photolithography. Then, a first etching process is performed. In this embodiment, an ICP etching apparatus is used, and Cl ₂ and CF ₄ are used as etching gases.
A plasma is formed by applying an RF (13.56 MHz) power of 3.2 W / cm ² at a pressure of 1 Pa. RF (13.56 MHz) power of 224 mW / cm ² is also applied to the substrate side (sample stage), whereby a substantially negative self-bias voltage is applied. Under these conditions, the etching rate of the W film is about 100 nm / m
in. The first etching process estimates the time when the W film is just etched based on the etching rate,
The time obtained by increasing the etching time by 20% was defined as the etching time.

[0238] Conductive layers 518 to 523 having a first tapered shape are formed by the first etching process. The angle of the tapered portion of the conductive layers 518 to 523 is 15 to 30 °
It is formed so that In order to perform etching without leaving a residue, over-etching is performed to increase the etching time at a rate of about 10 to 20%. The selectivity of the silicon oxynitride film (the first shape gate insulating film 509) to the W film is 2 to 4 (typically 3).
Therefore, the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 nm by the over-etching, and the conductive layers 518 to 523 having the first tapered shape are formed.
A second shape gate insulating film 580 having a tapered shape is formed near the end of the gate insulating film 580.

[0239] Then, a first doping process is performed to add an impurity element of one conductivity type to the island-shaped semiconductor layer. Here, a step of adding an n-type impurity element is performed. First
The masks 512 to 517 on which the conductive layers having the shapes shown in FIGS.
Using 523 as a mask, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method. An impurity element for imparting n-type is formed in the tapered portion at the end of the gate electrode by a second step.
Through the gate insulating film 580 of the shape, and the dose of ^{1 × 10 13 ~5 × 10 14} atoms / cm 2 in order to add to reach the semiconductor layer located thereunder, the acceleration voltage 8
The operation is performed at 0 to 160 keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. By such an ion doping method, the first impurity regions 524 to 528 have 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / c.
the impurity element is added that imparts n-type conductivity in a concentration range of m ^3,
Second impurity region (A) formed below the tapered portion
To 529 to 533, an impurity element imparting n-type is added in a concentration range of 1 × 10 ¹⁷ to 1 × 10 ²⁰ atomic / cm ³ although it is not necessarily uniform in the same region. (FIG. 20A)

In this step, in the second impurity regions (A) 529 to 533, the change in the concentration of the impurity element imparting n-type contained in at least the portion overlapping the first shape conductive layers 518 to 523 is as follows: This reflects the change in the thickness of the tapered portion. That is, the second impurity region (A) 529
The concentration of phosphorus (P) added to the conductive layers 533 to 533 gradually decreases in the region overlapping with the conductive layers 518 to 523 of the first shape from the end of the conductive layer toward the inside. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes depending on the difference in the thickness of the tapered portion.

Next, a second etching process is performed as shown in FIG. The etching process is also performed using an ICP etching apparatus, and CF ₄ and C are used as etching gases.
RF power 3.2 W / cm ² (13.56 MHz) using l ₂ mixed gas
z), bias power 45mW / cm ² (13.56MHz), pressure 1.0P
Etching is performed with a. Conductive layers 540 to 545 having the second shape formed under these conditions are formed. A tapered portion is formed at the end, and the tapered shape gradually increases inward from the end. As compared with the first etching process, the ratio of the isotropic etching is increased by the lower bias power applied to the substrate side, and the angle of the tapered portion is 30 to 60 °. Mask 512-5
17 is etched and the end is scraped, and the masks 534 to 5
39. The surface of the second shape gate insulating film 580 is etched by about 40 nm, and a third shape gate insulating film 570 is newly formed.

Then, an impurity element for imparting n-type is doped under the condition of a high acceleration voltage with a lower dose than in the first doping process. For example, when the accelerating voltage is 70 to 120
KeV is applied at a dose of 1 × 10 ¹³ / cm ^{2 so} that the impurity concentration of a region overlapping the conductive layers 540 to 545 having the second shape is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ^3. To Thus, the second impurity region (B) 54
6 to 550 are formed.

Then, impurity regions 556 and 557 of a conductivity type opposite to one conductivity type are formed in the island-shaped semiconductor layers 504 and 506 forming the p-channel TFT. In this case also the second
By using the conductive layers 540 and 542 having the above-mentioned shape as a mask, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner. At this time, the island-shaped semiconductor layers 505, 507, and 508 forming the n-channel TFT are formed by using resist masks 551 to 55 using a third photomask (PM3).
3 is formed and the entire surface is covered. The impurity regions 556 and 557 formed here are formed by an ion doping method using diborane (B ₂ H ₆ ). The concentration of the impurity element imparting p-type in impurity regions 556 and 557 is 2 × 10 ²⁰ to 2 ×
It is set to 10 ²¹ atoms / cm ³ .

However, the impurity regions 556,
Numeral 57 designates 3 containing an impurity element imparting n-type.
It can be divided into two areas. The third impurity regions 556a and 557a are 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm.
An impurity element imparting n-type at a concentration of ³ is contained, and the fourth impurity regions (A) 556b and 557b are 1 × 10 ¹⁷ to 1 ×
The fourth impurity region (B) 556c, 557c contains an impurity element imparting n-type at a concentration of 10 ²⁰ atoms / cm ³ ,
It contains an impurity element imparting n-type at a concentration of × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ . However, the concentration of the impurity element imparting p-type in these impurity regions 556b, 556c, 557b, and 557c is set to 1 × 10 ¹⁹ atoms / cm ³ or more, and in the third impurity regions 556a and 557a, By setting the concentration of the impurity element imparting the type to be 1.5 to 3 times the concentration of the impurity element imparting the n-type, the p-channel type TF is formed in the third impurity region.
There is no problem because it functions as the source and drain regions of T. Further, a fourth impurity region (B)
The portions 556c and 557c partially overlap with the conductive layer 540 or 542 having the second tapered shape.

Thereafter, as shown in FIG.
The first interlayer insulating film 558 is formed on the conductive layers 540 to 545 having the shapes described above and the gate insulating film 570. First
The interlayer insulating film 558 may be formed of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first interlayer insulating film 558 is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 558 is 100 to 200 nm. When a silicon oxide film is used as the first interlayer insulating film 558, TEOS and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is used. It can be formed by discharging at 0.5 to 0.8 W / cm ² . In the case where a silicon oxynitride film is used as the first interlayer insulating film 558, a silicon oxynitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a plasma CVD method, or a silicon oxynitride film formed from SiH ₄ and N ₂ O is used. What is necessary is just to form with the manufactured silicon oxynitride film. The manufacturing conditions in this case are a reaction pressure of 20 to 200 Pa and a substrate temperature of 300.
~ 400 ° C, high frequency (60MHz) power density 0.1 ~
It can be formed at 1.0 W / cm ² . Alternatively, as the first interlayer insulating film 558, a silicon oxynitride hydride film formed using SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, the silicon nitride film is made of SiH ₄ and NH ₃ by a plasma CVD method.
It is possible to produce from.

Then, a step of activating the n-type or p-type imparting impurity element added at each concentration is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
The heat treatment is performed at 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours.
When a plastic substrate having a low heat-resistant temperature is used as the substrate 501, a laser annealing method is preferably used.

Following the activation step, the atmosphere gas was changed.
And in an atmosphere containing 3 to 100% hydrogen,
Heat treatment at 450 ° C. for 1 to 12 hours to form an island-shaped semiconductor layer
Is carried out. This process was thermally excited
10 in the island-like semiconductor layer due to hydrogen¹⁶-10¹⁸/cm^ThreeNo da
This is a step of terminating the ringing bond. Other hydrogenation
As a means, plasma hydrogenation (excited by plasma
Using hydrogen). In any case, the island
Defect density in the semiconductor layers 504 to 508 is 10 ¹⁶/cm^ThreeLess than
It is preferable to set the hydrogen content to 0.01 to
What is necessary is just to give about 0.1 atomic%.

Then, a second interlayer insulating film 559 made of an organic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As organic resin materials, polyimide, acrylic,
Polyamide, polyimide amide, BCB (benzocyclobutene) and the like can be used. For example, in the case of using a polyimide of a type that is thermally polymerized after being applied to a substrate, it is formed by firing at 300 ° C. in a clean oven.
In the case of using acrylic, a two-component type is used, and after mixing the main material and the curing agent, the whole surface is applied using a spinner and then pre-heated at 80 ° C. for 60 seconds on a hot plate. Then, it can be formed by firing in a clean oven at 250 ° C. for 60 minutes.

As described above, by forming the second interlayer insulating film 559 from an organic insulating material, the surface can be satisfactorily planarized. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and is not suitable as a protective film, it is preferable to use it in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 558 as in this embodiment. .

Thereafter, using a fourth photomask (PM4), a resist mask having a predetermined pattern is formed, and a contact hole is formed in each island-like semiconductor layer and reaches an impurity region serving as a source region or a drain region. I do. The contact hole is formed by a dry etching method. In this case, the second interlayer insulating film 559 made of organic resin material using a mixed gas of CF _4, O _2, He as an etching gas is first etched, then followed by the first etching gas as CF _4, O ₂ Is etched. Further, in order to increase the selectivity with respect to the island-shaped semiconductor layer, a contact hole can be formed by switching the etching gas to CHF ₃ and etching the third shape gate insulating film 570.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed by a fifth photomask (PM5), and the source lines 560 to 564 and the drain lines 565 to 568 are etched.
To form The pixel electrode 569 is formed together with the drain line. The pixel electrode 571 represents a pixel electrode belonging to an adjacent pixel. Although not shown, in this embodiment, this wiring is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with an impurity region forming a source or drain region of the island-shaped semiconductor layer, and forming the Ti film. Aluminum (Al) was formed to a thickness of 300 to 400 nm on top of it, and a transparent conductive film was formed thereon to a thickness of 80 to 120 nm. Indium oxide zinc oxide alloy (I
n ₂ O ₃ —ZnO) and zinc oxide (ZnO) are also suitable materials, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to increase the transmittance and conductivity of visible light is also preferable. Can be used.

[0252] In this way, a substrate having TFTs of driver circuits (source signal line driver circuits and gate signal line driver circuits) and pixel TFTs of a pixel portion is completed over the same substrate by using five photomasks. Can be. The driving circuit includes a first p-channel TFT 600, a first n-channel TFT 601, a second p-channel TFT 602, and a second p-channel TFT 602.
N-channel type TFT 603, and the pixel portion has a pixel TFT 6
04, a storage capacitor 605 is formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the first p-channel TFT 600, a conductive layer having a second tapered shape has a function as a gate electrode 620, and the island-shaped semiconductor layer 504 serves as a channel formation region 606 and a source region or a drain region. A functioning third impurity region 607a and a fourth impurity region (A) forming an LDD region that does not overlap with the gate electrode 620
607b has a fourth impurity region (B) 607c which forms an LDD region partly overlapping the gate electrode 620.

In the first n-channel TFT 601, a conductive layer having a second tapered shape has a function as the gate electrode 621, and the island-shaped semiconductor layer 505 serves as a channel formation region 608 and a source region or a drain region. A functioning first impurity region 609a and a second impurity region (A) forming an LDD region which does not overlap with the gate electrode 621
609b has a second impurity region (B) 609c which forms an LDD region partly overlapping the gate electrode 621. For a channel length of 2 to 7 μm, the second
The length of the portion where the impurity region (B) 609c overlaps with the gate electrode 621 is 0.1 to 0.3 μm. The length of Lov is controlled from the thickness of the gate electrode 621 and the angle of the tapered portion. Such an LD in an n-channel TFT
By forming the D region, a high electric field generated near the drain region is relieved, and the generation of hot carriers is prevented.
Deterioration of the TFT can be prevented.

Second p-channel TFT 60 of drive circuit
Similarly, the island-shaped semiconductor layer 506 has a second tapered conductive layer functioning as a gate electrode 622.
A channel formation region 610, a third impurity region 611a functioning as a source region or a drain region, a fourth impurity region (A) 611b forming an LDD region which does not overlap with the gate electrode 622, and a portion overlaps with the gate electrode 622. Fourth impurity region (B) 61 forming LDD region
1c.

Second n-channel TFT 60 of drive circuit
3, a conductive layer having a second tapered shape has a function as a gate electrode 623, and a channel formation region 612, a first impurity region 613 a which functions as a source region or a drain region in the island-shaped semiconductor layer 507, Second impurity region (A) 613b forming an LDD region that does not overlap with gate electrode 623, and second impurity region (B) 613c forming an LDD region that partially overlaps with gate electrode 623
It has a structure having. Second n-channel TFT
Similarly to 601, the length of the portion where the second impurity region (B) 613 c overlaps with the gate electrode 623 is 0.1 to 0.3 μm.
And

The driving circuit has a logic circuit such as a shift register and a buffer, a sampling circuit formed by analog switches, and the like. In FIG. 21B, the TFTs forming them have a single-gate structure in which one gate electrode is provided between a pair of sources and drains. However, a multi-gate in which a plurality of gate electrodes are provided between a pair of sources and drains is shown. A gate structure may be used.

In the pixel TFT 604, a conductive layer having a second taper shape has a function as a gate electrode 624, and a channel forming region 614a is formed in the island-shaped semiconductor layer 508.
614b, first impurity regions 615a, 616, 617a functioning as a source region or a drain region, a second impurity region (A) 615b forming an LDD region which does not overlap with the gate electrode 624, part of which overlaps with the gate electrode 624 Second impurity region (B) 6 forming LDD region
15c. The length of the portion where the second impurity region (B) 613c overlaps with the gate electrode 624 is 0.1 to 0.3 μm. Further, the second impurity region (A) 619b extending from the first impurity region 617,
A second impurity region (B) 619c, a semiconductor layer including a region 618 to which an impurity element determining a conductivity type is not added, an insulating layer formed using the same layer as a gate insulating film having a third shape, A storage capacitor 605 is formed from a capacitor wiring 625 formed of a conductive layer having a second tapered shape.

The gate electrode 624 of the pixel TFT 604 is formed via the gate insulating film 570 with the island-like semiconductor layer 508 thereunder.
And extends over a plurality of island-shaped semiconductor layers to serve also as a gate signal line. The storage capacitor 605 is connected to the pixel T
The capacitor 625 is formed in a region where the semiconductor layer extending from the drain region 617a of the FT 604 and the capacitor wiring 625 overlap with the gate insulating film 570 interposed therebetween. In this configuration, the semiconductor layer 6
18 does not contain an impurity element for controlling valence electrons.

The configuration described above makes it possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the driving circuit, and to improve the operation performance and reliability of the semiconductor display device. I have. Further, by forming the gate electrode with a conductive material having heat resistance, L
Activation of the DD region, the source region, and the drain region is facilitated. Further, when forming an LDD region overlapping the gate electrode with a gate insulating film interposed therebetween, the impurity element added for the purpose of controlling the conductivity type is provided with a concentration gradient so that the LDD region is formed.
By forming the D region, it can be expected that the effect of alleviating the electric field particularly near the drain region is enhanced.

[0261] In the case of an active matrix liquid crystal display device, the first p-channel TFT 600 and the first n-channel TFT 601 are used for forming a shift register, a buffer, a level shift, and the like that emphasize high-speed operation. FIG. 21B illustrates these circuits as logic circuit portions. The second impurity region (B) 609c of the first n-channel TFT 601 has a structure in which measures against hot carriers are emphasized. Further, in order to increase the breakdown voltage and stabilize the operation, the TFT of the logic circuit portion may have a double gate structure in which two gate electrodes are provided between a pair of source and drain. A TFT having a double gate structure can be manufactured in the same manner by using the steps of this embodiment.

The sampling circuit composed of analog switches includes a second p-channel TFT 602 and a second n-channel TFT having the same configuration as the logic circuit portion.
603 can be applied. Because the sampling circuit emphasizes hot carrier measures and low off-current operation,
Second p-channel TFT 602 in sampling circuit section
May have a triple gate structure in which three gate electrodes are provided between a pair of source and drain regions, and such a TFT can be manufactured in the same manner by using the steps of this embodiment. The channel length is 3 to 7 μm, the LDD region overlapping with the gate electrode is Lov, and the length in the channel length direction is 0.1 to 0.3 μm.

As described above, whether the configuration of the gate electrode of the TFT is a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of sources and drains depends on the characteristics of the circuit. It is only necessary for the person to choose appropriately.

Next, as shown in FIG.
A spacer made of a columnar spacer is formed on the active matrix substrate in the state shown in FIG. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film on the entire surface of the substrate and then patterning the resin film is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Co., Ltd. is applied by a spinner, and then formed into a predetermined pattern by exposure and development processing. Using a clean oven, etc.
Heat and cure at 150-200 ° C. The spacer manufactured in this way can have different shapes depending on the conditions of the exposure and development processing.However, preferably, the shape of the spacer is columnar and the top is flat, so that the opposing substrate is When combined, the mechanical strength of the liquid crystal panel can be secured. The shape is conical,
Although there is no particular limitation such as a pyramid shape, for example, when the shape is a cone, specifically, the height is 1.2 to 5 μm, the average radius is 5 to 7 μm, and the ratio of the average radius to the bottom radius is 1 Vs. 1.
5 is assumed. At this time, the taper angle of the side surface is set to ± 15 ° or less.

The arrangement of the spacers may be arbitrarily determined, but preferably, as shown in FIG. 22A, in the pixel portion, the columnar spacer is overlapped with the contact portion 631 of the pixel electrode 569 so as to cover that portion. 656 may be formed. Since the flatness of the contact portion 631 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 656 is formed in such a manner that the contact portion 631 is filled with the resin for the spacer. In this way, it is possible to prevent the liquid crystal molecules from being disturbed by the disturbance. Further, spacers 655a to 655e are also formed on the TFT of the driving circuit. This spacer may be formed over the entire surface of the drive circuit section, or as shown in FIG.
The source line and the drain line may be provided as shown in FIG.

Then, an alignment film 657 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 656 provided in the pixel portion was set to 2 μm or less. In the rubbing treatment, generation of static electricity often poses a problem, but the effect of protecting the TFT from static electricity can be obtained by the spacers 655a to 655e formed on the TFT of the driving circuit. Although not shown in the drawing, after forming the alignment film 657 first, the spacers 656 and 65 are formed.
5a to 655e may be formed.

On the opposing substrate 651 on the opposing side, a light shielding film 65 is provided.
2. A transparent conductive film 653 and an alignment film 654 are formed.
The light-shielding film 652 includes a Ti film, a Cr film, an Al film,
It is formed with a thickness of 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached with a sealant 658. A filler (not shown) is mixed in the sealant 658, and the two substrates are bonded to each other at a uniform interval by the filler and the spacers 656 and 655a to 655e. After that, a liquid crystal material 659 is injected between the two substrates. A known liquid crystal material may be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance changes continuously with respect to an electric field can be used. In this thresholdless antiferroelectric mixed liquid crystal,
Some exhibit a V-shaped electro-optical response characteristic. Thus, the active matrix liquid crystal display device shown in FIG. 22B is completed.

A TFT formed by the manufacturing method described in this embodiment has a high crystallinity of a semiconductor layer, and therefore is extremely effective for use in a semiconductor display device of the present invention which requires a high response speed. It is.

[0269] The method for manufacturing the semiconductor display device of the present invention is not limited to the manufacturing method described in this embodiment. The semiconductor display device of the present invention can be manufactured by using a known method.

This embodiment can be freely combined with Embodiments 1 to 5.

(Embodiment 8) The present invention can be used for various liquid crystal panels. That is, the present invention can be applied to all semiconductor display devices (electronic devices) incorporating these liquid crystal panels (active matrix type liquid crystal displays) as display media.

As such electronic equipment, a video camera, digital camera, projector (rear or front type), head mounted display (goggle type display), game machine, car navigation, personal computer, portable information terminal (mobile computer) , A mobile phone or an electronic book).
One example of them is shown in FIG.

[0273] FIG. 23A shows a display, which includes a housing 2001, a support 2002, a display portion 2003, and the like.
The present invention can be applied to the display portion 2003.

FIG. 23B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6. The present invention can be applied to the display portion 2102.

FIG. 23C shows a part (right side) of a head-mounted display, which includes a main body 2201, a signal cable 2202, a head fixing band 2203, a screen section 2204, an optical system 2205, a display section 2206, and the like. including.
The present invention can be applied to the display portion 2206.

FIG. 23D shows an image reproducing apparatus (specifically, a DVD reproducing apparatus) provided with a recording medium.
1, recording medium (DVD or the like) 2302, operation switch 23
03, a display unit (a) 2304, a display unit (b) 2305, and the like. The display portion (a) 2304 mainly displays image information, and the display portion (b) 2305 mainly displays character information. The semiconductor display device of the present invention employs these display portions (a).
2304 and (b) 2305. Note that the image reproducing device provided with the recording medium includes a home game machine and the like.

FIG. 23E shows a personal computer, which includes a main body 2401, a video input section 2402, and a display section 24.
03, a keyboard 2404. The present invention can be applied to the video input unit 2402 and the display unit 2403.

FIG. 23F shows a goggle type display, which comprises a main body 2501, a display section 2502, and an arm section 250.
3 The present invention can be applied to the display portion 2502.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 7.

(Embodiment 9) The present invention can be applied to a projector (rear type or front type). Examples of these are shown in FIGS.

FIG. 24A shows a front type projector, which comprises a light source optical system, a display device 7601, and a screen 7602. The present invention can be applied to the display device 7601.

FIG. 24B shows a rear projector, in which a main body 7701, a light source optical system and a display device 7702,
Mirror 7703, mirror 7704, screen 7705
It consists of. The present invention can be applied to the display device 7702.

FIG. 24C shows the light source optical system and the display device 760 shown in FIGS. 24A and 24B.
1 is a diagram showing an example of the structure of 7702. FIG. The light source optical system and the display devices 7601 and 7702 are
01, mirrors 7802, 7804 to 7806, dichroic mirror 7803, optical system 7807, display device 78
08, a phase difference plate 7809, and a projection optical system 7810. The projection optical system 7810 includes a plurality of optical lenses provided with a projection lens. This configuration corresponds to the display 78
It is called a three-plate type because it uses three 08s. Further, the practitioner may appropriately place an optical lens, a film having a polarizing function,
A film for adjusting the phase difference, an IR film, or the like may be provided.

FIG. 24D is a diagram showing an example of the structure of the light source optical system 7801 in FIG. In the present embodiment, the light source optical system 7801 includes a reflector 7811, a light source 7812, and lens arrays 7813 and 7813.
814, a polarization conversion element 7815, and a condenser lens 7816. Note that the light source optical system shown in FIG. 24D is an example, and the present invention is not limited to this structure. For example, a practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like to the light source optical system.

FIG. 24 (C) shows an example of a three-plate type, while FIG. 25 (A) shows an example of a single-plate type. FIG.
The light source optical system and the display device illustrated in FIG. 1A include a light source optical system 7901, a display device 7902, a projection optical system 7903, and a retardation plate 7904. The projection optical system 7903 is
It is composed of a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in FIG.
24A and 24B can be applied to the light source optical system and the display devices 7601 and 7702. The light source optical system 7901 may use the light source optical system shown in FIG. Note that the display device 7902 is provided with a color filter (not shown) to colorize a display image.

The light source optical system and the display device shown in FIG. 25B are an application example of FIG. 25A. Instead of providing a color filter, an RGB rotating color filter disk 7905 is used. The display image is colorized. The light source optical system and the display device shown in FIG. 25B can be applied to the light source optical system and the display devices 7601 and 7702 in FIGS. 24A and 24B.

The light source optical system and the display device shown in FIG. 25C are called a color filterless single plate type. In this method, a microlens array 7915 is provided on a display device 7916, and a dichroic mirror (green) 7 is provided.
912, a dichroic mirror (red) 7913, and a dichroic mirror (blue) 7914 are used to colorize the display image. The projection optical system 7917 includes a plurality of optical lenses provided with a projection lens. The light source optical system and the display device shown in FIG.
(B) Light source optical system and display devices 7601 and 7 in FIG.
702. Further, as the light source optical system 7911, an optical system using a coupling lens and a collimator lens in addition to the light source may be used.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 7.

[0289]

According to the present invention, since the frame frequency can be increased without increasing the frequency of the video signal input to the IC by the above-described configuration, a burden is imposed on the electronic device generating the video signal. In addition, it is possible to display a clear and high-definition image in which a flicker, vertical stripes, horizontal stripes, and oblique stripes are hardly visually recognized by an observer.

In addition, by using frame inversion in the present invention, the occurrence of a phenomenon stripe called disclination between adjacent pixels can be suppressed, and the brightness of the entire display screen can be prevented from being reduced. .

Further, in two consecutive frame periods, the potential of the display signal input to each pixel is inverted with reference to the potential of the counter electrode (counter potential), so that the same image is displayed in the pixel portion. You. With the above structure, the temporal average of the potential of the display signal input to each pixel becomes closer to the opposite potential, and the deterioration of the liquid crystal is reduced as compared with the case where different display signals are input to each pixel in each frame period. More effective to prevent.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frame rate conversion unit included in a semiconductor display device of the present invention.

FIG. 2 is a block diagram of a frame frequency conversion unit.

FIG. 3 is a diagram showing write and read timings of a video signal of the SDRAM.

FIG. 4 is a diagram of a pixel portion and a driving circuit of a semiconductor display device of the present invention, and a pattern diagram of pixels.

FIG. 5 is a timing chart of a selection signal and a display signal in a pixel portion.

FIG. 6 is a pattern diagram showing the polarity of a display signal input to a pixel portion during frame inversion driving.

FIG. 7 is a pattern diagram showing the polarity of a display signal input to a pixel portion during source line inversion driving.

FIG. 8 is a pattern diagram showing the polarity of a display signal input to a pixel portion during gate line inversion driving.

FIG. 9 is a pattern diagram showing the polarity of a display signal input to a pixel portion during dot inversion driving.

FIG. 10 is a diagram showing timings of writing and reading of a video signal of the SDRAM.

FIG. 11 is a diagram showing timings of writing and reading of a video signal of the SDRAM.

FIG. 12 is a block diagram of a frame rate conversion unit included in the semiconductor display device of the present invention.

FIG. 13 is a diagram showing timings of writing and reading of a video signal of the SDRAM.

FIG. 14 is a diagram of a pixel portion and a driver circuit of an analog drive semiconductor display device of the present invention.

FIG. 15 is a circuit diagram of a source signal line driver circuit.

FIG. 16 is a circuit diagram of an analog switch and a level shift.

FIG. 17 is a block diagram of a frame rate converter included in the semiconductor display device of the present invention.

FIG. 18 is a diagram of a pixel portion and a driver circuit of a digitally driven semiconductor display device of the present invention.

FIG. 19 illustrates a manufacturing process of a semiconductor display device.

FIG. 20 illustrates a manufacturing process of a semiconductor display device.

FIG. 21 illustrates a manufacturing process of a semiconductor display device.

FIG. 22 illustrates a manufacturing process of a semiconductor display device.

FIG. 23 is a diagram of an electronic device to which the present invention is applied.

FIG. 24 is a diagram of a projector to which the invention is applied.

FIG. 25 is a diagram of a projector to which the invention is applied.

26A and 26B are a top view of an active matrix liquid crystal display device and a diagram showing an arrangement of pixels.

FIG. 27 is a diagram showing a polarity pattern in AC driving.

FIG. 28 is a timing chart of a conventional frame inversion drive.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/20 631 G09G 3/20 631B 650 650J 680 680V (72) Inventor Noboru Inoue 398 Nagatani, Atsugi-shi, Kanagawa Prefecture Address F-term in Semiconductor Energy Laboratory Co., Ltd. (reference) 2H092 JA24 NA01 PA06 2H093 NA16 NA33 NC13 NC24 NC34 ND10 5C006 AC07 AC24 AC28 AF04 AF05 AF44 BB16 BC16 BF02 EC11 EC13 FA23 5C080 AA10 BB05 DD01 DD06 EE32 FF11 JJ03 JJ02JJ02 KK43

Claims (24)

[Claims] 1. A semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit, wherein a display signal is applied to the plurality of pixel electrodes via the plurality of switching elements. All display signals that are input and input to the plurality of pixel electrodes have the same polarity with respect to the potential of the counter electrode during each frame period. The display signals input to the plurality of pixel electrodes in a later appearing frame period of any two adjacent frame periods are synchronized with the plurality of display signals in the earlier appearing frame period. Wherein the potential of the display signal input to the pixel electrode is inverted with respect to the potential of the counter electrode. 2. A semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit, wherein the plurality of switching elements are input to the plurality of source signal lines. A display signal is input to the plurality of pixel electrodes via the plurality of switching elements. During each frame period, adjacent source signal lines of the plurality of source signal lines are connected to each other with reference to the potential of the counter electrode. A display signal having a reverse polarity is input, and display signals input to each of the plurality of source signal lines always have the same polarity with reference to the potential of the counter electrode, and the frame rate The conversion unit operates in synchronization with the display signal, and, in any two adjacent frame periods, a plurality of the plurality of adjacent frame periods appear in a later appearing frame period. The display signal input to the pixel electrode is a signal obtained by inverting the potential of the display signal input to the plurality of pixel electrodes in the previously appearing frame period with reference to the potential of the counter electrode. Semiconductor display device. 3. A semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit, wherein the plurality of switching elements are input to the plurality of source signal lines. A display signal is input to the plurality of pixel electrodes via the plurality of switching elements. During each line period, a display signal input to all of the plurality of source signal lines is based on a potential of the counter electrode. Always have the same polarity, and in adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode. The conversion unit operates in synchronization with the display signal, and, in any two adjacent frame periods, the plurality of images in a later appearing frame period. The display signal input to the electrode is a signal obtained by inverting the potential of the display signal input to the plurality of pixel electrodes in the previously appearing frame period with reference to the potential of the counter electrode. Display device. 4. A semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion section, wherein the plurality of source signal lines are input. A display signal is input to the plurality of pixel electrodes via the plurality of switching elements. During each frame period, adjacent source signal lines of the plurality of source signal lines are connected to each other with reference to the potential of the counter electrode. Display signals having opposite polarities are input, and in adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode. The frame rate conversion unit is operating in synchronization with the display signal, and, of any two adjacent frame periods, a frame period that appears later Wherein the display signal input to the plurality of pixel electrodes is a signal obtained by inverting the potential of the display signal input to the plurality of pixel electrodes in the previously appearing frame period with reference to the potential of the counter electrode. A semiconductor display device characterized by the above-mentioned. 5. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; and a frame rate converter, wherein the plurality of pixels include a switching element, a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The generated video signals are both input to a source signal line driving circuit, two display signals are generated by the source signal line driving circuit, and the two display signals have opposite polarities. A display signal is input to the pixel electrode via the switching element, and a video signal is written to the one RAM or any one of the plurality of RAMs. A period in which the video signal is written to one RAM or any one of the plurality of RAMs is longer than a period in which the written video signal is read for the first time and a period in which the video signal is read for the second time. Semiconductor display device. 6. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; and a frame rate conversion portion, wherein the plurality of pixels include a switching element, a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. D / A
The conversion signal is converted into an analog signal and then input to a source signal line driving circuit. The source signal line driving circuit generates two display signals. The two display signals have inverted polarities. The two display signals are input to the pixel electrodes via the switching elements. During a period in which the video signal is written to the one RAM or any one of the plurality of RAMs, the written video signal is 1 A semiconductor display device, wherein the period is longer than a period during which the second reading is performed and a period during which the second reading is performed. 7. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; and a frame rate conversion portion, wherein the plurality of pixels include a switching element, a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The generated video signals are both input to a source signal line driving circuit, two display signals are generated by the source signal line driving circuit, and the two display signals have opposite polarities. A display signal is input to the pixel electrode via the switching element, and all display signals input to the pixel electrode change the potential of the counter electrode during each frame period. The video signal has the same polarity as a reference, and a period during which the video signal is written to the one RAM or any one of the plurality of RAMs is a period during which the written video signal is read out for the first time and a second time. A semiconductor display device which is longer than a readout period. 8. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; and a frame rate conversion portion, wherein the plurality of pixels include a switching element, a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The converted video signals are both converted to analog in a D / A conversion circuit and then input to a source signal line driving circuit, where two display signals are generated by the source signal line driving circuit, and the two display signals are mutually polar. Are inverted, and the two generated display signals are input to the pixel electrode via the switching element, and all the display signals input to the pixel electrode are displayed. The signal has the same polarity with respect to the potential of the counter electrode during each frame period, and the period during which a video signal is written to the one RAM or any one of the plurality of RAMs is the period during which the video signal is written. A period in which the video signal is read out for the first time and a period in which the video signal is read out for the second time. 9. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; a plurality of source signal lines; and a frame rate conversion section, wherein the plurality of pixels are switching elements. And a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The generated video signals are both input to a source signal line driving circuit, two display signals are generated by the source signal line driving circuit, and the two display signals have opposite polarities. A display signal is input to the pixel electrode via the plurality of source signal lines and the switching element, and a source signal line adjacent to the plurality of source signal lines during each frame period. A display signal having polarities opposite to each other with respect to the potential of the counter electrode is input to the signal line, and a display signal input to each of the plurality of source signal lines changes the potential of the counter electrode. The same polarity is always used as a reference, and a period during which the video signal is written to the one RAM or any one of the plurality of RAMs includes a period during which the written video signal is read out for the first time and a second period. A semiconductor display device, wherein the period is longer than the period of time when data is read out. 10. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; a plurality of source signal lines; and a frame rate converter, wherein the plurality of pixels are switching elements. And a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. D / A
The conversion signal is converted into an analog signal and then input to a source signal line driving circuit. The source signal line driving circuit generates two display signals. The two display signals have inverted polarities. The two display signals are input to the pixel electrode via the plurality of source signal lines and the switching element. During each frame period, a source signal line adjacent to the plurality of source signal lines includes the counter electrode. Display signals having polarities opposite to each other with respect to the potential are input, and the display signals input to each of the plurality of source signal lines always have the same polarity with reference to the potential of the counter electrode. In a period during which a video signal is written to the one RAM or any one of the plurality of RAMs, the written video signal is output for the first time. The semiconductor display device comprising longer than the period to be read period and a second time to Desa seen. 11. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; a plurality of source signal lines; and a frame rate conversion section, wherein the plurality of pixels are switching elements. And a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The generated video signals are both input to a source signal line driving circuit, two display signals are generated by the source signal line driving circuit, and the two display signals have opposite polarities. A display signal is input to the pixel electrode via the plurality of source signal lines and the switching element, and is input to all of the plurality of source signal lines during each line period. The display signal always has the same polarity with reference to the potential of the counter electrode. In the adjacent line period, the polarity of the display signal input to the plurality of source signal lines is equal to the potential of the counter electrode. The period during which the video signal is written to the one RAM or any one of the plurality of RAMs is a period during which the written video signal is read for the first time and a period during which the video signal is written at the second time. A semiconductor display device, wherein the period is longer than the period of time. 12. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; and a frame rate conversion portion, wherein the plurality of pixels include a switching element, a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. D / A
The conversion signal is converted into an analog signal and then input to a source signal line driving circuit. The source signal line driving circuit generates two display signals. The two display signals have inverted polarities. The two display signals are input to the pixel electrode via the switching element. During each line period, the display signals input to all of the plurality of source signal lines are always the same with reference to the potential of the counter electrode. The polarities of the display signals input to the plurality of source signal lines in adjacent line periods are inverted with respect to the potential of the counter electrode, and the one RAM, Alternatively, a period in which the video signal is written to any one of the plurality of RAMs is a period in which the written video signal is read for the first time and a period in which the video signal is read for the second time. The semiconductor display device comprising longer than the period issued. 13. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line drive circuit; a plurality of source signal lines; and a frame rate conversion section, wherein the plurality of pixels are switching elements. And a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. The generated video signals are both input to a source signal line driving circuit, two display signals are generated by the source signal line driving circuit, and the two display signals have opposite polarities. A display signal is input to the pixel electrode via the switching element. During each frame period, a source signal line adjacent to the plurality of source signal lines is provided with the counter electrode. Display signals having polarities opposite to each other with respect to the potential are input, and in adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are determined with reference to the potential of the counter electrode. The period during which the video signal is written to the one RAM or any one of the plurality of RAMs is shorter than the period during which the written video signal is read for the first time and the period at which the video signal is read for the second time. Semiconductor display device characterized by having a long length. 14. A semiconductor display device comprising: a pixel portion having a plurality of pixels; a source signal line driving circuit; a plurality of source signal lines; and a frame rate conversion portion, wherein the plurality of pixels are switching elements. And a pixel electrode,
The frame rate conversion unit has one or a plurality of RAMs, and a video signal is written into one of the one or the plurality of RAMs, The video signal written to the one RAM or any one of the plurality of RAMs is read twice, and the video signal is read twice from the one RAM or any one of the plurality of RAMs twice. D / A
The conversion signal is converted into an analog signal and then input to a source signal line driving circuit. The source signal line driving circuit generates two display signals. The two display signals have inverted polarities. The two display signals are input to the pixel electrode via the switching element. During each frame period, the source signal lines adjacent to the plurality of source signal lines are opposite to each other with respect to the potential of the counter electrode. A display signal having a polarity is input, and in adjacent line periods, polarities of the display signals input to the plurality of source signal lines are inverted with respect to a potential of the counter electrode, During the period of writing the video signal to one RAM or any one of the plurality of RAMs, the written video signal is read out for the first time. The semiconductor display device comprising longer than the period to be read period and the second time that. 15. The RAM according to claim 5, wherein the RAM is an SRAM, a DRAM or an SD.
A semiconductor display device, which is a RAM. 16. The switching element according to claim 1, wherein the switching element uses a transistor formed using single crystal silicon, a thin film transistor formed using polycrystalline silicon, or amorphous silicon. A semiconductor display device, characterized in that it is a thin film transistor formed by: 17. A computer using the semiconductor display device according to any one of claims 1 to 16. 18. A video camera using the semiconductor display device according to any one of claims 1 to 16. 19. A DVD player using the semiconductor display device according to any one of claims 1 to 16. 20. A method of driving a semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit, wherein the plurality of pixel electrodes are connected to the plurality of pixel electrodes via the plurality of switching elements. A display signal is input, and the frame rate conversion unit is operating in synchronization with the display signal, and the plurality of pixel electrodes are arranged in a frame period that appears later in any two adjacent frame periods. The display signal input to the plurality of pixel electrodes is a signal obtained by inverting the polarity of the display signal input to the plurality of pixel electrodes with respect to the potential of the counter electrode in a frame period that appears earlier. How to drive the device. 21. A method for driving a semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, and a frame rate conversion unit, wherein the plurality of pixel electrodes are connected to the plurality of pixel electrodes via the plurality of switching elements. A display signal is input, and all display signals input to the plurality of pixel electrodes have the same polarity with respect to the potential of the counter electrode during each frame period. The display signal which is operated in synchronization with the display signal and which is input to the plurality of pixel electrodes in a later appearing frame period of any two adjacent frame periods is a frame period which appears earlier. 3. The semiconductor device according to claim 1, wherein the potential of the display signal input to the plurality of pixel electrodes is inverted with reference to the potential of the counter electrode. The driving method of the indicating device. 22. A method for driving a semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion section, wherein the plurality of source signal lines are An input display signal is input to the plurality of pixel electrodes via the plurality of switching elements. During each frame period, a potential of the counter electrode is applied to a source signal line adjacent to the plurality of source signal lines. Display signals having polarities opposite to each other as a reference are input, and the display signals input to each of the plurality of source signal lines always have the same polarity with reference to the potential of the counter electrode, The frame rate conversion unit operates in synchronization with the display signal, and in a frame period appearing later, of any two adjacent frame periods. The display signal input to the plurality of pixel electrodes is a signal obtained by inverting the potential of the display signal input to the plurality of pixel electrodes in a previously appearing frame period with reference to the potential of the counter electrode. A method for driving a semiconductor display device. 23. A method for driving a semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit, wherein: An input display signal is input to the plurality of pixel electrodes via the plurality of switching elements. During each line period, a display signal input to all of the plurality of source signal lines is a potential of the counter electrode. Have the same polarity as a reference, and in adjacent line periods, the polarities of display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode, The frame rate conversion unit operates in synchronization with the display signal, and in any two adjacent frame periods, a frame period that appears later The display signal input to the plurality of pixel electrodes is a signal obtained by inverting the potential of the display signal input to the plurality of pixel electrodes in the previously appearing frame period with reference to the potential of the counter electrode. A method for driving a semiconductor display device. 24. A method for driving a semiconductor display device having a plurality of switching elements, a plurality of pixel electrodes, a counter electrode, a plurality of source signal lines, and a frame rate conversion unit, wherein: An input display signal is input to the plurality of pixel electrodes via the plurality of switching elements. During each frame period, a potential of the counter electrode is applied to a source signal line adjacent to the plurality of source signal lines. Display signals having polarities opposite to each other are input as a reference, and in adjacent line periods, the polarities of the display signals input to the plurality of source signal lines are inverted with respect to the potential of the counter electrode. The frame rate conversion unit is operating in synchronization with the display signal, and appears later in any two adjacent frame periods. The display signal input to the plurality of pixel electrodes in a frame period is a signal obtained by inverting the potential of the display signal input to the plurality of pixel electrodes in the previously appearing frame period with reference to the potential of the counter electrode. A method for driving a semiconductor display device.