KR20100029236A - 입력/출력 버퍼에 대한 동적 임피던스 제어 - Google Patents

입력/출력 버퍼에 대한 동적 임피던스 제어 Download PDF

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Publication number
KR20100029236A
KR20100029236A KR1020107000345A KR20107000345A KR20100029236A KR 20100029236 A KR20100029236 A KR 20100029236A KR 1020107000345 A KR1020107000345 A KR 1020107000345A KR 20107000345 A KR20107000345 A KR 20107000345A KR 20100029236 A KR20100029236 A KR 20100029236A
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KR
South Korea
Prior art keywords
pull
termination
network
drive
calibration
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Abandoned
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KR1020107000345A
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English (en)
Korean (ko)
Inventor
브루스 밀라
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모사이드 테크놀로지스 인코퍼레이티드
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Publication of KR20100029236A publication Critical patent/KR20100029236A/ko
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/0045—Impedance matching networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020107000345A 2007-06-08 2008-06-06 입력/출력 버퍼에 대한 동적 임피던스 제어 Abandoned KR20100029236A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US94279807P 2007-06-08 2007-06-08
US60/942,798 2007-06-08

Publications (1)

Publication Number Publication Date
KR20100029236A true KR20100029236A (ko) 2010-03-16

Family

ID=40093105

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020107000345A Abandoned KR20100029236A (ko) 2007-06-08 2008-06-06 입력/출력 버퍼에 대한 동적 임피던스 제어

Country Status (9)

Country Link
US (5) US7834654B2 (enExample)
EP (1) EP2171844B1 (enExample)
JP (1) JP5312453B2 (enExample)
KR (1) KR20100029236A (enExample)
CN (1) CN101779373B (enExample)
CA (1) CA2688277A1 (enExample)
ES (1) ES2507075T3 (enExample)
TW (1) TW200910373A (enExample)
WO (1) WO2008148197A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160108432A (ko) * 2014-01-16 2016-09-19 퀄컴 인코포레이티드 시스템 레벨 전력 분배 네트워크들에 대한 전압 의존적 다이 rc 모델링
KR20170064842A (ko) * 2015-12-02 2017-06-12 에스케이하이닉스 주식회사 송신 회로 및 반도체 장치

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100772533B1 (ko) 2006-09-27 2007-11-01 주식회사 하이닉스반도체 온 다이 터미네이션 회로 및 그의 구동 방법
TW200910373A (en) 2007-06-08 2009-03-01 Mosaid Technologies Inc Dynamic impedance control for input/output buffers
US7771115B2 (en) * 2007-08-16 2010-08-10 Micron Technology, Inc. Temperature sensor circuit, device, system, and method
KR101639762B1 (ko) * 2009-02-02 2016-07-14 삼성전자주식회사 출력 버퍼 회로 및 이를 포함하는 집적 회로
KR20110128858A (ko) * 2009-02-12 2011-11-30 모사이드 테크놀로지스 인코퍼레이티드 온-다이 터미네이션을 위한 터미네이션 회로
US9608630B2 (en) * 2009-05-06 2017-03-28 Micron Technology, Inc. Reference voltage circuits and on-die termination circuits, methods for updating the same, and methods for tracking supply, temperature, and/or process variation
US8606211B2 (en) 2009-06-23 2013-12-10 Qualcomm Incorporated High dynamic range receiver front-end with Q-enhancement
KR101789077B1 (ko) * 2010-02-23 2017-11-20 삼성전자주식회사 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법
KR101166643B1 (ko) * 2010-09-07 2012-07-23 에스케이하이닉스 주식회사 데이터 출력 회로
KR20120121707A (ko) * 2011-04-27 2012-11-06 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 반도체 시스템
US8643419B2 (en) * 2011-11-04 2014-02-04 Silicon Laboratories Inc. Flexible low power slew-rate controlled output buffer
KR101874584B1 (ko) * 2012-04-03 2018-07-04 삼성전자주식회사 전압 방식 구동기
US8797084B2 (en) 2012-08-31 2014-08-05 International Business Machines Corporation Calibration schemes for charge-recycling stacked voltage domains
US8957700B2 (en) * 2012-09-28 2015-02-17 Analog Devices, Inc. Apparatus and methods for digital configuration of integrated circuits
CN102915756B (zh) * 2012-10-09 2015-05-20 无锡江南计算技术研究所 Ddr3信号端接结构
US9130557B2 (en) 2012-12-03 2015-09-08 Samsung Electronics Co., Ltd. Operating method of input/output interface
USRE49506E1 (en) 2012-12-03 2023-04-25 Samsung Electronics Co., Ltd. High/low speed mode selection for output driver circuits of a memory interface
WO2014099291A1 (en) * 2012-12-18 2014-06-26 Borgwarner Inc. Tensioner with spring force control in a second bore
CN103077736B (zh) * 2012-12-21 2015-12-09 西安华芯半导体有限公司 一种可兼容ddr2和ddr3的ocd模块
WO2014112453A1 (ja) * 2013-01-16 2014-07-24 ピーエスフォー ルクスコ エスエイアールエル 半導体装置
KR102044478B1 (ko) 2013-04-22 2019-11-13 삼성전자주식회사 드라이버 및 이를 포함하는 메모리 컨트롤러
US9454500B2 (en) * 2013-06-17 2016-09-27 Nxp B.V. Network communication control apparatus, system and method
KR102098243B1 (ko) 2013-07-19 2020-05-26 삼성전자주식회사 집적 회로 및 그것의 데이터 입력 방법
US9166565B2 (en) * 2013-10-17 2015-10-20 Qualcomm Incorporated Calibrated output driver with enhanced reliability and density
KR20150049267A (ko) 2013-10-29 2015-05-08 삼성전자주식회사 반도체 메모리 장치 및 이의 동작 방법
KR102185284B1 (ko) * 2013-12-12 2020-12-01 삼성전자 주식회사 온 다이 터미네이션 저항들의 부정합을 보상하는 버퍼 회로, 반도체 장치 반도체 장치의 동작방법
CN104135268B (zh) * 2014-06-27 2017-04-12 晨星半导体股份有限公司 适用于ddr的信号传输电路
US9754093B2 (en) * 2014-08-28 2017-09-05 Ncr Corporation Methods and a system for automated authentication confidence
WO2016068938A1 (en) * 2014-10-30 2016-05-06 Hewlett-Packard Development Company, L.P. Ratioed logic with a high impedance load
CN106158006B (zh) * 2015-04-14 2019-05-17 中芯国际集成电路制造(上海)有限公司 输出缓冲器
KR20160148112A (ko) * 2015-06-15 2016-12-26 에스케이하이닉스 주식회사 출력 드라이버 및 이를 이용하는 반도체 장치 및 시스템
TWI590247B (zh) 2015-08-27 2017-07-01 新唐科技股份有限公司 驅動電路
US9910482B2 (en) * 2015-09-24 2018-03-06 Qualcomm Incorporated Memory interface with adjustable voltage and termination and methods of use
US10425386B2 (en) * 2016-05-11 2019-09-24 Oracle International Corporation Policy enforcement point for a multi-tenant identity and data security management cloud service
CN107452420B (zh) * 2016-05-31 2020-01-10 辰芯科技有限公司 存储装置和存储器控制器
KR102584637B1 (ko) 2016-08-22 2023-10-05 삼성전자주식회사 반도체 메모리 장치 및 반도체 장치
US10003335B2 (en) * 2016-08-25 2018-06-19 SK Hynix Inc. Data transmission device, and semiconductor device and system including the same
CN106656157A (zh) * 2016-11-18 2017-05-10 深圳市紫光同创电子有限公司 一种用于可编程逻辑器件的缓冲电路
CN108123709B (zh) * 2016-11-30 2021-08-06 上海复旦微电子集团股份有限公司 输出电路
KR102672957B1 (ko) * 2017-02-13 2024-06-10 에스케이하이닉스 주식회사 데이터 출력 버퍼
US10003336B1 (en) * 2017-03-14 2018-06-19 Xilinx, Inc. Integrated driver and termination circuit
KR102310508B1 (ko) * 2017-09-12 2021-10-08 에스케이하이닉스 주식회사 임피던스 조절 회로 및 이를 포함하는 집적 회로
US11063591B2 (en) 2017-10-20 2021-07-13 Marvell Asia Pte, Ltd. Multi-termination scheme interface
US10585835B1 (en) * 2018-11-20 2020-03-10 Micron Technology, Inc. Methods and apparatuses for independent tuning of on-die termination impedances and output driver impedances, and related semiconductor devices and systems
CN109741778A (zh) * 2018-12-29 2019-05-10 西安紫光国芯半导体有限公司 一种dram输出驱动电路及其减小漏电的方法
US10529412B1 (en) * 2019-04-09 2020-01-07 Micron Technology, Inc. Output buffer circuit with non-target ODT function
US10637474B1 (en) * 2019-07-09 2020-04-28 Nanya Technology Corporation OCD and associated DRAM
US10896143B1 (en) * 2019-12-19 2021-01-19 Micron Technology, Inc. Configurable termination circuitry
CN112636717B (zh) * 2020-12-30 2025-09-16 深圳市紫光同创电子股份有限公司 阻抗校准电路和方法
CN114765040B (zh) * 2021-01-11 2025-01-24 长鑫存储技术有限公司 驱动电路
EP4200851B1 (en) * 2021-04-28 2025-06-04 Yangtze Memory Technologies Co., Ltd. Clock signal return scheme for data read in page buffer of memory device
US12160237B2 (en) 2021-06-24 2024-12-03 Stmicroelectronics International N.V. Integrated circuit with output driver that compensates for supply voltage variations
CN116107384B (zh) * 2021-11-11 2025-09-23 瑞昱半导体股份有限公司 具有自参考阻抗的集成电路
US11677399B1 (en) * 2022-01-04 2023-06-13 Nanya Technology Corporation Interface circuit
JP7490792B2 (ja) * 2022-03-25 2024-05-27 チャンシン メモリー テクノロジーズ インコーポレイテッド 制御方法、半導体メモリ及び電子機器
KR20250020709A (ko) * 2022-03-25 2025-02-11 창신 메모리 테크놀로지즈 아이엔씨 제어 방법, 반도체 메모리 및 전자 기기
KR102815432B1 (ko) * 2022-03-25 2025-05-29 창신 메모리 테크놀로지즈 아이엔씨 제어 방법, 반도체 메모리 및 전자 기기
CN114756497B (zh) * 2022-04-24 2025-07-04 湖南国科微电子股份有限公司 一种ddr电阻配置电路、连接控制方法及电子设备
US12130331B2 (en) 2022-09-29 2024-10-29 Nanya Technology Corporation Test interface circuit
CN115397079B (zh) * 2022-10-28 2023-04-28 深圳市爱图仕影像器材有限公司 一种通信阻抗匹配电路、灯具和灯具控制系统
CN116994533A (zh) * 2023-08-04 2023-11-03 深圳市航顺芯片技术研发有限公司 偏压适配模块、方法和lcd驱动芯片
CN118969032B (zh) * 2024-10-09 2025-02-07 长鑫科技集团股份有限公司 一种数据输入输出电路和存储器

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5134311A (en) * 1990-06-07 1992-07-28 International Business Machines Corporation Self-adjusting impedance matching driver
US5107230A (en) * 1991-04-26 1992-04-21 Hewlett-Packard Company Switched drivers providing backmatch impedance for circuit test systems
US5194765A (en) * 1991-06-28 1993-03-16 At&T Bell Laboratories Digitally controlled element sizing
US5457407A (en) * 1994-07-06 1995-10-10 Sony Electronics Inc. Binary weighted reference circuit for a variable impedance output buffer
US5666078A (en) * 1996-02-07 1997-09-09 International Business Machines Corporation Programmable impedance output driver
US5955894A (en) * 1997-06-25 1999-09-21 Sun Microsystems, Inc. Method for controlling the impedance of a driver circuit
US5990701A (en) * 1997-06-25 1999-11-23 Sun Microsystems, Inc. Method of broadly distributing termination for buses using switched terminators
US6060907A (en) * 1997-06-25 2000-05-09 Sun Microsystems, Inc. Impedance control circuit
JP3579856B2 (ja) * 1997-07-08 2004-10-20 株式会社日立製作所 半導体集積回路システム
US6087847A (en) * 1997-07-29 2000-07-11 Intel Corporation Impedance control circuit
JPH11185479A (ja) * 1997-12-22 1999-07-09 Toshiba Corp 半導体集積回路
US6064224A (en) * 1998-07-31 2000-05-16 Hewlett--Packard Company Calibration sharing for CMOS output driver
US6118310A (en) * 1998-11-04 2000-09-12 Agilent Technologies Digitally controlled output driver and method for impedance matching
US6166563A (en) * 1999-04-26 2000-12-26 Intel Corporation Method and apparatus for dual mode output buffer impedance compensation
US6255874B1 (en) * 1999-07-28 2001-07-03 National Semiconductor Corporation Transistor channel width and slew rate correction circuit and method
KR100308791B1 (ko) * 1999-09-07 2001-11-05 윤종용 반도체 장치의 프로그래머블 임피던스 콘트롤 출력회로 및 프로그래머블 임피던스 콘트롤 방법
US6326802B1 (en) * 1999-09-30 2001-12-04 Intel Corporation On-die adaptive arrangements for continuous process, voltage and temperature compensation
US6326829B1 (en) * 1999-10-14 2001-12-04 Hewlett-Packard Company Pulse latch with explicit, logic-enabled one-shot
US6501293B2 (en) * 1999-11-12 2002-12-31 International Business Machines Corporation Method and apparatus for programmable active termination of input/output devices
US6329836B1 (en) * 2000-05-26 2001-12-11 Sun Microsystems, Inc. Resistive arrayed high speed output driver with pre-distortion
US6445245B1 (en) * 2000-10-06 2002-09-03 Xilinx, Inc. Digitally controlled impedance for I/O of an integrated circuit device
US6509757B1 (en) * 2001-08-02 2003-01-21 Agilent Technologies, Inc. Binary weighted thermometer code for PVT controlled output drivers
JP3721117B2 (ja) * 2001-10-29 2005-11-30 エルピーダメモリ株式会社 入出力回路と基準電圧生成回路及び半導体集積回路
US6885959B2 (en) * 2002-10-29 2005-04-26 Intel Corporation Circuit and method for calibrating DRAM pullup Ron to pulldown Ron
US6937055B2 (en) * 2002-12-23 2005-08-30 Mosaic Systems, Inc. Programmable I/O buffer
US7119549B2 (en) * 2003-02-25 2006-10-10 Rambus Inc. Output calibrator with dynamic precision
US6847225B2 (en) * 2003-03-21 2005-01-25 Infineon Technologies Ag CML (current mode logic) OCD (off chip driver)—ODT (on die termination) circuit for bidirectional data transmission
JP3733128B2 (ja) * 2003-04-28 2006-01-11 トレックスデバイス株式会社 Ｄｃ／ｄｃコンバータの制御回路
JPWO2004112139A1 (ja) * 2003-06-10 2006-09-28 富士通株式会社 半導体装置とその製造方法
US6894529B1 (en) * 2003-07-09 2005-05-17 Integrated Device Technology, Inc. Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control
JP4258309B2 (ja) * 2003-08-01 2009-04-30 住友電気工業株式会社 半導体製造装置用サセプタおよびそれを搭載した半導体製造装置
KR100583636B1 (ko) * 2003-08-19 2006-05-26 삼성전자주식회사 단일의 기준 저항기를 이용하여 종결 회로 및 오프-칩구동 회로의 임피던스를 제어하는 장치
US6864704B1 (en) * 2003-09-24 2005-03-08 Altera Corporation Adjustable differential input and output drivers
JP4086757B2 (ja) * 2003-10-23 2008-05-14 Ｎｅｃエレクトロニクス株式会社 半導体集積回路の入出力インターフェース回路
US7133884B1 (en) 2003-11-26 2006-11-07 Bmc Software, Inc. Unobtrusive point-in-time consistent copies
US6967501B1 (en) * 2003-12-18 2005-11-22 Integrated Device Technology, Inc. Impedance-matched output driver circuits having enhanced predriver control
KR100533383B1 (ko) * 2004-03-12 2005-12-06 주식회사 하이닉스반도체 출력 드라이버 회로
KR100541557B1 (ko) * 2004-04-13 2006-01-10 삼성전자주식회사 메모리 모듈 및 이 모듈의 반도체 메모리 장치의 임피던스교정 방법
US7513637B2 (en) * 2004-12-23 2009-04-07 Nualight Limited Display cabinet illumination
US7135884B1 (en) 2005-01-13 2006-11-14 Advanced Micro Devices, Inc. Voltage mode transceiver having programmable voltage swing and external reference-based calibration
KR100575006B1 (ko) * 2005-04-12 2006-04-28 삼성전자주식회사 Ｏｃｄ 회로와 ｏｄｔ 회로를 제어할 수 있는 반도체 장치및 제어 방법
US7389194B2 (en) * 2005-07-06 2008-06-17 Rambus Inc. Driver calibration methods and circuits
JP2007036546A (ja) * 2005-07-26 2007-02-08 Nec Electronics Corp インピーダンス調整回路と方法
US20070024317A1 (en) 2005-07-29 2007-02-01 Hansen James E Apparatus for obtaining precision integrated resistors
KR100744039B1 (ko) 2005-09-27 2007-07-30 주식회사 하이닉스반도체 데이터 출력드라이버의 임피던스를 조정할 수 있는 반도체메모리 장치
KR100753035B1 (ko) * 2005-09-29 2007-08-30 주식회사 하이닉스반도체 온-다이 터미네이션 테스트 장치
KR100733430B1 (ko) * 2005-09-29 2007-06-29 주식회사 하이닉스반도체 반도체 메모리 장치
KR100879747B1 (ko) * 2006-06-30 2009-01-21 주식회사 하이닉스반도체 데이터 입출력드라이버의 임피던스를 조정할 수 있는반도체 장치
US7417452B1 (en) * 2006-08-05 2008-08-26 Altera Corporation Techniques for providing adjustable on-chip termination impedance
US7692446B2 (en) * 2006-08-24 2010-04-06 Hynix Semiconductor, Inc. On-die termination device
US7459930B2 (en) * 2006-11-14 2008-12-02 Micron Technology, Inc. Digital calibration circuits, devices and systems including same, and methods of operation
TW200910373A (en) * 2007-06-08 2009-03-01 Mosaid Technologies Inc Dynamic impedance control for input/output buffers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160108432A (ko) * 2014-01-16 2016-09-19 퀄컴 인코포레이티드 시스템 레벨 전력 분배 네트워크들에 대한 전압 의존적 다이 rc 모델링
KR20170064842A (ko) * 2015-12-02 2017-06-12 에스케이하이닉스 주식회사 송신 회로 및 반도체 장치

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US8847623B2 (en) 2014-09-30
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US8035413B2 (en) 2011-10-11
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US20160277027A1 (en) 2016-09-22
US20150008956A1 (en) 2015-01-08
US20120019282A1 (en) 2012-01-26
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EP2171844B1 (en) 2014-06-25
US9300291B2 (en) 2016-03-29
CA2688277A1 (en) 2008-12-11
US7834654B2 (en) 2010-11-16
US20080303546A1 (en) 2008-12-11
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