KR20070088258A - 다이 위에 적층된 역전된 패키지를 구비한 멀티 칩 패키지모듈 - Google Patents
다이 위에 적층된 역전된 패키지를 구비한 멀티 칩 패키지모듈 Download PDFInfo
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- KR20070088258A KR20070088258A KR1020067012034A KR20067012034A KR20070088258A KR 20070088258 A KR20070088258 A KR 20070088258A KR 1020067012034 A KR1020067012034 A KR 1020067012034A KR 20067012034 A KR20067012034 A KR 20067012034A KR 20070088258 A KR20070088258 A KR 20070088258A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
크기 | 전체 패키지 높이 "OT" (Max) | ||||
1.4mm | 1.2mm | 1.0mm | 0.8mm | ||
몰드 캡 | 다이 두께 "CT" (Max) | 0.150 | 0.132 | 0.087 | |
스페이서 다이 두께 "SPT" (Max) | 0.125 | 0.125 | 0.087 | ||
루프 높이 "LH" (Max) | 0.115 | 0.089 | 0.075 | ||
몰드 높이 "MH" (Nom) | 0.070 | 0.650 | 0.500 | 0.370 | |
기판 | 기판 두께 "ST" (Nom) | 0.260 | 0.210 | 0.190 | 0.170 |
볼 | 볼 직경 "BD" (Nom) | 0.400 | 0.350 | 0.350 | 0.300 |
(옵션) "BD" (Min) | 0.450 | 0.300 | 0.350 | ||
붕괴 높이 "CH" (Min) | 0.250 | 0.250 | 0.150 | 0.150 | |
(옵션) "CH" (Min) | 0.300 | 0.150 |
Claims (52)
- 다이 위에 적층된 역전된 패키지를 포함하는 멀티-칩 패키지 모듈.
- 적층된 제 1, 2 패키지들을 포함하는 멀티-칩 모듈에 있어서,각각의 패키지는 기판에 부착되는 다이를 포함하고, 상부 패키지는 역전되며, 상부 패키지는 하부 패키지의 다이 위에 적층되면서, 상부 패키지와 하부 패키지 다이 사이의 간격에 대한 설비가 제공되는 것을 특징으로 하는 멀티-칩 모듈.
- 적층된 제 1, 2 패키지들을 포함하는 멀티-칩 모듈에 있어서,제 1 패키지는 기판에 부착된 다이를 가진 BGA 패키지이고, 제 2 패키지는 기판에 부착된 다이를 포함하며, 상기 제 2 패키지는 역전되어, 다이가 부착되는 기판 표면이 하향을 향하고, 역전된 패키지는 제 1 패키지 다이 위에 고정되면서, 제 1 패키지 다이와 역전된 제 2 패키지 사이에 간격에 대한 설비가 제공되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 2 패키지가 LGA 패키지인 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 2 패키지는 소-싱귤레이션 패키지(saw- singulated package)인 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 2 패키지가 칩 스케일 패키지인 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 2 패키지가 테이프-기반 패키지 기판을 가지는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 2 패키지가 범프 칩 캐리어 패키지인 것을 특징으로 하는 멀티-칩 모듈.
- 제 1 패키지 상의 다이 위에 역전되어 적층되는 제 2 패키지를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 9 항에 있어서, 상기 제 1 패키지가 BGA 패키지를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 9 항에 있어서, 상기 제 1 패키지가 기판에 장착된 한개 이상의 다이를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 9 항에 있어서, 제 1 패키지 다이는 와이어 본드에 의해 제 1 패키지 기판에 연결되고, 다이의 상향 사이드에 스페이서가 고정되며, 스페이서의 상향 사이드에 역전된 패키지가 고정되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 9 항에 있어서, 역전된 패키지와 제 1 패키지 간의 z-인터커넥트가 와이어 본드를 기반으로 하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 13 항에 있어서, 와이어 본드들이, 역전된 제 2 패키지의 상향 사이드 상의 z-인터커넥트 와이어 본드 패드들을, 하부 패키지 다이 상의 패드들과 연결하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 13 항에 있어서, 와이어 본드들이, 역전된 제 2 패키지의 상향 사이드 상의 와이어 본드 패드들을, 제 1 패키지 기판의 상향 사이드 상의 z-인터커넥트 와이어 본드 패드들과 연결하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 13 항에 있어서, 와이어 본드들이, 역전된 제 2 패키지의 상향 사이드 상의 와이어 본드 패드들을, 제 1 패키지 기판의 상향 사이드 상의 z-인터커넥트 와이어 본드 패드들과 연결하며,와이어 본드들이, 역전된 제 2 패키지의 상향 사이드 상의 z-인터커넥트 와이어 본드 패드들을, 하부 패키지 다이 상의 패드들과 연결하는 것을 특징으로 하 는 멀티-칩 모듈.
- 제 3 항에 있어서, 제 2 패키지 다이와 제 2 패키지 기판의 연결은 플립 칩 또는 와이어 본드 인터커넥트에 의해 구현되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지가 래미네이트 기판 LGA를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지가 테이프-기반 LGA를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지가 QFN 패키지를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지가 BCC 패키지를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지가 한개 이상의 다이를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 22 항에 있어서, 역전된 제 2 패키지가 다수의 다이를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 1 패키지가 한개 이상의 다이를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 1 패키지가 다수의 다이를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 1 패키지가 다수의 적층된 다이들을 포함하고, 역전된 제 2 패키지가 적층된 다이 중 가장 위의 다이 위에 장착되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 1 패키지가 제 1 기판에 본딩된 플립 칩 다이를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 제 1 패키지가 제 2 기판에 본딩된 플립 칩 다이를 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 제 2 패키지 위에 열 스프레더를 추가로 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 래미네이트 기판을 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 빌드-업 기판(build-up substrate)을 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 가요성 기판을 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 세라믹 기판을 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지 위에 장착되는 추가 패키지를 추가로 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 34 항에 있어서, 역전된 제 2 패키지 기판에 추가 LGA 패키지가 와이어 본딩되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 34 항에 있어서, 제 1 패키지 기판에 추가 LGA 패키지가 와이어 본딩되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지 위에 장착되는 추가 다이를 추가로 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 37 항에 있어서, 상기 추가 다이가 상부 패키지 기판에 와이어 본딩되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 37 항에 있어서, 상기 추가 다이가 하부 패키지 기판에 와이어 본딩되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 열 스프레더를 추가로 포함하는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 열 스프레더는 가장 위에 놓인 패키지의 상향 표면에 고정되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 제 2 패키지의 추가 다이의 상향 표면에 열 스프레더가 고정되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 역전된 제 2 패키지가 모듈의 가장 위에 놓인 패키지이고, 역전된 제 2 패키지의 상향 사이드에 열 스프레더가 고정되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 상기 모듈의 가장 위 표면에서 열 스프레더가 몰딩되는 것을 특징으로 하는 멀티-칩 모듈.
- 제 3 항에 있어서, 전기절연성의 열전도성 몰딩이 모듈 캡슐화에 사용되는 것을 특징으로 하는 멀티-칩 모듈.
- 다이 위에 적층된 역전된 패키지를 구비한 멀티-칩 패키지 모듈을 제작하는 방법에 있어서, 이 방법은,- 제 1 패키지 기판의 상향 사이드에 부착되는 제 1 다이를 가진 제 1 패키지를 제공하는 단계, 그리고- 상기 제 1 패키지 상의 다이 위에 역전된 제 2 패키지를 적층하는 단계를 포함하며, 이때, 제 2 패키지의 하향 사이드와, 제 1 다이를 제 1 패키지 기판에 연결하는 와이어 본드들 간에 임팩트에 의한 손상을 방지하기 위해 제 2 패키지와 제 1 패키지 다이 간에 스탠드오프(standoff)를 제공하는 것을 특징으로 하는 멀티-칩 패키지 모듈 제작 방법.
- 다이 위에 적층되는 역전된 패키지를 구비한 멀티-칩 패키지 모듈들을 제작하는 방법에 있어서, 상기 방법은,- 제 1 기판에 제 1 다이를 부착하는 단계,- 상기 제 1 다이를 상기 제 1 기판에 와이어 본딩하는 단계,- 제 1 다이 위에 스페이서를 고정하는 단계,- 상기 스페이서 위에 역전된 상부 패키지를 고정하는 단계,- z-인터커넥트 와이어 본딩을 위한 와이어 본드 위치들을 마련하도록 제 1 플라즈마 세척을 수행하는 단계,- z-인터커넥트 와이어 본딩을 수행하는 단계,- 몰딩의 양호한 접착을 위한 표면을 마련하도록 제 2 플라즈마 세척을 수행하는 단계,- 몰딩을 공급 및 경화시키는 단계, 그리고- 솔더 볼들을 부착하는 단계를 포함하는 것을 특징으로 하는 멀티-칩 패키지 모듈 제작 방법.
- 제 47 항에 있어서, z-인터커넥트 와이어 본딩 수행 이후,- 제 2 패키지의 상향 사이드에 접착제를 도포하는 단계,- 상기 접착제 위에 열 스프레더를 배치하는 단계, 그리고- 상기 접착제를 경화하는 단계를 추가로 포함하는 것을 특징으로 하는 멀티-칩 패키지 모듈 제작 방법.
- 제 47 항에 있어서, z-인터커넥트 와이어 본딩 수행 이후,- 열 스프레더를 몰드 캐버티 내에 배치하는 단계,- 상기 몰드 캐버니 내의 열 스프레더 위에, 제 1 다이 위에 고정된 조립된 역전 패키지를 배치하는 단계,- 몰딩 화합물을 캐버티에 공급하는 단계, 그리고- 몰딩 화합물을 경화하는 단계를 추가로 포함하는 것을 특징으로 하는 멀티-칩 패키지 모듈 제작 방법.
- 다이 위에 적층된, 역전된 패키지를 구비한 멀티-칩 패키지 모듈을 구비한 컴퓨터.
- 다이 위에 적층된, 역전된 패키지를 구비한 멀티-칩 패키지 모듈을 구비한 휴대용 전자 기기.
- 다이 위에 적층된, 역전된 패키지를 구비한 멀티-칩 패키지 모듈을 구비한 이동 통신 기기.
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PCT/US2004/042413 WO2005059967A2 (en) | 2003-12-17 | 2004-12-16 | Multiple chip package module having inverted package stacked over die |
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JP (1) | JP5197961B2 (ko) |
KR (1) | KR101076537B1 (ko) |
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WO (1) | WO2005059967A2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11308257B1 (en) | 2020-12-15 | 2022-04-19 | International Business Machines Corporation | Stacked via rivets in chip hotspots |
Families Citing this family (123)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100401020B1 (ko) * | 2001-03-09 | 2003-10-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체칩의 스택킹 구조 및 이를 이용한 반도체패키지 |
US6856009B2 (en) | 2003-03-11 | 2005-02-15 | Micron Technology, Inc. | Techniques for packaging multiple device components |
TWI283467B (en) * | 2003-12-31 | 2007-07-01 | Advanced Semiconductor Eng | Multi-chip package structure |
KR101313391B1 (ko) | 2004-11-03 | 2013-10-01 | 테세라, 인코포레이티드 | 적층형 패키징 |
US7745918B1 (en) | 2004-11-24 | 2010-06-29 | Amkor Technology, Inc. | Package in package (PiP) |
KR100593703B1 (ko) * | 2004-12-10 | 2006-06-30 | 삼성전자주식회사 | 돌출부 와이어 본딩 구조 보강용 더미 칩을 포함하는반도체 칩 적층 패키지 |
US7822912B2 (en) * | 2005-03-14 | 2010-10-26 | Phision Electronics Corp. | Flash storage chip and flash array storage system |
US8395251B2 (en) * | 2005-05-12 | 2013-03-12 | Stats Chippac Ltd. | Integrated circuit package to package stacking system |
US20060284298A1 (en) * | 2005-06-15 | 2006-12-21 | Jae Myun Kim | Chip stack package having same length bonding leads |
SG130055A1 (en) | 2005-08-19 | 2007-03-20 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices |
US7291900B2 (en) | 2005-08-25 | 2007-11-06 | Micron Technology, Inc. | Lead frame-based semiconductor device packages incorporating at least one land grid array package |
US8796836B2 (en) | 2005-08-25 | 2014-08-05 | Micron Technology, Inc. | Land grid array semiconductor device packages |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
JP5522561B2 (ja) * | 2005-08-31 | 2014-06-18 | マイクロン テクノロジー, インク. | マイクロ電子デバイスパッケージ、積重ね型マイクロ電子デバイスパッケージ、およびマイクロ電子デバイスを製造する方法 |
CN100433327C (zh) * | 2005-09-15 | 2008-11-12 | 南茂科技股份有限公司 | 芯片封装体与堆叠型芯片封装结构 |
US20070165457A1 (en) * | 2005-09-30 | 2007-07-19 | Jin-Ki Kim | Nonvolatile memory system |
US7652922B2 (en) | 2005-09-30 | 2010-01-26 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
TWI543185B (zh) | 2005-09-30 | 2016-07-21 | 考文森智財管理公司 | 具有輸出控制之記憶體及其系統 |
JP4930970B2 (ja) * | 2005-11-28 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | マルチチップモジュール |
US8093717B2 (en) * | 2005-12-09 | 2012-01-10 | Intel Corporation | Microstrip spacer for stacked chip scale packages, methods of making same, methods of operating same, and systems containing same |
US20070138628A1 (en) * | 2005-12-15 | 2007-06-21 | Lam Ken M | Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package |
US8258599B2 (en) * | 2005-12-15 | 2012-09-04 | Atmel Corporation | Electronics package with an integrated circuit device having post wafer fabrication integrated passive components |
US8058101B2 (en) | 2005-12-23 | 2011-11-15 | Tessera, Inc. | Microelectronic packages and methods therefor |
CN100459124C (zh) * | 2005-12-30 | 2009-02-04 | 日月光半导体制造股份有限公司 | 多芯片封装结构 |
US20070158537A1 (en) * | 2006-01-10 | 2007-07-12 | Nanogate Optoelectronic Robot, Inc. | Package for Image Sensor and Identification Module |
US7768083B2 (en) | 2006-01-20 | 2010-08-03 | Allegro Microsystems, Inc. | Arrangements for an integrated sensor |
US20070170599A1 (en) * | 2006-01-24 | 2007-07-26 | Masazumi Amagai | Flip-attached and underfilled stacked semiconductor devices |
US7675180B1 (en) | 2006-02-17 | 2010-03-09 | Amkor Technology, Inc. | Stacked electronic component package having film-on-wire spacer |
US20080237824A1 (en) * | 2006-02-17 | 2008-10-02 | Amkor Technology, Inc. | Stacked electronic component package having single-sided film spacer |
US8120156B2 (en) * | 2006-02-17 | 2012-02-21 | Stats Chippac Ltd. | Integrated circuit package system with die on base package |
US20070231970A1 (en) * | 2006-03-31 | 2007-10-04 | Tsuyoshi Fukuo | Cured mold compound spacer for stacked-die package |
TWI296148B (en) * | 2006-04-28 | 2008-04-21 | Advanced Semiconductor Eng | Stackable semiconductor package and the method for making the same |
US7633144B1 (en) | 2006-05-24 | 2009-12-15 | Amkor Technology, Inc. | Semiconductor package |
TWI298198B (en) * | 2006-05-30 | 2008-06-21 | Advanced Semiconductor Eng | Stackable semiconductor package |
TWI339436B (en) * | 2006-05-30 | 2011-03-21 | Advanced Semiconductor Eng | Stackable semiconductor package |
US7838971B2 (en) * | 2006-07-11 | 2010-11-23 | Atmel Corporation | Method to provide substrate-ground coupling for semiconductor integrated circuit dice constructed from SOI and related materials in stacked-die packages |
US7932590B2 (en) * | 2006-07-13 | 2011-04-26 | Atmel Corporation | Stacked-die electronics package with planar and three-dimensional inductor elements |
JP5069879B2 (ja) * | 2006-07-31 | 2012-11-07 | 三洋電機株式会社 | 回路装置 |
US7687892B2 (en) * | 2006-08-08 | 2010-03-30 | Stats Chippac, Ltd. | Quad flat package |
TWI317993B (en) * | 2006-08-18 | 2009-12-01 | Advanced Semiconductor Eng | Stackable semiconductor package |
KR100809701B1 (ko) * | 2006-09-05 | 2008-03-06 | 삼성전자주식회사 | 칩간 열전달 차단 스페이서를 포함하는 멀티칩 패키지 |
US8269319B2 (en) * | 2006-10-13 | 2012-09-18 | Tessera, Inc. | Collective and synergistic MRAM shields |
US8154881B2 (en) * | 2006-11-13 | 2012-04-10 | Telecommunication Systems, Inc. | Radiation-shielded semiconductor assembly |
EP3540736B1 (en) * | 2006-12-14 | 2023-07-26 | Rambus Inc. | Multi-die memory device |
WO2008074185A1 (en) * | 2006-12-19 | 2008-06-26 | Intel Corporation | Integrated circuit package and its manufacturing method, memory system |
US7687897B2 (en) * | 2006-12-28 | 2010-03-30 | Stats Chippac Ltd. | Mountable integrated circuit package-in-package system with adhesive spacing structures |
US7714377B2 (en) * | 2007-04-19 | 2010-05-11 | Qimonda Ag | Integrated circuits and methods of manufacturing thereof |
US7915667B2 (en) * | 2008-06-11 | 2011-03-29 | Qimonda Ag | Integrated circuits having a contact region and methods for manufacturing the same |
US7969018B2 (en) * | 2008-07-15 | 2011-06-28 | Infineon Technologies Ag | Stacked semiconductor chips with separate encapsulations |
KR101007932B1 (ko) * | 2008-07-25 | 2011-01-14 | 세크론 주식회사 | 패턴 위치 결정 방법, 캐비티 위치 결정 방법 및 솔더 범프형성 방법 |
DE102008054735A1 (de) * | 2008-12-16 | 2010-06-17 | Robert Bosch Gmbh | Leadless-Gehäusepackung |
US8533853B2 (en) | 2009-06-12 | 2013-09-10 | Telecommunication Systems, Inc. | Location sensitive solid state drive |
JP2011077108A (ja) * | 2009-09-29 | 2011-04-14 | Elpida Memory Inc | 半導体装置 |
KR20110074135A (ko) * | 2009-12-24 | 2011-06-30 | 삼성전자주식회사 | 내장 회로 기판을 구비한 시스템 인 패키지 |
US9159708B2 (en) * | 2010-07-19 | 2015-10-13 | Tessera, Inc. | Stackable molded microelectronic packages with area array unit connectors |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
KR101075241B1 (ko) | 2010-11-15 | 2011-11-01 | 테세라, 인코포레이티드 | 유전체 부재에 단자를 구비하는 마이크로전자 패키지 |
US20120146206A1 (en) | 2010-12-13 | 2012-06-14 | Tessera Research Llc | Pin attachment |
US8618659B2 (en) | 2011-05-03 | 2013-12-31 | Tessera, Inc. | Package-on-package assembly with wire bonds to encapsulation surface |
KR101128063B1 (ko) | 2011-05-03 | 2012-04-23 | 테세라, 인코포레이티드 | 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리 |
US9105483B2 (en) | 2011-10-17 | 2015-08-11 | Invensas Corporation | Package-on-package assembly with wire bond vias |
US8749037B1 (en) * | 2011-10-28 | 2014-06-10 | Altera Corporation | Multi-access memory system and a method to manufacture the system |
US9502360B2 (en) * | 2012-01-11 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress compensation layer for 3D packaging |
US8946757B2 (en) | 2012-02-17 | 2015-02-03 | Invensas Corporation | Heat spreading substrate with embedded interconnects |
US8372741B1 (en) | 2012-02-24 | 2013-02-12 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
US9349706B2 (en) | 2012-02-24 | 2016-05-24 | Invensas Corporation | Method for package-on-package assembly with wire bonds to encapsulation surface |
KR20130105175A (ko) * | 2012-03-16 | 2013-09-25 | 삼성전자주식회사 | 보호 층을 갖는 반도체 패키지 및 그 형성 방법 |
US9768137B2 (en) * | 2012-04-30 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stud bump structure for semiconductor package assemblies |
US8835228B2 (en) | 2012-05-22 | 2014-09-16 | Invensas Corporation | Substrate-less stackable package with wire-bond interconnect |
US9385006B2 (en) | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
US9391008B2 (en) | 2012-07-31 | 2016-07-12 | Invensas Corporation | Reconstituted wafer-level package DRAM |
US9502390B2 (en) | 2012-08-03 | 2016-11-22 | Invensas Corporation | BVA interposer |
US9418971B2 (en) * | 2012-11-08 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure including a thermal isolation material and method of forming the same |
US8975738B2 (en) | 2012-11-12 | 2015-03-10 | Invensas Corporation | Structure for microelectronic packaging with terminals on dielectric mass |
US8878353B2 (en) | 2012-12-20 | 2014-11-04 | Invensas Corporation | Structure for microelectronic packaging with bond elements to encapsulation surface |
US9136254B2 (en) | 2013-02-01 | 2015-09-15 | Invensas Corporation | Microelectronic package having wire bond vias and stiffening layer |
JP6128993B2 (ja) * | 2013-06-28 | 2017-05-17 | キヤノン株式会社 | 積層型半導体装置、プリント回路板、電子機器及び積層型半導体装置の製造方法 |
US9023691B2 (en) | 2013-07-15 | 2015-05-05 | Invensas Corporation | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
US8883563B1 (en) | 2013-07-15 | 2014-11-11 | Invensas Corporation | Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation |
US9034696B2 (en) | 2013-07-15 | 2015-05-19 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
US9685365B2 (en) | 2013-08-08 | 2017-06-20 | Invensas Corporation | Method of forming a wire bond having a free end |
US20150076714A1 (en) | 2013-09-16 | 2015-03-19 | Invensas Corporation | Microelectronic element with bond elements to encapsulation surface |
US9082753B2 (en) | 2013-11-12 | 2015-07-14 | Invensas Corporation | Severing bond wire by kinking and twisting |
US9087815B2 (en) | 2013-11-12 | 2015-07-21 | Invensas Corporation | Off substrate kinking of bond wire |
US9379074B2 (en) | 2013-11-22 | 2016-06-28 | Invensas Corporation | Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects |
US9583456B2 (en) | 2013-11-22 | 2017-02-28 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9263394B2 (en) | 2013-11-22 | 2016-02-16 | Invensas Corporation | Multiple bond via arrays of different wire heights on a same substrate |
US9735082B2 (en) | 2013-12-04 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3DIC packaging with hot spot thermal management features |
US9667900B2 (en) * | 2013-12-09 | 2017-05-30 | Optiz, Inc. | Three dimensional system-on-chip image sensor package |
US9583411B2 (en) | 2014-01-17 | 2017-02-28 | Invensas Corporation | Fine pitch BVA using reconstituted wafer with area array accessible for testing |
US9214454B2 (en) | 2014-03-31 | 2015-12-15 | Invensas Corporation | Batch process fabrication of package-on-package microelectronic assemblies |
US10381326B2 (en) | 2014-05-28 | 2019-08-13 | Invensas Corporation | Structure and method for integrated circuits packaging with increased density |
US9646917B2 (en) | 2014-05-29 | 2017-05-09 | Invensas Corporation | Low CTE component with wire bond interconnects |
US9412714B2 (en) | 2014-05-30 | 2016-08-09 | Invensas Corporation | Wire bond support structure and microelectronic package including wire bonds therefrom |
US9899794B2 (en) * | 2014-06-30 | 2018-02-20 | Texas Instruments Incorporated | Optoelectronic package |
US9627367B2 (en) * | 2014-11-21 | 2017-04-18 | Micron Technology, Inc. | Memory devices with controllers under memory packages and associated systems and methods |
US9735084B2 (en) | 2014-12-11 | 2017-08-15 | Invensas Corporation | Bond via array for thermal conductivity |
US9888579B2 (en) | 2015-03-05 | 2018-02-06 | Invensas Corporation | Pressing of wire bond wire tips to provide bent-over tips |
US9502372B1 (en) | 2015-04-30 | 2016-11-22 | Invensas Corporation | Wafer-level packaging using wire bond wires in place of a redistribution layer |
US9761554B2 (en) | 2015-05-07 | 2017-09-12 | Invensas Corporation | Ball bonding metal wire bond wires to metal pads |
US9786632B2 (en) * | 2015-07-30 | 2017-10-10 | Mediatek Inc. | Semiconductor package structure and method for forming the same |
US9490222B1 (en) | 2015-10-12 | 2016-11-08 | Invensas Corporation | Wire bond wires for interference shielding |
US10490528B2 (en) | 2015-10-12 | 2019-11-26 | Invensas Corporation | Embedded wire bond wires |
US10332854B2 (en) | 2015-10-23 | 2019-06-25 | Invensas Corporation | Anchoring structure of fine pitch bva |
US10181457B2 (en) | 2015-10-26 | 2019-01-15 | Invensas Corporation | Microelectronic package for wafer-level chip scale packaging with fan-out |
US9911718B2 (en) | 2015-11-17 | 2018-03-06 | Invensas Corporation | ‘RDL-First’ packaged microelectronic device for a package-on-package device |
US9659848B1 (en) | 2015-11-18 | 2017-05-23 | Invensas Corporation | Stiffened wires for offset BVA |
KR102372300B1 (ko) * | 2015-11-26 | 2022-03-08 | 삼성전자주식회사 | 스택 패키지 및 그 제조 방법 |
US9984992B2 (en) | 2015-12-30 | 2018-05-29 | Invensas Corporation | Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces |
US9704819B1 (en) * | 2016-03-29 | 2017-07-11 | Hong Kong Applied Science And Technology Research Institute Co. Ltd. | Three dimensional fully molded power electronics module having a plurality of spacers for high power applications |
US9935075B2 (en) | 2016-07-29 | 2018-04-03 | Invensas Corporation | Wire bonding method and apparatus for electromagnetic interference shielding |
US9859255B1 (en) * | 2016-10-01 | 2018-01-02 | Intel Corporation | Electronic device package |
KR20180055635A (ko) * | 2016-11-14 | 2018-05-25 | 삼성전자주식회사 | 반도체 모듈 |
US10299368B2 (en) | 2016-12-21 | 2019-05-21 | Invensas Corporation | Surface integrated waveguides and circuit structures therefor |
US10935612B2 (en) | 2018-08-20 | 2021-03-02 | Allegro Microsystems, Llc | Current sensor having multiple sensitivity ranges |
JP7094828B2 (ja) * | 2018-08-21 | 2022-07-04 | キヤノン株式会社 | 集積回路装置 |
US20200402958A1 (en) * | 2019-06-20 | 2020-12-24 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages and methods of manufacturing the same |
US11293979B2 (en) | 2019-10-22 | 2022-04-05 | Peter Shun Shen Wang | Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die |
CN113539989B (zh) * | 2020-04-13 | 2023-07-21 | 烽火通信科技股份有限公司 | 一种多芯片散热封装结构及封装方法 |
TWI761864B (zh) * | 2020-06-19 | 2022-04-21 | 海華科技股份有限公司 | 散熱式晶片級封裝結構 |
US11567108B2 (en) | 2021-03-31 | 2023-01-31 | Allegro Microsystems, Llc | Multi-gain channels for multi-range sensor |
TWI765791B (zh) * | 2021-07-30 | 2022-05-21 | 華碩電腦股份有限公司 | 印刷電路板與具有該印刷電路板之電子裝置 |
Family Cites Families (124)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02312265A (ja) * | 1989-05-26 | 1990-12-27 | Mitsubishi Electric Corp | 半導体装置 |
US5446620A (en) | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
FR2670322B1 (fr) | 1990-12-05 | 1997-07-04 | Matra Espace | Modules de memoire a l'etat solide et dispositifs de memoire comportant de tels modules |
JPH05152505A (ja) | 1991-11-25 | 1993-06-18 | Fujitsu Ltd | 電子回路実装基板 |
JPH05160170A (ja) | 1991-12-10 | 1993-06-25 | Fujitsu Ltd | 半導体装置の製造方法及び製造装置 |
JPH05206365A (ja) | 1992-01-30 | 1993-08-13 | Fuji Electric Co Ltd | 半導体装置およびその組立用リードフレーム |
US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5422435A (en) | 1992-05-22 | 1995-06-06 | National Semiconductor Corporation | Stacked multi-chip modules and method of manufacturing |
FR2694840B1 (fr) | 1992-08-13 | 1994-09-09 | Commissariat Energie Atomique | Module multi-puces à trois dimensions. |
US5340771A (en) | 1993-03-18 | 1994-08-23 | Lsi Logic Corporation | Techniques for providing high I/O count connections to semiconductor dies |
US5444296A (en) | 1993-11-22 | 1995-08-22 | Sun Microsystems, Inc. | Ball grid array packages for high speed applications |
US5675180A (en) * | 1994-06-23 | 1997-10-07 | Cubic Memory, Inc. | Vertical interconnect process for silicon segments |
US5436203A (en) | 1994-07-05 | 1995-07-25 | Motorola, Inc. | Shielded liquid encapsulated semiconductor device and method for making the same |
MY112145A (en) | 1994-07-11 | 2001-04-30 | Ibm | Direct attachment of heat sink attached directly to flip chip using flexible epoxy |
US5652185A (en) | 1995-04-07 | 1997-07-29 | National Semiconductor Corporation | Maximized substrate design for grid array based assemblies |
DE69634376D1 (de) * | 1995-05-12 | 2005-03-31 | St Microelectronics Inc | IC-Packungsfassungssystem mit niedrigem Profil |
US5719440A (en) | 1995-12-19 | 1998-02-17 | Micron Technology, Inc. | Flip chip adaptor package for bare die |
US7166495B2 (en) | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
US6075289A (en) | 1996-10-24 | 2000-06-13 | Tessera, Inc. | Thermally enhanced packaged semiconductor assemblies |
US5994166A (en) | 1997-03-10 | 1999-11-30 | Micron Technology, Inc. | Method of constructing stacked packages |
US5898219A (en) | 1997-04-02 | 1999-04-27 | Intel Corporation | Custom corner attach heat sink design for a plastic ball grid array integrated circuit package |
JP2964983B2 (ja) | 1997-04-02 | 1999-10-18 | 日本電気株式会社 | 三次元メモリモジュール及びそれを用いた半導体装置 |
JPH10294423A (ja) | 1997-04-17 | 1998-11-04 | Nec Corp | 半導体装置 |
US5982633A (en) | 1997-08-20 | 1999-11-09 | Compaq Computer Corporation | Opposed ball grid array mounting |
JP3834426B2 (ja) | 1997-09-02 | 2006-10-18 | 沖電気工業株式会社 | 半導体装置 |
CA2218307C (en) | 1997-10-10 | 2006-01-03 | Gennum Corporation | Three dimensional packaging configuration for multi-chip module assembly |
JP3644662B2 (ja) | 1997-10-29 | 2005-05-11 | 株式会社ルネサステクノロジ | 半導体モジュール |
JPH11219984A (ja) | 1997-11-06 | 1999-08-10 | Sharp Corp | 半導体装置パッケージおよびその製造方法ならびにそのための回路基板 |
US5899705A (en) | 1997-11-20 | 1999-05-04 | Akram; Salman | Stacked leads-over chip multi-chip module |
JP2000208698A (ja) | 1999-01-18 | 2000-07-28 | Toshiba Corp | 半導体装置 |
JP3178405B2 (ja) | 1998-03-05 | 2001-06-18 | 住友金属工業株式会社 | 熱応力を緩和した積層半導体装置モジュール |
TW434756B (en) | 1998-06-01 | 2001-05-16 | Hitachi Ltd | Semiconductor device and its manufacturing method |
US6451624B1 (en) | 1998-06-05 | 2002-09-17 | Micron Technology, Inc. | Stackable semiconductor package having conductive layer and insulating layers and method of fabrication |
US6034875A (en) | 1998-06-17 | 2000-03-07 | International Business Machines Corporation | Cooling structure for electronic components |
US5977640A (en) | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
JP3643706B2 (ja) * | 1998-07-31 | 2005-04-27 | 三洋電機株式会社 | 半導体装置 |
JP2000058691A (ja) | 1998-08-07 | 2000-02-25 | Sharp Corp | ミリ波半導体装置 |
US6051887A (en) * | 1998-08-28 | 2000-04-18 | Medtronic, Inc. | Semiconductor stacked device for implantable medical apparatus |
US6201302B1 (en) | 1998-12-31 | 2001-03-13 | Sampo Semiconductor Corporation | Semiconductor package having multi-dies |
JP3685947B2 (ja) | 1999-03-15 | 2005-08-24 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP4075204B2 (ja) * | 1999-04-09 | 2008-04-16 | 松下電器産業株式会社 | 積層型半導体装置 |
US6118176A (en) | 1999-04-26 | 2000-09-12 | Advanced Semiconductor Engineering, Inc. | Stacked chip assembly utilizing a lead frame |
US6890798B2 (en) | 1999-06-08 | 2005-05-10 | Intel Corporation | Stacked chip packaging |
US6238949B1 (en) | 1999-06-18 | 2001-05-29 | National Semiconductor Corporation | Method and apparatus for forming a plastic chip on chip package module |
JP3526788B2 (ja) | 1999-07-01 | 2004-05-17 | 沖電気工業株式会社 | 半導体装置の製造方法 |
SG87046A1 (en) | 1999-08-17 | 2002-03-19 | Micron Technology Inc | Multi-chip module with stacked dice |
US6424033B1 (en) | 1999-08-31 | 2002-07-23 | Micron Technology, Inc. | Chip package with grease heat sink and method of making |
WO2001018864A1 (fr) | 1999-09-03 | 2001-03-15 | Seiko Epson Corporation | Dispositif a semi-conducteurs, son procede de fabrication, carte de circuit et dispositif electronique |
JP2001156212A (ja) | 1999-09-16 | 2001-06-08 | Nec Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2001094045A (ja) | 1999-09-22 | 2001-04-06 | Seiko Epson Corp | 半導体装置 |
JP3415509B2 (ja) | 1999-09-28 | 2003-06-09 | エヌイーシーマイクロシステム株式会社 | 半導体装置 |
JP3485507B2 (ja) | 1999-10-25 | 2004-01-13 | 沖電気工業株式会社 | 半導体装置 |
JP2001127246A (ja) | 1999-10-29 | 2001-05-11 | Fujitsu Ltd | 半導体装置 |
US6376904B1 (en) | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
JP2001223326A (ja) | 2000-02-09 | 2001-08-17 | Hitachi Ltd | 半導体装置 |
KR100335717B1 (ko) * | 2000-02-18 | 2002-05-08 | 윤종용 | 고용량 메모리 카드 |
US6462421B1 (en) | 2000-04-10 | 2002-10-08 | Advanced Semicondcutor Engineering, Inc. | Multichip module |
JP2001308262A (ja) | 2000-04-26 | 2001-11-02 | Mitsubishi Electric Corp | 樹脂封止bga型半導体装置 |
TW445610B (en) * | 2000-06-16 | 2001-07-11 | Siliconware Precision Industries Co Ltd | Stacked-die packaging structure |
TW459361B (en) | 2000-07-17 | 2001-10-11 | Siliconware Precision Industries Co Ltd | Three-dimensional multiple stacked-die packaging structure |
US6472758B1 (en) | 2000-07-20 | 2002-10-29 | Amkor Technology, Inc. | Semiconductor package including stacked semiconductor dies and bond wires |
JP2002040095A (ja) | 2000-07-26 | 2002-02-06 | Nec Corp | 半導体装置及びその実装方法 |
US6607937B1 (en) | 2000-08-23 | 2003-08-19 | Micron Technology, Inc. | Stacked microelectronic dies and methods for stacking microelectronic dies |
JP3377001B2 (ja) | 2000-08-31 | 2003-02-17 | セイコーエプソン株式会社 | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP4570809B2 (ja) | 2000-09-04 | 2010-10-27 | 富士通セミコンダクター株式会社 | 積層型半導体装置及びその製造方法 |
US6492726B1 (en) | 2000-09-22 | 2002-12-10 | Chartered Semiconductor Manufacturing Ltd. | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection |
JP2002118201A (ja) | 2000-10-05 | 2002-04-19 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP3913481B2 (ja) | 2001-01-24 | 2007-05-09 | シャープ株式会社 | 半導体装置および半導体装置の製造方法 |
TW459363B (en) | 2000-11-22 | 2001-10-11 | Kingpak Tech Inc | Integrated circuit stacking structure and the manufacturing method thereof |
JP2002170921A (ja) * | 2000-12-01 | 2002-06-14 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP3798620B2 (ja) | 2000-12-04 | 2006-07-19 | 富士通株式会社 | 半導体装置の製造方法 |
US6340846B1 (en) | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
JP2002176136A (ja) | 2000-12-08 | 2002-06-21 | Mitsubishi Electric Corp | マルチチップパッケージ、半導体及び半導体製造装置 |
US6777819B2 (en) | 2000-12-20 | 2004-08-17 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with flash-proof device |
US6734539B2 (en) | 2000-12-27 | 2004-05-11 | Lucent Technologies Inc. | Stacked module package |
JP2002208656A (ja) | 2001-01-11 | 2002-07-26 | Mitsubishi Electric Corp | 半導体装置 |
JP2002222903A (ja) | 2001-01-26 | 2002-08-09 | Mitsubishi Electric Corp | 半導体パッケージ及び半導体装置 |
US6388313B1 (en) | 2001-01-30 | 2002-05-14 | Siliconware Precision Industries Co., Ltd. | Multi-chip module |
JP2002231885A (ja) * | 2001-02-06 | 2002-08-16 | Mitsubishi Electric Corp | 半導体装置 |
JP4780844B2 (ja) | 2001-03-05 | 2011-09-28 | Okiセミコンダクタ株式会社 | 半導体装置 |
TW502408B (en) | 2001-03-09 | 2002-09-11 | Advanced Semiconductor Eng | Chip with chamfer |
JP2002280516A (ja) | 2001-03-19 | 2002-09-27 | Toshiba Corp | 半導体モジュール |
SG108245A1 (en) | 2001-03-30 | 2005-01-28 | Micron Technology Inc | Ball grid array interposer, packages and methods |
US6400007B1 (en) | 2001-04-16 | 2002-06-04 | Kingpak Technology Inc. | Stacked structure of semiconductor means and method for manufacturing the same |
US6888240B2 (en) | 2001-04-30 | 2005-05-03 | Intel Corporation | High performance, low cost microelectronic circuit package with interposer |
US6472741B1 (en) * | 2001-07-14 | 2002-10-29 | Siliconware Precision Industries Co., Ltd. | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
JP2002373969A (ja) | 2001-06-15 | 2002-12-26 | Oki Electric Ind Co Ltd | 半導体装置及び半導体装置の製造方法 |
US6900528B2 (en) | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
US6734552B2 (en) | 2001-07-11 | 2004-05-11 | Asat Limited | Enhanced thermal dissipation integrated circuit package |
DE10138278C1 (de) * | 2001-08-10 | 2003-04-03 | Infineon Technologies Ag | Elektronisches Bauteil mit aufeinander gestapelten elektronischen Bauelementen und Verfahren zur Herstellung derselben |
KR100445073B1 (ko) | 2001-08-21 | 2004-08-21 | 삼성전자주식회사 | 듀얼 다이 패키지 |
US6787916B2 (en) | 2001-09-13 | 2004-09-07 | Tru-Si Technologies, Inc. | Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity |
US6847105B2 (en) | 2001-09-21 | 2005-01-25 | Micron Technology, Inc. | Bumping technology in stacked die configurations |
US6599779B2 (en) | 2001-09-24 | 2003-07-29 | St Assembly Test Service Ltd. | PBGA substrate for anchoring heat sink |
JP4917225B2 (ja) * | 2001-09-28 | 2012-04-18 | ローム株式会社 | 半導体装置 |
TW523887B (en) | 2001-11-15 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Semiconductor packaged device and its manufacturing method |
US6737750B1 (en) | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
US20030113952A1 (en) | 2001-12-19 | 2003-06-19 | Mahesh Sambasivam | Underfill materials dispensed in a flip chip package by way of a through hole |
TW523894B (en) | 2001-12-24 | 2003-03-11 | Siliconware Precision Industries Co Ltd | Semiconductor device and its manufacturing method |
JP3865055B2 (ja) | 2001-12-28 | 2007-01-10 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2003273317A (ja) | 2002-03-19 | 2003-09-26 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP3688249B2 (ja) | 2002-04-05 | 2005-08-24 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP3550391B2 (ja) | 2002-05-15 | 2004-08-04 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US6906415B2 (en) | 2002-06-27 | 2005-06-14 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor devices and methods |
US6600222B1 (en) * | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
KR100442880B1 (ko) | 2002-07-24 | 2004-08-02 | 삼성전자주식회사 | 적층형 반도체 모듈 및 그 제조방법 |
US7132311B2 (en) | 2002-07-26 | 2006-11-07 | Intel Corporation | Encapsulation of a stack of semiconductor dice |
US7053476B2 (en) | 2002-09-17 | 2006-05-30 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages |
US20040061213A1 (en) | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
US6972481B2 (en) | 2002-09-17 | 2005-12-06 | Chippac, Inc. | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
US6838761B2 (en) | 2002-09-17 | 2005-01-04 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
US7064426B2 (en) | 2002-09-17 | 2006-06-20 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages |
TWI322448B (en) | 2002-10-08 | 2010-03-21 | Chippac Inc | Semiconductor stacked multi-package module having inverted second package |
US7034387B2 (en) | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
TW567601B (en) | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
SG114585A1 (en) | 2002-11-22 | 2005-09-28 | Micron Technology Inc | Packaged microelectronic component assemblies |
TW576549U (en) | 2003-04-04 | 2004-02-11 | Advanced Semiconductor Eng | Multi-chip package combining wire-bonding and flip-chip configuration |
TWI225292B (en) | 2003-04-23 | 2004-12-11 | Advanced Semiconductor Eng | Multi-chips stacked package |
US6818980B1 (en) | 2003-05-07 | 2004-11-16 | Asat Ltd. | Stacked semiconductor package and method of manufacturing the same |
US7342248B2 (en) * | 2003-05-15 | 2008-03-11 | Shinko Electric Industries Co., Ltd. | Semiconductor device and interposer |
TWI299551B (en) * | 2003-06-25 | 2008-08-01 | Via Tech Inc | Quad flat no-lead type chip carrier |
US6930378B1 (en) | 2003-11-10 | 2005-08-16 | Amkor Technology, Inc. | Stacked semiconductor die assembly having at least one support |
US20060138631A1 (en) | 2003-12-31 | 2006-06-29 | Advanced Semiconductor Engineering, Inc. | Multi-chip package structure |
US20060043556A1 (en) | 2004-08-25 | 2006-03-02 | Chao-Yuan Su | Stacked packaging methods and structures |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11308257B1 (en) | 2020-12-15 | 2022-04-19 | International Business Machines Corporation | Stacked via rivets in chip hotspots |
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US20050133916A1 (en) | 2005-06-23 |
WO2005059967A2 (en) | 2005-06-30 |
US8970049B2 (en) | 2015-03-03 |
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WO2005059967A3 (en) | 2009-06-04 |
TW200536130A (en) | 2005-11-01 |
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