WO2008074185A1 - Integrated circuit package and its manufacturing method, memory system - Google Patents

Integrated circuit package and its manufacturing method, memory system Download PDF

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Publication number
WO2008074185A1
WO2008074185A1 PCT/CN2006/003477 CN2006003477W WO2008074185A1 WO 2008074185 A1 WO2008074185 A1 WO 2008074185A1 CN 2006003477 W CN2006003477 W CN 2006003477W WO 2008074185 A1 WO2008074185 A1 WO 2008074185A1
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WO
WIPO (PCT)
Prior art keywords
substrate
die
package
coupled
dies
Prior art date
Application number
PCT/CN2006/003477
Other languages
French (fr)
Inventor
Tingqing Wang
Ying Wang
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/CN2006/003477 priority Critical patent/WO2008074185A1/en
Publication of WO2008074185A1 publication Critical patent/WO2008074185A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/1433—Application-specific integrated circuit [ASIC]
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Definitions

  • SCSP Stacked Chip Scale Package
  • the dies may be coupled to the substrate with connecting lines, known as bond fingers.
  • connecting lines known as bond fingers.
  • SCSPs typically include one or more spacers provided between dies in the package.
  • spacers one of the problems with using spacers is that the size of the package is increased.
  • FIG. 1 is a cross-sectional view of an integrated circuit package according to an embodiment of the present invention.
  • FIGs. 2A-2E are cross-sectional views illustrating an embodiment of a method that may be used to manufacture the embodiment of FIG. 1.
  • FIG. 3 is a schematic diagram of an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of an integrated circuit package according to another embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of an integrated circuit package according to yet another embodiment of the present invention.
  • references in the specification to "one embodiment”, “an embodiment”, “an example embodiment”, etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
  • FIG. 1 illustrates an embodiment of a semiconductor package 100.
  • a second substrate 206 may be coupled to interconnects such as solder balls 326. While FIG. 1 is described with a ball grid array or solder ball, in some embodiments, other external interconnects may be utilized. For example, land grid arrays may also be utilized. In some embodiments, other numbers of dies, substrates, and arrangements may be used.
  • a first substrate 106 may be encapsulated within an encapsulant or molding compound 108 of a first assembly 110 or an encapsulant or molding compound 308. The first substrate 106 may be coupled to the second substrate 206. Any suitable substrate may be utilized, including flex substrates such as folded flex substrates or flexible polyimide tape, laminate substrates such as bismaleimide triazine (BT) substrates, buildup substrates, or ceramic substrates.
  • BT bismaleimide triazine
  • the first substrate 106 may be coupled to a set of dies.
  • the first substrate 106 may be coupled to a first die 102 and a second die 104 stacked on its lower side or surface 132; the first substrate 106 may be couple to a fifth die 302 and a six die 304 stacked on its upper side or surface 134.
  • die attach adhesives (not shown), such as epoxy, may be used to secure stacked dies to one another and to a substrate.
  • the adhesive may comprise epoxy and may be conductive or non-conductive. Some embodiments may comprise paste and/or adhesive tape, etc. In other embodiments, die attach adhesives may be not required.
  • the first substrate 106 may comprise one or more bond fingers on the upper side 134 and the lower side 132.
  • the first and second dies 102 and 104 may be wire bonded to the lower side 132 of the first substrate 106.
  • the fifth and six dies 302 and 304 may be wire bonded to the upper side 134 of the first substrate 106.
  • the second substrate 206 may be coupled to one or more dies, e.g., a third die 202 and a fourth die 204 stacked on the second substrate 206.
  • a spacer 210 may separate the assembly 110 that comprises the first substrate 106 from the assembly coupled to the second substrate 206; however, in other embodiments, the spacer 210 may be omitted. In another embodiment, the spacer 210 may allow for interconnecting, e.g., wire bonding, the upper die 202 to the second substrate 206.
  • any of the variety of SCSP including ultra-thin SCSP (UT-SCSP), may be utilized for the individual sets of substrates and stacked dies coupled thereto.
  • Any encapsulating or molding material may be utilized for the encapsulant 108 and/or 308.
  • the encapsulant or molding compound 108 and 308 may be the same material and, in some embodiments, they may be different materials.
  • Examples of the package 100 may comprise flash memory, static random access memory (SDRAM), digital signal processor (DSP), application specific integrated circuit (ASIC), logic circuits, and/or any other circuits or devices.
  • FIGs. 2A-2E illustrate an exemplary embodiment of a method of forming the package 100.
  • the first die 102 and the second die 104 may be mounted or attached to the upper side 132 of the first substrate 106 to form a die- substrate stack.
  • the second die 104 may be mounted to the upper side 132 of the first substrate 106 and the first die 102 may be mounted on top of the second die 104.
  • the first die 102 may be mounted on top of the second die 104.
  • the stack of the first and second dies 102 and 104 may be further mounted to the upper side 132 of the first substrate 106 with the second die 104 on top of the first substrate 106.
  • An adhesive e.g., epoxy resin etc.
  • an adhesive film may be used to bond the first and second dies 102 and 104 to the first substrate 106.
  • the adhesive may be not required.
  • the first and second dies 102 and 104 may be bonded, e.g., wire bonded, to the first substrate 106.
  • the first substrate 106 may include a printed circuit board (PCB) or a printed wiring board (PWB); however, other examples for the first substrate 106 may comprise flame retardant (FR-4), BT, and tape automated bonding (TAB) tape material, etc.
  • the first substrate 106 may be configured for one or more bond fingers or I/O terminals 126 on one surface, e.g., the upper side 132.
  • the bond fingers 126 may connect to one or more conductive traces or wires (not shown) on either or both sides of the first substrate 106.
  • the bond fingers 126 may be used to interconnect one or more dies (e.g. , the first and second dies 102 and 104) with the first substrate 106.
  • the first bond fingers 126 may provide locations for bond wires, e.g., bond . wires 112 and 114, to interconnect the dies 102 and 104 to the first substrate 106.
  • the first substrate 106 may comprise one or more bond fingers on both the upper and lower sides 132 and 134.
  • one or more bond fingers 136 may be provided on a lower side 134 of the first substrate 106.
  • FIG. 2A illustrates the embodiment that may use bond fingers 126 and/or 136, other embodiments may use one or more bond pads, bond areas or any other structure on either or both sides of the first substrate 106 for wire bonding.
  • the first die 102 may comprise one or more first bond pads 122 and the second die 104 may comprise one or more second bond pads 124; however, in some embodiments, the bond pads may comprise bond areas or any other structure to interconnect the first and second dies 102 and 104 to the first substrate 106.
  • each of the first and second dies 102 and 104 may comprise one or more bond pads on either or both the top and bottom surfaces 132 and 134.
  • the first die 102 may be coupled by wire bonds 112 to the bond finger side 132 of the first substrate 106.
  • the second die 104 may be coupled by wire bonds 114 to the bond finger side 132 of first substrate 106.
  • the wire bonds 112 may be used to interconnect a bond pad 122 on the first die 102 to a bond finger 126 on the bond finger side 132.
  • the wire bond 114 may be used to interconnect a bond pad 124 on the second die 104 with another bond finger 126 on the upper side 132 of the first substrate 106.
  • the wire bonds e.g., wire bonds 112 and 114, may be gold wire bonds but other metals may also be used, such as aluminum.
  • the die-substrate stack of FIG. 2A may be molded or encapsulated with an encapsulant or molding compound 108.
  • the molding compound 108 may encapsulate the first and second dies 102 and 104 and the upper side 132 of the first substrate 106.
  • the molding compound 108 may further encapsulate the bond wires 112 and 114 and the bond fingers 126 on the upper side 132 of the first substrate 106.
  • the bond fingers 136 on the bottom side 134 of the first substrate 106 may be exposed.
  • an embedded unit or an embedded package 110 may be formed.
  • the molding compound 108 may comprise epoxy resin or any other molding compound.
  • the molding compound 108 may comprise one or more filler, such as a hardener.
  • a second stack or laminate 120 may be formed.
  • the third die 202 and the fourth die 204 may be stacked on the second substrate 206.
  • An adhesive (not shown) or the like may be used to secure the stacked dies 202 and 204 to one another and the second substrate 206.
  • the third and fourth dies 202 and 204 may be coupled to the second substrate 206 by wire bonds 212 and 214, respectively.
  • the wire bond 212 may be used to connect a bond pad 222 on the third die 202 with a bond finger 226 on the second substrate 206.
  • the wire bond 214 may couple a bond pad 224 on the fourth die 204 to another bond finger 226 on the second substrate 206.
  • a third stack 130 e.g., a package-die stack may be formed.
  • the prepackage 110 of FIG. 2B may be stacked over the second substrate 206.
  • the prepackage 110 may be inverted and positioned over the third die 202.
  • the exposed side 134 of the first substrate 106 may become an upper side of the first substrate 106.
  • a spacer 210 may be provided between the prepackage 110 and the third die 202. The spacer 210 may separate the prepackage 110 from the assembly 120.
  • the molding compound 108 may contact the spacer 210.
  • One side 134 of the first substrate 106 where the bond fingers 136 of FIG. 2B locate may become an upper side of the package-die stack 130.
  • the opposite side 132 of the first substrate 106 may face the spacer 210 and/or the second substrate 206.
  • the fifth die 302 and the sixth die 304 may be mounted or stacked on the upper side 134 of the first substrate 106.
  • the fifth and sixth dies 302 and 304 may be mounted to the third stack 130 of FIG. 2D in a manner similar to that has mentioned with regard to the embodiment of FIG. 2A and/or FIG. 2C; however, other embodiments may apply a different manner.
  • an adhesive (not shown) or the like may be used to attach the fifth and sixth dies 302 and 304 to the third stack 130 of FIG. 2D.
  • the adhesive may be not required.
  • a spacer may not be needed between the prepackage 110 and the second stack 120.
  • the spacing function may be performed by encapsulant or molding compound 108 of FIG. 2B.
  • the encapsulant 108 may be patterned or shaped to space apart the prepackage 110 and the second stack 120.
  • a spacer between the prepackage 110 and the second package 120 may not be required.
  • the prepackage 110 may be disposed on the third die 202 with an area larger than that of the prepackage 110.
  • the prepackage 110 may be stacked on a bump die that is coupled to the second substrate. As shown in FIG. 2E, wire bonding may be performed to interconnect the fifth and sixth dies 302 and 304 and the first substrate 106.
  • the fifth die 302 may be wire bonded to the first substrate 106 by bond wires 312.
  • the six die 304 may be wire bonded to the first substrate 106 by bond wires 314.
  • a wire bond 312 may interconnect a bond pad 322 on the fifth die 302 with a bond finger 136 on the back side 134 of the first substrate 106.
  • a wire bond 314 may connect a bond pad 324 of the six die 304 to a bond finger 136 on the back side 134 of the first substrate 106.
  • the first substrate 106 may be coupled to the second substrate 206 by the wire bonds 332.
  • a wire bond 332 may be bonded to connect a bond finger 136 on the back side 134 of the first substrate 106 with a bond finger 226 on the second substrate 206.
  • the bond fingers 136 on the back surface 134 of the first substrate 106 may connect with one or more conductive traces (not shown) on either or both sides of the first substrate 106.
  • the bond fingers 226 on the second substrate 206 may be connect to one or more conductive traces (not shown) of the second substrate 206.
  • the package-die stack 140 may be molded or encapsulated, e.g., with molding compound 308 of FIG. 1 , to form the package 100.
  • molding compound 308 of FIG. 1 may be the same as the molding compound 108 of FIG. 2B, and in some embodiments, the molding compound 308 of FIG. 1 may be different from the molding compound 108 of FIG. 2B.
  • one or more solder balls or other interconnects 326 of FIG. 1 may be attached to the second substrate 206.
  • solder balls 326 may be soldered to one or more solder ball lands or pads (not shown) configured on the lower side 234 of the second substrate 206; however, other embodiments may mount the solder balls 326 to the second substrate 206 in a different manner.
  • solder balls 326 of FIG. 1 may be used in this embodiment, some embodiment may utilize any other interconnects that may electrically connect to the second substrate 206.
  • the lower side 234 may be configured for conductive adhesive film, or any other connectional material.
  • FIG. 3 illustrates an embodiment of a memory system 30 that may be formed in one package
  • a universal serial bus (USB) flash memory or any other memory may be formed in one package.
  • the memory system 30 may be formed in the package 100 with die 104 being omitted.
  • the memory system 30 may comprise a control 32 that may be implemented as the first die 102 on the first substrate 106.
  • the control 32 may comprise a memory controller, a digital signal processor (DSP), a processor, logic circuit or any other control unit or device.
  • the memory system 30 may comprise four flash memories 34a, 34b, 34c, and 34d that may coupled to the control 102.
  • the flash memory 34a may be implemented by the third die 202
  • the flash memory 34b may be implemented by the fourth die 204
  • the flash memory 34c may be implemented by the fifth die 302
  • the flash memory 34d may be implemented by the sixth die 304.
  • One or more interconnects 36 may couple the control 32 to the flash memories 34a-34d.
  • the interconnects 36 may be made up of the substrate 106, 206, as well as the wire bonds in the package 100 such as 112, 212, 214, 312, 314, 332 and the solder balls 326.
  • the memory system 30 may be coupled to an external I/O 38 via the second substrate 206 and the solder ball 326.
  • FIG. 3 is illustrated to use four flash memories 34a-34d, in some embodiments, other memory devices may be utilized, such as NOR, NAND, dynamic random access memory (DRAM). Again, in some embodiments, a different number of memory devices may be utilized.
  • FIG. 3 is illustrated to use four flash memories 34a-34d, in some embodiments, other memory devices may be utilized, such as NOR, NAND, dynamic random access memory (DRAM). Again, in some embodiments, a different number of memory devices may be utilized. Furthermore, while FIG.
  • dies 202 and 204 may be implemented as the control 32 and dies 102, 104, 302, and 304 may be implemented as the memory devices 34a-34d.
  • FIG. 4 illustrates an example embodiment of an integrated circuit package 400.
  • the package 400 may be formed in a manner similar to that has been described with regard to FIGs. 2A-2E.
  • the package 400 may comprise a first substrate 406 that may be secured in the package 400 by an encapsulant or molding compound 408 or 428.
  • a first die 402 and a second die 404 may be coupled to the first substrate 406.
  • the assembly that comprises the first substrate 406 including the first and second dies 402 and 404 may form an embedded package 410.
  • the first and second dies 402 and 404 may comprise one or more bond pads (not shown) or any other structure to interconnect with one or more bond fingers (not shown) etc. on a lower side 432 of the first substrate 406.
  • Example of the prepackage 410 may refer to the embodiment as shown in FIG. 2B.
  • the embedded unit 410 may be stacked on a die 412 to form a package-die stack.
  • the encapsulant 408 or 428 may separate the assembly 410 from the die 412.
  • the die 412 may be implemented as a bump die.
  • a lower side of the die 412 may be configured with bumps, solder balls, conductive protrusions or other interconnects 414.
  • the bump die 412 may be attached to a second substrate 416, e.g., the upper side of the second substrate 416.
  • the embedded unit 410 may be positioned over the bump die 412, e.g., the molding compound 408 may contact the upper side of the bump die 412 and the exposed upper side 434 may be opposite to the bump die 412.
  • the one or more bumps 414 may interconnect the bump die 412 with the second substrate 416 that may be configured with bump pads (not shown) on an upper side.
  • Example of the one or more bumps 414 may comprise bump balls, conductive protrusions, conductive contacts and/or any other structures that may couple the bump die 412 to the second substrate 416.
  • the second substrate 416 may utilize other structure to adapt with the bumps 414.
  • one or more dies may be attached to the embedded unit 410.
  • the third and fourth dies 422 and 424 may be mounted to an upper side 434 of the first substrate 406 that is opposite to the lower side 432.
  • the third and fourth dies 422 and 424 via one or more bond wires may be coupled to the first substrate 406 that may comprise one or more bond fingers or other interconnect (not shown) on the upper side 434.
  • the first substrate 406 may be further coupled to the second substrate 416 by one or more bond wires.
  • Example of the interconnection may refer to the description with regard to FIG. 2E.
  • molding may be performed to the assembly that may comprise the second substrate 416, the bump die 412, the embedded unit 410, the third die 422, and the fourth die 424.
  • molding compound 428 may be utilized; however, other embodiment may use any other molding material.
  • one or more solder ball 418 may be attached to the ball land (not shown) on the back side of the second substrate 416.
  • FIG. 5 illustrates an example embodiment of a package or unit 500.
  • the package 500 may be formed in a manner similar to that has been described with regard to FIGs. 2A-2E.
  • the package 500 may comprise an embedded substrate 506 that may form an embedded unit 510.
  • a first die 502 and a second die 504 may be secured to one another and the embedded substrate 506 that may be molded with the encapsulant or molding compound 508 or 528.
  • the first and second dies 502 and 504 may be coupled to the embedded substrate 506.
  • the first and second dies 502 and 504 may comprise one or more bond pads (not shown) or any other structure to interconnect to the embedded substrate 506 that may comprise one or more bond fingers (not shown) or the like on an lower side 532.
  • Example of the embedded unit 510 may refer to the embodiment as shown in FIG. 2B.
  • the embedded unit 510 may be stacked on a third die 512 to form a package-die stack.
  • the embedded unit 510 may be disposed on a spacer 518 that may be positioned on the third die 512.
  • the spacer 518 may be unnecessary.
  • the embedded unit 510 may be stacked onto the third die 512 with the lower side 532 of the embedded substrate 506 facing the third die 512.
  • the lower side 532 may be covered with molding compound 508 or 528.
  • the molding compound 508 may contact the spacer 518.
  • a second substrate 516 may be coupled to the third die 512 and a fourth die 514 that are stacked on the second substrate 516.
  • Example of each of the spacer 518, the third and fourth dies 512 and 514, and the second substrate 516 may refer to the embodiment as shown in FIG. 2C.
  • a bump die 522 may be stacked on the embedded unit 510.
  • the bump die 522 may be attached to the top or upper surface 534 of the embedded substrate 506 that may comprise one or more bump pads or other interconnects (not shown) on the upper side 534.
  • the bump die 522 may comprise one or more bumps 524 on one side, e.g., the bottom or lower surface as shown in FIG. 5 to couple the bump die 522 with the embedded substrate 506.
  • interconnection between the bump die 522 and the embedded substrate 506 may refer to the embodiment as shown in FIG.4.
  • the bump die 522 may further comprise one or more bumps (not shown) on an upper side to interconnect with other dies that may be positioned over the bump die 522.
  • the embedded substrate 506 may be interconnected with the second substrate 516 via bond wires or the like. Example of the interconnection may refer to the description with regard to FIG. 2E.
  • the whole stack may be encapsulated in an encapsulant or molding compound 528.
  • molding compound 528 may comprise the same molding material as the molding compound 508; however, in some embodiments, the molding compound 528 and the molding compound 508 may be different.
  • the second substrate 516 may be configure with solder ball lands or pads (not shown) on the lower side for the attachment of one or more solder balls or other interconnects 520,
  • FIGs. 2A-2E is illustrated to comprise a sequence of processes, the method in some embodiments may perform illustrated processes in a different order.
  • the embodiments as identified above are illustrated to comprise a certain number of dies, bump dies and substrates, some embodiments may apply to different numbers. For example, in some embodiments, more than two substrates may be utilized. Some embodiments may even embed the packages 100, 400 or 500, e.g., with one or more bond fingers formed on an outer surface of an embedded package in another package, and so on. In some other embodiments, the one or more dies in the embedded packages 100, 400 or 500 may comprise a bump die.

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Abstract

A semiconductor package (100) may be formed by an embedded package (110) stacked on dies. The embedded package may comprise a first substrate (106) with one or more dies (302,304) attached to one side (132) of the first substrate (106). One or more dies (102,104) may be stacked on the opposite side (134) of the first substrate. The embedded package may be stacked on a die (202,204) mounted on a second substrate (206) with the first substrate coupled to the second substrate at the other side. The entire assembly may be encapsulated.

Description

INTEGRATED CIRCUIT PACKAGE AND ITS MANUFACTURING METHOD, MEMORY SYSTEM
BACKGROUND
[0001] One type of integrated circuit (IC) package is known as Stacked Chip Scale Package (SCSP) that may comprise a number of stacked dies supported by a substrate. The dies may be coupled to the substrate with connecting lines, known as bond fingers. To create space for the bond fingers, SCSPs typically include one or more spacers provided between dies in the package. However, one of the problems with using spacers is that the size of the package is increased.
BRIEF DESCRIPTION OF THE DRAWINGS
[0002] The invention described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.
[0003] FIG. 1 is a cross-sectional view of an integrated circuit package according to an embodiment of the present invention.
[0004] FIGs. 2A-2E are cross-sectional views illustrating an embodiment of a method that may be used to manufacture the embodiment of FIG. 1.
[0005] FIG. 3 is a schematic diagram of an embodiment of the present invention.
[0006] FIG. 4 is a cross-sectional view of an integrated circuit package according to another embodiment of the present invention. [0007] FIG. 5 is a cross-sectional view of an integrated circuit package according to yet another embodiment of the present invention.
DETAILED DESCRIPTION
[0008] In the following detailed description, references is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numbers refer to the same or similar functionality throughout the several views.
[0009] References in the specification to "one embodiment", "an embodiment", "an example embodiment", etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0010] The following description may include terms, such as upper, lower, top, bottom, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting.
[0011] FIG. 1 illustrates an embodiment of a semiconductor package 100. Referring to FIG. 1 , a second substrate 206 may be coupled to interconnects such as solder balls 326. While FIG. 1 is described with a ball grid array or solder ball, in some embodiments, other external interconnects may be utilized. For example, land grid arrays may also be utilized. In some embodiments, other numbers of dies, substrates, and arrangements may be used. As shown in FIG. 1 , a first substrate 106 may be encapsulated within an encapsulant or molding compound 108 of a first assembly 110 or an encapsulant or molding compound 308. The first substrate 106 may be coupled to the second substrate 206. Any suitable substrate may be utilized, including flex substrates such as folded flex substrates or flexible polyimide tape, laminate substrates such as bismaleimide triazine (BT) substrates, buildup substrates, or ceramic substrates.
[0012] In one embodiment, the first substrate 106 may be coupled to a set of dies. For example, referring to FIG. 1 , the first substrate 106 may be coupled to a first die 102 and a second die 104 stacked on its lower side or surface 132; the first substrate 106 may be couple to a fifth die 302 and a six die 304 stacked on its upper side or surface 134. In one embodiment, die attach adhesives (not shown), such as epoxy, may be used to secure stacked dies to one another and to a substrate. The adhesive may comprise epoxy and may be conductive or non-conductive. Some embodiments may comprise paste and/or adhesive tape, etc. In other embodiments, die attach adhesives may be not required.
[0013] In one embodiment, the first substrate 106 may comprise one or more bond fingers on the upper side 134 and the lower side 132. The first and second dies 102 and 104 may be wire bonded to the lower side 132 of the first substrate 106. The fifth and six dies 302 and 304 may be wire bonded to the upper side 134 of the first substrate 106. Referring to FIG. 1 , the second substrate 206 may be coupled to one or more dies, e.g., a third die 202 and a fourth die 204 stacked on the second substrate 206. In one embodiment, a spacer 210 may separate the assembly 110 that comprises the first substrate 106 from the assembly coupled to the second substrate 206; however, in other embodiments, the spacer 210 may be omitted. In another embodiment, the spacer 210 may allow for interconnecting, e.g., wire bonding, the upper die 202 to the second substrate 206.
[0014] Any of the variety of SCSP, including ultra-thin SCSP (UT-SCSP), may be utilized for the individual sets of substrates and stacked dies coupled thereto. Any encapsulating or molding material may be utilized for the encapsulant 108 and/or 308. The encapsulant or molding compound 108 and 308 may be the same material and, in some embodiments, they may be different materials. Examples of the package 100 may comprise flash memory, static random access memory (SDRAM), digital signal processor (DSP), application specific integrated circuit (ASIC), logic circuits, and/or any other circuits or devices.
[0015] FIGs. 2A-2E illustrate an exemplary embodiment of a method of forming the package 100. With reference to FIG. 2A, the first die 102 and the second die 104 may be mounted or attached to the upper side 132 of the first substrate 106 to form a die- substrate stack. In one embodiment, the second die 104 may be mounted to the upper side 132 of the first substrate 106 and the first die 102 may be mounted on top of the second die 104. In another embodiment, the first die 102 may be mounted on top of the second die 104. The stack of the first and second dies 102 and 104 may be further mounted to the upper side 132 of the first substrate 106 with the second die 104 on top of the first substrate 106. An adhesive, e.g., epoxy resin etc., may be used to attach the first and second dies 102 and 104 to the first substrate 106. In another embodiment, an adhesive film may be used to bond the first and second dies 102 and 104 to the first substrate 106. In some embodiments, the adhesive may be not required.
[0016] Referring to FIG. 2A, in one embodiment, the first and second dies 102 and 104 may be bonded, e.g., wire bonded, to the first substrate 106. One example of the first substrate 106 may include a printed circuit board (PCB) or a printed wiring board (PWB); however, other examples for the first substrate 106 may comprise flame retardant (FR-4), BT, and tape automated bonding (TAB) tape material, etc. In one embodiment, the first substrate 106 may be configured for one or more bond fingers or I/O terminals 126 on one surface, e.g., the upper side 132. The bond fingers 126 may connect to one or more conductive traces or wires (not shown) on either or both sides of the first substrate 106. The bond fingers 126 may be used to interconnect one or more dies (e.g. , the first and second dies 102 and 104) with the first substrate 106. For example, the first bond fingers 126 may provide locations for bond wires, e.g., bond . wires 112 and 114, to interconnect the dies 102 and 104 to the first substrate 106. In another embodiment, the first substrate 106 may comprise one or more bond fingers on both the upper and lower sides 132 and 134. For example, one or more bond fingers 136, may be provided on a lower side 134 of the first substrate 106. Although FIG. 2A illustrates the embodiment that may use bond fingers 126 and/or 136, other embodiments may use one or more bond pads, bond areas or any other structure on either or both sides of the first substrate 106 for wire bonding.
[0017] In one embodiment, the first die 102 may comprise one or more first bond pads 122 and the second die 104 may comprise one or more second bond pads 124; however, in some embodiments, the bond pads may comprise bond areas or any other structure to interconnect the first and second dies 102 and 104 to the first substrate 106. In another embodiment, each of the first and second dies 102 and 104 may comprise one or more bond pads on either or both the top and bottom surfaces 132 and 134. As shown in FIG. 2A, the first die 102 may be coupled by wire bonds 112 to the bond finger side 132 of the first substrate 106. The second die 104 may be coupled by wire bonds 114 to the bond finger side 132 of first substrate 106. For example, the wire bonds 112 may be used to interconnect a bond pad 122 on the first die 102 to a bond finger 126 on the bond finger side 132. The wire bond 114 may be used to interconnect a bond pad 124 on the second die 104 with another bond finger 126 on the upper side 132 of the first substrate 106. In one embodiment, the wire bonds, e.g., wire bonds 112 and 114, may be gold wire bonds but other metals may also be used, such as aluminum.
[0018] Referring now to FIG. 2B1 the die-substrate stack of FIG. 2A may be molded or encapsulated with an encapsulant or molding compound 108. In one embodiment, the molding compound 108 may encapsulate the first and second dies 102 and 104 and the upper side 132 of the first substrate 106. The molding compound 108 may further encapsulate the bond wires 112 and 114 and the bond fingers 126 on the upper side 132 of the first substrate 106. The bond fingers 136 on the bottom side 134 of the first substrate 106 may be exposed. Thus, an embedded unit or an embedded package 110 may be formed. In one embodiment, the molding compound 108 may comprise epoxy resin or any other molding compound. In another embodiment, the molding compound 108 may comprise one or more filler, such as a hardener.
[0019] With reference to FIG. 2C, a second stack or laminate 120 may be formed. In one embodiment, the third die 202 and the fourth die 204 may be stacked on the second substrate 206. An adhesive (not shown) or the like may be used to secure the stacked dies 202 and 204 to one another and the second substrate 206. Referring to FIG. 2C, the third and fourth dies 202 and 204 may be coupled to the second substrate 206 by wire bonds 212 and 214, respectively. For example, the wire bond 212 may be used to connect a bond pad 222 on the third die 202 with a bond finger 226 on the second substrate 206. The wire bond 214 may couple a bond pad 224 on the fourth die 204 to another bond finger 226 on the second substrate 206.
[0020] Referring to FIG. 2D, a third stack 130, e.g., a package-die stack may be formed. In one embodiment, the prepackage 110 of FIG. 2B may be stacked over the second substrate 206. For example, as shown in FIG. 2D, the prepackage 110 may be inverted and positioned over the third die 202. In one embodiment, the exposed side 134 of the first substrate 106 may become an upper side of the first substrate 106. A spacer 210 may be provided between the prepackage 110 and the third die 202. The spacer 210 may separate the prepackage 110 from the assembly 120. In one embodiment, the molding compound 108 may contact the spacer 210. One side 134 of the first substrate 106 where the bond fingers 136 of FIG. 2B locate may become an upper side of the package-die stack 130. In another embodiment, the opposite side 132 of the first substrate 106 may face the spacer 210 and/or the second substrate 206.
[0021 ] Referring now to FIG. 2E, the fifth die 302 and the sixth die 304 may be mounted or stacked on the upper side 134 of the first substrate 106. The fifth and sixth dies 302 and 304 may be mounted to the third stack 130 of FIG. 2D in a manner similar to that has mentioned with regard to the embodiment of FIG. 2A and/or FIG. 2C; however, other embodiments may apply a different manner. For example, an adhesive (not shown) or the like may be used to attach the fifth and sixth dies 302 and 304 to the third stack 130 of FIG. 2D. In other embodiments, the adhesive may be not required. In some embodiments, a spacer may not be needed between the prepackage 110 and the second stack 120. For example, the spacing function may be performed by encapsulant or molding compound 108 of FIG. 2B. In this arrangement, the encapsulant 108 may be patterned or shaped to space apart the prepackage 110 and the second stack 120. In another arrangement, a spacer between the prepackage 110 and the second package 120 may not be required. For example, the prepackage 110 may be disposed on the third die 202 with an area larger than that of the prepackage 110. In another embodiment, the prepackage 110 may be stacked on a bump die that is coupled to the second substrate. As shown in FIG. 2E, wire bonding may be performed to interconnect the fifth and sixth dies 302 and 304 and the first substrate 106. In one embodiment, the fifth die 302 may be wire bonded to the first substrate 106 by bond wires 312. The six die 304 may be wire bonded to the first substrate 106 by bond wires 314. For example, a wire bond 312 may interconnect a bond pad 322 on the fifth die 302 with a bond finger 136 on the back side 134 of the first substrate 106. A wire bond 314 may connect a bond pad 324 of the six die 304 to a bond finger 136 on the back side 134 of the first substrate 106. In another embodiment, the first substrate 106 may be coupled to the second substrate 206 by the wire bonds 332. For example, a wire bond 332 may be bonded to connect a bond finger 136 on the back side 134 of the first substrate 106 with a bond finger 226 on the second substrate 206. In one embodiment, the bond fingers 136 on the back surface 134 of the first substrate 106 may connect with one or more conductive traces (not shown) on either or both sides of the first substrate 106. The bond fingers 226 on the second substrate 206 may be connect to one or more conductive traces (not shown) of the second substrate 206.
[0023] In one embodiment, the package-die stack 140 may be molded or encapsulated, e.g., with molding compound 308 of FIG. 1 , to form the package 100. For example, over molding may be performed. Examples of the molding compound 308 of FIG. 1 may be the same as the molding compound 108 of FIG. 2B, and in some embodiments, the molding compound 308 of FIG. 1 may be different from the molding compound 108 of FIG. 2B. In another embodiment, one or more solder balls or other interconnects 326 of FIG. 1 may be attached to the second substrate 206. For example, the solder balls 326 may be soldered to one or more solder ball lands or pads (not shown) configured on the lower side 234 of the second substrate 206; however, other embodiments may mount the solder balls 326 to the second substrate 206 in a different manner. Although solder balls 326 of FIG. 1 may be used in this embodiment, some embodiment may utilize any other interconnects that may electrically connect to the second substrate 206. For example, the lower side 234 may be configured for conductive adhesive film, or any other connectional material.
[0024] FIG. 3 illustrates an embodiment of a memory system 30 that may be formed in one package, In one embodiment, a universal serial bus (USB) flash memory or any other memory may be formed in one package. For example, the memory system 30 may be formed in the package 100 with die 104 being omitted. In one embodiment, the memory system 30 may comprise a control 32 that may be implemented as the first die 102 on the first substrate 106. For example, the control 32 may comprise a memory controller, a digital signal processor (DSP), a processor, logic circuit or any other control unit or device. The memory system 30 may comprise four flash memories 34a, 34b, 34c, and 34d that may coupled to the control 102. In one embodiment, the flash memory 34a may be implemented by the third die 202, the flash memory 34b may be implemented by the fourth die 204, the flash memory 34c may be implemented by the fifth die 302, and the flash memory 34d may be implemented by the sixth die 304.
[0025] One or more interconnects 36 may couple the control 32 to the flash memories 34a-34d. The interconnects 36 may be made up of the substrate 106, 206, as well as the wire bonds in the package 100 such as 112, 212, 214, 312, 314, 332 and the solder balls 326. In one embodiment, the memory system 30 may be coupled to an external I/O 38 via the second substrate 206 and the solder ball 326. Although the embodiment of FIG. 3 is illustrated to use four flash memories 34a-34d, in some embodiments, other memory devices may be utilized, such as NOR, NAND, dynamic random access memory (DRAM). Again, in some embodiments, a different number of memory devices may be utilized. Furthermore, while FIG. 3 is illustrated to use die 102 as the control 32, in some embodiments, one or more other dies may be utilized. For example, referring to FIG. 1 , in one embodiment, dies 202 and 204 may be implemented as the control 32 and dies 102, 104, 302, and 304 may be implemented as the memory devices 34a-34d.
[0026] FIG. 4 illustrates an example embodiment of an integrated circuit package 400. In one embodiment, the package 400 may be formed in a manner similar to that has been described with regard to FIGs. 2A-2E. As shown in FIG. 4, the package 400 may comprise a first substrate 406 that may be secured in the package 400 by an encapsulant or molding compound 408 or 428. In one embodiment, a first die 402 and a second die 404 may be coupled to the first substrate 406. The assembly that comprises the first substrate 406 including the first and second dies 402 and 404 may form an embedded package 410. The first and second dies 402 and 404 may comprise one or more bond pads (not shown) or any other structure to interconnect with one or more bond fingers (not shown) etc. on a lower side 432 of the first substrate 406. Example of the prepackage 410 may refer to the embodiment as shown in FIG. 2B.
[0027] As shown in FIG. 4, the embedded unit 410 may be stacked on a die 412 to form a package-die stack. The encapsulant 408 or 428 may separate the assembly 410 from the die 412. In one embodiment, the die 412 may be implemented as a bump die. In another embodiment, a lower side of the die 412 may be configured with bumps, solder balls, conductive protrusions or other interconnects 414. In one embodiment, the bump die 412 may be attached to a second substrate 416, e.g., the upper side of the second substrate 416. In one embodiment, the embedded unit 410 may be positioned over the bump die 412, e.g., the molding compound 408 may contact the upper side of the bump die 412 and the exposed upper side 434 may be opposite to the bump die 412. The one or more bumps 414 may interconnect the bump die 412 with the second substrate 416 that may be configured with bump pads (not shown) on an upper side. Example of the one or more bumps 414 may comprise bump balls, conductive protrusions, conductive contacts and/or any other structures that may couple the bump die 412 to the second substrate 416. In some embodiments, the second substrate 416 may utilize other structure to adapt with the bumps 414.
[0028] In another embodiment, one or more dies, e.g., a third die 422 and a fourth die 424 may be attached to the embedded unit 410. For example, the third and fourth dies 422 and 424 may be mounted to an upper side 434 of the first substrate 406 that is opposite to the lower side 432. The third and fourth dies 422 and 424 via one or more bond wires may be coupled to the first substrate 406 that may comprise one or more bond fingers or other interconnect (not shown) on the upper side 434. In another embodiment, the first substrate 406 may be further coupled to the second substrate 416 by one or more bond wires. Example of the interconnection may refer to the description with regard to FIG. 2E.
[0029] In one embodiment, molding may be performed to the assembly that may comprise the second substrate 416, the bump die 412, the embedded unit 410, the third die 422, and the fourth die 424. For example, molding compound 428 may be utilized; however, other embodiment may use any other molding material. In another embodiment, one or more solder ball 418 may be attached to the ball land (not shown) on the back side of the second substrate 416.
[0030] FIG. 5 illustrates an example embodiment of a package or unit 500. In one embodiment, the package 500 may be formed in a manner similar to that has been described with regard to FIGs. 2A-2E. As shown in FIG. 5, the package 500 may comprise an embedded substrate 506 that may form an embedded unit 510. A first die 502 and a second die 504 may be secured to one another and the embedded substrate 506 that may be molded with the encapsulant or molding compound 508 or 528. The first and second dies 502 and 504 may be coupled to the embedded substrate 506. The first and second dies 502 and 504 may comprise one or more bond pads (not shown) or any other structure to interconnect to the embedded substrate 506 that may comprise one or more bond fingers (not shown) or the like on an lower side 532. Example of the embedded unit 510 may refer to the embodiment as shown in FIG. 2B.
[0031] As shown in FIG. 5, the embedded unit 510 may be stacked on a third die 512 to form a package-die stack. For example, the embedded unit 510 may be disposed on a spacer 518 that may be positioned on the third die 512. In one embodiment, the spacer 518 may be unnecessary. In another embodiment, the embedded unit 510 may be stacked onto the third die 512 with the lower side 532 of the embedded substrate 506 facing the third die 512. The lower side 532 may be covered with molding compound 508 or 528. The molding compound 508 may contact the spacer 518. A second substrate 516 may be coupled to the third die 512 and a fourth die 514 that are stacked on the second substrate 516. Example of each of the spacer 518, the third and fourth dies 512 and 514, and the second substrate 516 may refer to the embodiment as shown in FIG. 2C.
[0032] As shown in FIG. 5, a bump die 522 may be stacked on the embedded unit 510. For example, the bump die 522 may be attached to the top or upper surface 534 of the embedded substrate 506 that may comprise one or more bump pads or other interconnects (not shown) on the upper side 534. In one embodiment, the bump die 522 may comprise one or more bumps 524 on one side, e.g., the bottom or lower surface as shown in FIG. 5 to couple the bump die 522 with the embedded substrate 506. For example, interconnection between the bump die 522 and the embedded substrate 506 may refer to the embodiment as shown in FIG.4. In some embodiments, the bump die 522 may further comprise one or more bumps (not shown) on an upper side to interconnect with other dies that may be positioned over the bump die 522. In another embodiment, the embedded substrate 506 may be interconnected with the second substrate 516 via bond wires or the like. Example of the interconnection may refer to the description with regard to FIG. 2E.
[0033] In one embodiment, the whole stack may be encapsulated in an encapsulant or molding compound 528. For example, molding compound 528 may comprise the same molding material as the molding compound 508; however, in some embodiments, the molding compound 528 and the molding compound 508 may be different. In another embodiment, the second substrate 516 may be configure with solder ball lands or pads (not shown) on the lower side for the attachment of one or more solder balls or other interconnects 520,
[0034] While the method of FIGs. 2A-2E is illustrated to comprise a sequence of processes, the method in some embodiments may perform illustrated processes in a different order. Further, while the embodiments as identified above are illustrated to comprise a certain number of dies, bump dies and substrates, some embodiments may apply to different numbers. For example, in some embodiments, more than two substrates may be utilized. Some embodiments may even embed the packages 100, 400 or 500, e.g., with one or more bond fingers formed on an outer surface of an embedded package in another package, and so on. In some other embodiments, the one or more dies in the embedded packages 100, 400 or 500 may comprise a bump die.
[0035] While certain features of the invention have been described with reference to embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the embodiments, as well as other embodiments of the invention, which are apparent to persons skilled in the art to which the invention pertains are deemed to lie within the spirit and scope of the invention.

Claims

What is claimed is:
1. A method, comprising: providing a first substrate with a first die mounted to a first surface of the first substrate and a second die mounted to a second surface of the first substrate, wherein the second surface is opposite to the first surface, and forming a package that comprises the first substrate coupled to a second substrate from a second surface of the first substrate.
2. The method of claim 1 , further comprising: coupling the second die on the second surface to the first substrate by one or more bond wires.
3. The method of claim 1 , further comprising: coupling the second die to the first substrate by one or more bumps.
4. The method of claim 1 , further comprising: encapsulating the first substrate with the first die to form an embedded assembly, and stacking the embedded assembly on an upper die of a set of dies coupled to the second substrate.
5. The method of claim 4, further comprising: providing a spacer between the embedded assembly and the upper die.
6. The method of claim 4, further comprising: encapsulating the embedded assembly and the second substrate.
7. The method of claim 1 , further comprising: encapsulating the first substrate and the second substrate with a bump die coupled to the second substrate.
8. The method of claim 1 , further comprising: encapsulating a third die attached to the second substrate with the first substrate, wherein the first surface of the first substrate faces the second substrate.
9. An integrated circuit package, comprising: a first substrate that includes a first die mounted to a first side of the first substrate, and a second substrate coupled to the first substrate at a second side of the first substrate.
10. The package of claim 9, further comprising: a second die mounted on a second side of the first substrate.
11. The package of claim 9, further comprising: an encapsulant that secures the first substrate in the package.
12. The package of claim 9, further comprising: a third die coupled to the second substrate.
13. The package of claim 12, further comprising: an encapsulant provided between the first die and the third die.
14. The package of claim 12, further comprising: a spacer provided between the first die and the third die.
15. The package of claim 10, wherein the second die is coupled to the second side of the first substrate by a set of bond wires.
16. The package of claim 10, wherein the second die is coupled to the second side of the first substrate by a set of bumps.
17. The package of claim 9, further comprising: a bump die coupled to the second substrate, wherein the first substrate is separated from the bump die by molding compound.
18. A memory system, comprising: a package, a first substrate disposed in the package, a second substrate disposed in the package, the second substrate being coupled to the first substrate, a plurality of memory devices, and a control coupled to the memory devices, wherein the plurality of memory devices and the control are coupled to one of a group consisting of a first side of the first substrate, a second side of the first substrate, and the second substrate.
19. The memory system of claim 18, comprising: an encapsulant to secure the first substrate and the second substrate.
20. The memory system of claim 18, wherein the control is mounted on one side of the first substrate, and the first substrate is coupled to the second substrate through an opposite side of the first substrate.
21. The memory system of claim 18, wherein the control is a die mounted on the second substrate,
22. The memory system of claim 18, one of the memory devices is coupled to one of the first substrate and second substrate via bumps.
23. The memory system of claim 18, wherein the second substrate comprises external interconnects on the package.
24. The memory system of claim 18, comprising: a spacer to allow for wire bonds for an upper die on the second substrate.
PCT/CN2006/003477 2006-12-19 2006-12-19 Integrated circuit package and its manufacturing method, memory system WO2008074185A1 (en)

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US20050133916A1 (en) * 2003-12-17 2005-06-23 Stats Chippac, Inc Multiple chip package module having inverted package stacked over die
US20060043556A1 (en) * 2004-08-25 2006-03-02 Chao-Yuan Su Stacked packaging methods and structures
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