KR20030040169A - 반도체 장치 및 그 제조 방법 - Google Patents

반도체 장치 및 그 제조 방법 Download PDF

Info

Publication number
KR20030040169A
KR20030040169A KR1020020070718A KR20020070718A KR20030040169A KR 20030040169 A KR20030040169 A KR 20030040169A KR 1020020070718 A KR1020020070718 A KR 1020020070718A KR 20020070718 A KR20020070718 A KR 20020070718A KR 20030040169 A KR20030040169 A KR 20030040169A
Authority
KR
South Korea
Prior art keywords
film
barrier metal
wiring
insulating film
conductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020020070718A
Other languages
English (en)
Korean (ko)
Inventor
사이또우다쯔유끼
오오하시나오후미
이마이도시노리
노구찌쥰지
다마루쯔요시
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가부시키가이샤 히타치세이사쿠쇼
Publication of KR20030040169A publication Critical patent/KR20030040169A/ko
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/034—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics bottomless barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020020070718A 2001-11-15 2002-11-14 반도체 장치 및 그 제조 방법 Abandoned KR20030040169A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2001-00349875 2001-11-15
JP2001349875A JP4198906B2 (ja) 2001-11-15 2001-11-15 半導体装置および半導体装置の製造方法

Publications (1)

Publication Number Publication Date
KR20030040169A true KR20030040169A (ko) 2003-05-22

Family

ID=19162481

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020070718A Abandoned KR20030040169A (ko) 2001-11-15 2002-11-14 반도체 장치 및 그 제조 방법

Country Status (5)

Country Link
US (2) US7053487B2 (https=)
JP (1) JP4198906B2 (https=)
KR (1) KR20030040169A (https=)
CN (1) CN100470787C (https=)
TW (1) TWI300970B (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100770486B1 (ko) * 2003-08-12 2007-10-25 가부시끼가이샤 르네사스 테크놀로지 반도체 장치의 제조방법
KR101139650B1 (ko) * 2004-02-25 2012-05-14 소니 주식회사 배선 기판, 그 제조 방법, 및 반도체 장치

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049226B2 (en) 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
JP4198906B2 (ja) * 2001-11-15 2008-12-17 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法
JP2004247337A (ja) * 2003-02-10 2004-09-02 Toshiba Corp 半導体装置及びその製造方法
JP2004273523A (ja) * 2003-03-05 2004-09-30 Renesas Technology Corp 配線接続構造
US7026714B2 (en) * 2003-03-18 2006-04-11 Cunningham James A Copper interconnect systems which use conductive, metal-based cap layers
JP2004356315A (ja) * 2003-05-28 2004-12-16 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US20040245636A1 (en) * 2003-06-06 2004-12-09 International Business Machines Corporation Full removal of dual damascene metal level
WO2004114398A1 (en) * 2003-06-13 2004-12-29 Applied Materials, Inc. Integration of ald tantalum nitride for copper metallization
JP4638140B2 (ja) * 2003-07-09 2011-02-23 マグナチップセミコンダクター有限会社 半導体素子の銅配線形成方法
JP2005044910A (ja) * 2003-07-24 2005-02-17 Ebara Corp 配線形成方法及び配線形成装置
US7423343B2 (en) * 2003-08-05 2008-09-09 Semiconductor Energy Laboratory Co., Ltd. Wiring board, manufacturing method thereof, semiconductor device and manufacturing method thereof
CN100342526C (zh) * 2003-08-22 2007-10-10 全懋精密科技股份有限公司 有电性连接垫金属保护层的半导体封装基板结构及其制法
KR100555515B1 (ko) * 2003-08-27 2006-03-03 삼성전자주식회사 코발트층 캡핑막을 갖는 반도체 소자 및 그 제조방법
US20050064629A1 (en) * 2003-09-22 2005-03-24 Chen-Hua Yu Tungsten-copper interconnect and method for fabricating the same
JP4041785B2 (ja) 2003-09-26 2008-01-30 松下電器産業株式会社 半導体装置の製造方法
JP4339152B2 (ja) 2004-03-08 2009-10-07 富士通マイクロエレクトロニクス株式会社 配線構造の形成方法
JP2005347511A (ja) * 2004-06-03 2005-12-15 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7301239B2 (en) * 2004-07-26 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Wiring structure to minimize stress induced void formation
JP4417202B2 (ja) * 2004-08-19 2010-02-17 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2006165115A (ja) * 2004-12-03 2006-06-22 Toshiba Corp 半導体装置
JP4963349B2 (ja) * 2005-01-14 2012-06-27 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2006202852A (ja) 2005-01-18 2006-08-03 Toshiba Corp 半導体装置
US7332428B2 (en) * 2005-02-28 2008-02-19 Infineon Technologies Ag Metal interconnect structure and method
JP5204370B2 (ja) * 2005-03-17 2013-06-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2006278635A (ja) * 2005-03-29 2006-10-12 Fujitsu Ltd 半導体装置の製造方法及びその製造に用いられる成膜装置
JP2006324584A (ja) * 2005-05-20 2006-11-30 Sharp Corp 半導体装置およびその製造方法
US7544606B2 (en) * 2005-06-01 2009-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method to implement stress free polishing
TWI267195B (en) 2005-06-20 2006-11-21 Au Optronics Corp Switching device for a pixel electrode and methods for fabricating the same
CN100446274C (zh) * 2005-07-07 2008-12-24 友达光电股份有限公司 像素电极的开关元件及其制造方法
KR100784074B1 (ko) * 2005-07-07 2007-12-10 주식회사 하이닉스반도체 반도체 소자의 비트 라인 형성 방법
DE102005052052B4 (de) * 2005-10-31 2008-02-07 Advanced Micro Devices, Inc., Sunnyvale Ätzstoppschicht für Metallisierungsschicht mit verbesserter Haftung, Ätzselektivität und Dichtigkeit und Verfahren zur Herstellung eines dielektrischen Schichtstapels
US7655972B2 (en) * 2005-11-21 2010-02-02 International Business Machines Corporation Structure and method for MOSFET with reduced extension resistance
JP2008028058A (ja) 2006-07-20 2008-02-07 Tokyo Electron Ltd 半導体装置の製造方法、半導体装置の製造装置、半導体装置及び記憶媒体
JP5072091B2 (ja) * 2006-12-08 2012-11-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN101569003B (zh) * 2006-12-22 2011-02-16 日本电气株式会社 半导体装置及其制造方法
US7859113B2 (en) * 2007-02-27 2010-12-28 International Business Machines Corporation Structure including via having refractory metal collar at copper wire and dielectric layer liner-less interface and related method
KR100824637B1 (ko) * 2007-06-26 2008-04-25 주식회사 동부하이텍 Ｎｏｒ 플래쉬 디바이스 및 그의 제조 방법
US7960036B2 (en) 2007-07-31 2011-06-14 International Business Machines Corporation Semiconductor structure and method of manufacturing same
KR100902106B1 (ko) * 2007-10-31 2009-06-09 주식회사 하이닉스반도체 텅스텐함유막이 포함된 패턴을 구비한 반도체소자의 제조방법
DE102008016431B4 (de) * 2008-03-31 2010-06-02 Advanced Micro Devices, Inc., Sunnyvale Metalldeckschicht mit erhöhtem Elektrodenpotential für kupferbasierte Metallgebiete in Halbleiterbauelementen sowie Verfahren zu ihrer Herstellung
US20090269507A1 (en) 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
DE102008021568B3 (de) 2008-04-30 2010-02-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Reduzieren der Erosion einer Metalldeckschicht während einer Kontaktlochstrukturierung in Halbleiterbauelementen und Halbleiterbauelement mit einem schützenden Material zum Reduzieren der Erosion der Metalldeckschicht
WO2009134386A1 (en) * 2008-04-30 2009-11-05 Advanced Micro Devices, Inc. Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
US7968460B2 (en) * 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
DE102008030849B4 (de) * 2008-06-30 2013-12-19 Advanced Micro Devices, Inc. Verfahren zur Reduzierung der Leckströme in dielektrischen Materialien mit Metallgebieten und einer Metalldeckschicht in Halbleiterbauelementen
US20100084766A1 (en) 2008-10-08 2010-04-08 International Business Machines Corporation Surface repair structure and process for interconnect applications
US7867891B2 (en) * 2008-12-10 2011-01-11 Intel Corporation Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance
US8324686B2 (en) * 2009-01-16 2012-12-04 Infineon Technologies Austria Ag Semiconductor device and method for manufacturing
JP5190415B2 (ja) * 2009-06-04 2013-04-24 パナソニック株式会社 半導体装置
JP5671253B2 (ja) * 2010-05-07 2015-02-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5755471B2 (ja) * 2011-03-10 2015-07-29 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8518818B2 (en) * 2011-09-16 2013-08-27 Taiwan Semiconductor Manufacturing Co., Ltd. Reverse damascene process
KR101713920B1 (ko) * 2011-09-29 2017-03-09 인텔 코포레이션 반도체 응용을 위한 양전성 금속 포함 층
CN104934368B (zh) * 2011-11-04 2019-12-17 英特尔公司 形成自对准帽的方法和设备
KR20160141875A (ko) 2011-11-04 2016-12-09 인텔 코포레이션 자기 정렬 캡의 형성 방법 및 장치
KR20130056014A (ko) * 2011-11-21 2013-05-29 삼성전자주식회사 듀얼 다마신 배선 구조체를 포함하는 반도체 소자
CN102593098A (zh) * 2012-02-27 2012-07-18 北京大学 一种集成电路金属互连结构及其制备方法
US9299638B2 (en) 2012-12-06 2016-03-29 Globalfoundries Inc. Patterning transition metals in integrated circuits
US9318447B2 (en) * 2014-07-18 2016-04-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of forming vertical structure
US9368443B1 (en) 2015-01-20 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Memory metal scheme
US9287183B1 (en) * 2015-03-31 2016-03-15 Lam Research Corporation Using electroless deposition as a metrology tool to highlight contamination, residue, and incomplete via etch
CN106531776B (zh) * 2015-09-11 2021-06-29 联华电子股份有限公司 半导体结构
JP6329199B2 (ja) * 2016-03-30 2018-05-23 株式会社日立国際電気 半導体装置の製造方法、基板処理装置およびプログラム
CN108573949B (zh) * 2017-03-08 2022-04-05 三星电子株式会社 集成电路器件及其制造方法
KR102217242B1 (ko) 2017-03-08 2021-02-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US10510657B2 (en) 2017-09-26 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with interconnecting structure and method for manufacturing the same
KR102751263B1 (ko) * 2018-08-07 2025-01-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11114336B2 (en) * 2018-11-30 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US11227833B2 (en) 2019-09-16 2022-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method for forming the same
US11222843B2 (en) * 2019-09-16 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure and method for forming the same
US11699618B2 (en) * 2020-01-24 2023-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k dielectric damage prevention
US20210391176A1 (en) * 2020-06-16 2021-12-16 Applied Materials, Inc. Overhang reduction using pulsed bias
CN115132905B (zh) 2021-03-19 2026-04-21 京东方科技集团股份有限公司 基板、其制作方法及显示面板
US12598994B2 (en) * 2021-06-01 2026-04-07 Wolfspeed, Inc. Multilayer encapsulation for humidity robustness and related fabrication methods
JP7685373B2 (ja) * 2021-06-04 2025-05-29 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
US20230317634A1 (en) * 2022-04-05 2023-10-05 Applied Materials, Inc. Coatings with diffusion barriers for corrosion and contamination protection

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09312291A (ja) * 1996-05-21 1997-12-02 Toshiba Corp 半導体装置及びその製造方法
JPH11145138A (ja) * 1997-11-10 1999-05-28 Hitachi Ltd 半導体装置およびその製造方法
KR20010076659A (ko) * 2000-01-27 2001-08-16 박종섭 반도체 소자의 배선형성 방법
JP2001284449A (ja) * 2000-03-31 2001-10-12 Sony Corp 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100212098B1 (ko) * 1987-09-19 1999-08-02 가나이 쓰도무 반도체 집적회로 장치 및 그 제조 방법과 반도체 집적 회로 장치의 배선기판 및 그 제조 방법
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5858868A (en) * 1992-05-08 1999-01-12 Yamaha Corporation Method of manufacturing a laminated wiring structure preventing impurity diffusion therein from N+ and P+ regions in CMOS device with ohmic contact
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
JP3456391B2 (ja) * 1997-07-03 2003-10-14 セイコーエプソン株式会社 半導体装置の製造方法
US6114243A (en) * 1999-11-15 2000-09-05 Chartered Semiconductor Manufacturing Ltd Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
US6380084B1 (en) * 2000-10-02 2002-04-30 Chartered Semiconductor Manufacturing Inc. Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
JP4523194B2 (ja) * 2001-04-13 2010-08-11 富士通セミコンダクター株式会社 半導体装置とその製造方法
US6531780B1 (en) * 2001-06-27 2003-03-11 Advanced Micro Devices, Inc. Via formation in integrated circuit interconnects
JP4198906B2 (ja) * 2001-11-15 2008-12-17 株式会社ルネサステクノロジ 半導体装置および半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09312291A (ja) * 1996-05-21 1997-12-02 Toshiba Corp 半導体装置及びその製造方法
JPH11145138A (ja) * 1997-11-10 1999-05-28 Hitachi Ltd 半導体装置およびその製造方法
KR20010076659A (ko) * 2000-01-27 2001-08-16 박종섭 반도체 소자의 배선형성 방법
JP2001284449A (ja) * 2000-03-31 2001-10-12 Sony Corp 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100770486B1 (ko) * 2003-08-12 2007-10-25 가부시끼가이샤 르네사스 테크놀로지 반도체 장치의 제조방법
KR101139650B1 (ko) * 2004-02-25 2012-05-14 소니 주식회사 배선 기판, 그 제조 방법, 및 반도체 장치

Also Published As

Publication number Publication date
CN1420560A (zh) 2003-05-28
US20030089928A1 (en) 2003-05-15
US6908847B2 (en) 2005-06-21
TWI300970B (en) 2008-09-11
US20030109129A1 (en) 2003-06-12
CN100470787C (zh) 2009-03-18
TW200302549A (en) 2003-08-01
JP2003152077A (ja) 2003-05-23
US7053487B2 (en) 2006-05-30
JP4198906B2 (ja) 2008-12-17

Similar Documents

Publication Publication Date Title
KR20030040169A (ko) 반도체 장치 및 그 제조 방법
US8178437B2 (en) Barrier material and process for Cu interconnect
US7553756B2 (en) Process for producing semiconductor integrated circuit device
JP3887282B2 (ja) 金属−絶縁体−金属キャパシタ及びダマシン配線構造を有する半導体素子の製造方法
US7109127B2 (en) Manufacturing method of semiconductor device
US20080182405A1 (en) Self-aligned air-gap in interconnect structures
US7052990B2 (en) Sealed pores in low-k material damascene conductive structures
KR20080086375A (ko) 반도체 장치 및 그 제조 방법
JP4527948B2 (ja) 半導体装置およびその製造方法
EP1330842B1 (en) Low temperature hillock suppression method in integrated circuit interconnects
US7670946B2 (en) Methods to eliminate contact plug sidewall slit
CN100452387C (zh) 具有多层铜线路层的半导体器件及其制造方法
KR100783868B1 (ko) 반도체장치의 제조방법 및 반도체장치
KR100914982B1 (ko) 반도체 소자의 금속배선 및 그 형성방법
TW202324735A (zh) 使用錳及石墨烯之用於敷金屬的阻障方案
KR100341482B1 (ko) 구리 배선층의 형성방법
KR100790452B1 (ko) 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
US7679192B2 (en) Semiconductor device including cover layer
JP2000150517A (ja) 半導体集積回路装置およびその製造方法
JP2006135363A (ja) 半導体装置および半導体装置の製造方法
KR100386628B1 (ko) 반도체 소자의 금속 배선 형성방법
KR100652317B1 (ko) 반도체 소자의 금속 패드 제조 방법
JP2006179950A (ja) 半導体集積回路装置の製造方法
KR100935193B1 (ko) 반도체 소자의 금속배선 및 그의 형성방법
KR20100036008A (ko) 반도체 소자의 금속배선 형성방법

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

NORF Unpaid initial registration fee
PC1904 Unpaid initial registration fee

St.27 status event code: A-2-2-U10-U13-oth-PC1904

St.27 status event code: N-2-6-B10-B12-nap-PC1904

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000