JP2006165115A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2006165115A JP2006165115A JP2004351680A JP2004351680A JP2006165115A JP 2006165115 A JP2006165115 A JP 2006165115A JP 2004351680 A JP2004351680 A JP 2004351680A JP 2004351680 A JP2004351680 A JP 2004351680A JP 2006165115 A JP2006165115 A JP 2006165115A
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- copper
- wiring
- additive
- copper wiring
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/927—Electromigration resistant metallization
Abstract
【解決手段】本発明の例に関わる多層配線構造を有する半導体集積回路が形成される半導体装置は、銅配線14と、銅配線14の上面上に形成される絶縁層16とを備え、銅配線14は、銅配線14と絶縁層16との密着性を向上させる添加物を含み、その添加物のプロファイルは、銅配線14の上面から内部に向かうに従い、次第に濃度が減少する勾配を持ち、銅配線14の上面で最も高い濃度となる。
【選択図】図7
Description
本発明の例では、第一に、銅ダマシン配線とその上に形成される銅の拡散/酸化防止層としてのストッパ、例えば、SiN、SiCN、SiCOなどとの密着性を向上させるために、銅ダマシン配線を形成した後、この配線に、その上面から、銅に固溶し、かつ、ストッパとの密着性を向上できる添加物、例えば、Ti(チタン)、Al(アルミ)、Si(シリコン)、Co(コバルト)、B(ボロン)、P(リン)などを注入する。
以下、最良と思われる実施の形態について説明する。
図1乃至図6は、第1実施の形態に関わる半導体装置の製造方法を示している。
図9乃至図12は、第2実施の形態に関わる半導体装置の製造方法を示している。
本発明の例に関わる銅ダマシン配線によれば、銅ダマシン配線の上面及びその近傍に固溶した添加物の面内密度(濃度)が不均一であっても、EM耐性には影響を与えない。
Claims (5)
- 多層配線構造を有する半導体集積回路が形成される半導体装置において、銅配線と、前記銅配線の上面上に形成される絶縁層とを具備し、前記銅配線は、前記銅配線と前記絶縁層との密着性を向上させる添加物を含み、前記添加物のプロファイルは、前記銅配線の上面から内部に向かうに従い、次第に濃度が減少する勾配を持ち、前記銅配線の上面で最も高い濃度となることを特徴とする半導体装置。
- 多層配線構造を有する半導体集積回路が形成される半導体装置において、銅配線と、前記銅配線の側面及び下面を覆うバリアメタルと、前記銅配線と前記バリアメタルとの間に形成され、前記銅配線内に固溶する添加物を含む銅固溶材料層と、前記銅配線の上面上に形成される絶縁層とを具備し、前記添加物は、前記銅配線の上面、側面及び下面に、その内部よりも多く固溶していることを特徴とする半導体装置。
- 前記銅配線の上面における前記添加物の密度は、不均一であることを特徴とする請求項1又は2に記載の半導体装置。
- 前記絶縁層は、前記銅配線を構成する銅の拡散/酸化を防止する機能を持つ材料から構成されることを特徴とする請求項1又は2に記載の半導体装置。
- 前記添加物は、Ti、Al、Si、Co、B、及び、Pのうちのいずれか1つであることを特徴とする請求項1又は2に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004351680A JP2006165115A (ja) | 2004-12-03 | 2004-12-03 | 半導体装置 |
US11/095,567 US7422977B2 (en) | 2004-12-03 | 2005-04-01 | Copper adhesion improvement device and method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004351680A JP2006165115A (ja) | 2004-12-03 | 2004-12-03 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
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JP2006165115A true JP2006165115A (ja) | 2006-06-22 |
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004351680A Pending JP2006165115A (ja) | 2004-12-03 | 2004-12-03 | 半導体装置 |
Country Status (2)
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US (1) | US7422977B2 (ja) |
JP (1) | JP2006165115A (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007189061A (ja) * | 2006-01-13 | 2007-07-26 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
JP2009277683A (ja) * | 2008-05-12 | 2009-11-26 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
WO2009153834A1 (ja) * | 2008-06-18 | 2009-12-23 | 富士通株式会社 | 半導体装置とその製造方法 |
JP2010541247A (ja) * | 2007-09-27 | 2010-12-24 | ティーイーエル エピオン インコーポレイテッド | 半導体デバイスにおける電気漏れ特性の改善及びエレクトロマイグレーションの抑制を行う方法 |
JP2012195488A (ja) * | 2011-03-17 | 2012-10-11 | Renesas Electronics Corp | 半導体装置の製造方法、及び半導体装置 |
US9899326B2 (en) | 2014-11-19 | 2018-02-20 | Renesas Electronics Corporation | Semiconductor device with inhibited electromigration and manufacturing method thereof |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090321935A1 (en) * | 2008-06-30 | 2009-12-31 | O'brien Kevin | Methods of forming improved electromigration resistant copper films and structures formed thereby |
DE102009021488A1 (de) * | 2009-05-15 | 2010-12-16 | Globalfoundries Dresden Module One Llc & Co. Kg | Verbessertes Elektromigrationsverhalten von Kupferleitungen in Metallisierungssystemen von Halbleiterbauelementen durch Legierung von Oberflächen |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6130161A (en) * | 1997-05-30 | 2000-10-10 | International Business Machines Corporation | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity |
US6284656B1 (en) * | 1998-08-04 | 2001-09-04 | Micron Technology, Inc. | Copper metallurgy in integrated circuits |
US6066196A (en) * | 1998-09-18 | 2000-05-23 | Gelest, Inc. | Method for the chemical vapor deposition of copper-based films and copper source precursors for the same |
US6800554B2 (en) * | 2000-12-18 | 2004-10-05 | Intel Corporation | Copper alloys for interconnections having improved electromigration characteristics and methods of making same |
US6528412B1 (en) * | 2001-04-30 | 2003-03-04 | Advanced Micro Devices, Inc. | Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening |
JP4198906B2 (ja) * | 2001-11-15 | 2008-12-17 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の製造方法 |
JP4647184B2 (ja) * | 2002-12-27 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2004319834A (ja) * | 2003-04-17 | 2004-11-11 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US6967155B2 (en) * | 2003-07-11 | 2005-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adhesion of copper and etch stop layer for copper alloy |
KR100538633B1 (ko) * | 2003-11-13 | 2005-12-22 | 매그나칩 반도체 유한회사 | 반도체 소자의 금속 배선 형성 방법 |
US7176571B2 (en) * | 2004-01-08 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company | Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure |
DE102004003863B4 (de) * | 2004-01-26 | 2009-01-29 | Advanced Micro Devices, Inc., Sunnyvale | Technik zur Herstellung eingebetteter Metallleitungen mit einer erhöhten Widerstandsfähigkeit gegen durch Belastung hervorgerufenen Materialtransport |
JP5208349B2 (ja) * | 2004-09-03 | 2013-06-12 | 富士通株式会社 | 容量素子とその製造方法 |
-
2004
- 2004-12-03 JP JP2004351680A patent/JP2006165115A/ja active Pending
-
2005
- 2005-04-01 US US11/095,567 patent/US7422977B2/en active Active
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007189061A (ja) * | 2006-01-13 | 2007-07-26 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
JP2010541247A (ja) * | 2007-09-27 | 2010-12-24 | ティーイーエル エピオン インコーポレイテッド | 半導体デバイスにおける電気漏れ特性の改善及びエレクトロマイグレーションの抑制を行う方法 |
KR101528383B1 (ko) * | 2007-09-27 | 2015-06-11 | 텔 에피온 인크 | 반도체 장치에서 누전 성능을 개선시키고 전자이동을 최소화시키는 방법 |
JP2009277683A (ja) * | 2008-05-12 | 2009-11-26 | Fujitsu Microelectronics Ltd | 半導体装置及びその製造方法 |
WO2009153834A1 (ja) * | 2008-06-18 | 2009-12-23 | 富士通株式会社 | 半導体装置とその製造方法 |
JP5310721B2 (ja) * | 2008-06-18 | 2013-10-09 | 富士通株式会社 | 半導体装置とその製造方法 |
US8836122B2 (en) | 2008-06-18 | 2014-09-16 | Fujitsu Limited | Semiconductor device having copper wiring with increased migration resistance |
JP2012195488A (ja) * | 2011-03-17 | 2012-10-11 | Renesas Electronics Corp | 半導体装置の製造方法、及び半導体装置 |
US9899326B2 (en) | 2014-11-19 | 2018-02-20 | Renesas Electronics Corporation | Semiconductor device with inhibited electromigration and manufacturing method thereof |
Also Published As
Publication number | Publication date |
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US7422977B2 (en) | 2008-09-09 |
US20060121734A1 (en) | 2006-06-08 |
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