KR20010051970A - 반도체 장치의 제조방법 - Google Patents
반도체 장치의 제조방법 Download PDFInfo
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- KR20010051970A KR20010051970A KR1020000070870A KR20000070870A KR20010051970A KR 20010051970 A KR20010051970 A KR 20010051970A KR 1020000070870 A KR1020000070870 A KR 1020000070870A KR 20000070870 A KR20000070870 A KR 20000070870A KR 20010051970 A KR20010051970 A KR 20010051970A
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- KR
- South Korea
- Prior art keywords
- wafer
- adhesive layer
- chip
- dicing
- die bond
- Prior art date
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- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Die Bonding (AREA)
Abstract
Description
와이어 밴딩 시험 | 패키지 균열 시험 | 칩핑 시험 | |||
배선 결합성 | 수율(%) | 균열발생율(%) | 칩 결함/균열 | 균열의 폭 | |
실시예 1 | 좋음 | 100 | 0 | 없음 | 0 |
실시예 2 | 좋음 | 100 | 0 | 없음 | 0 |
비교예 1 | 나쁨 | 30 | 20 | 없음 | 0 |
비교예 2 | 좋음 | 100 | 0 | 존재 | 13~ 20 |
Claims (1)
- 반도체 회로가 장착된 표면 및 이면을 가지는 소정 두께의 웨이퍼를 제공하는 단계;웨이퍼 회로 표면으로부터 연장된, 웨이퍼의 두께보다 더 작은 절단 깊이의 홈들을 형성하는 단계;웨이퍼 회로 표면 위에 표면 보호 시트를 부착시키는 단계;웨이퍼 이면을 연삭하여 웨이퍼의 두께를 감소시키고, 결과 그 사이 공간으로 웨이퍼를 각각의 칩들로 분리하는 단계;웨이퍼의 연삭 이면 위에 다이싱/다이 본드 시트를 부착하고, 상기 다이싱/다이 본드 시트가 기재 및 그 위에 놓여지는 접착제층을 포함하며, 상기 접착제층이 웨이퍼의 연삭 이면과 접촉되도록 접착시키는 단계;표면 보호 시트를 웨이퍼 회로 표면으로 부터 박리하여 다이싱/다이 본드 시트의 접착제층이 이웃하는 각각의 칩사이 공간에 노출되도록 하는 단계;노출된 다이싱/다이 본드 시트의 접착제층을 절단하는 단계;절단 접착제층이 접착된 각각의 칩들을 다이싱/다이 본드 시트의 기재로부터 분리하는 단계; 및소정의 기부상에 접착제층으로 각각의 칩들을 고착시키는 단계;를 포함하는 반도체 장치의 제조방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34033499A JP4409014B2 (ja) | 1999-11-30 | 1999-11-30 | 半導体装置の製造方法 |
JP1999-340334 | 1999-11-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010051970A true KR20010051970A (ko) | 2001-06-25 |
KR100655035B1 KR100655035B1 (ko) | 2006-12-07 |
Family
ID=18335954
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020000070870A KR100655035B1 (ko) | 1999-11-30 | 2000-11-27 | 반도체 장치의 제조방법 |
Country Status (10)
Country | Link |
---|---|
US (1) | US6656819B1 (ko) |
EP (1) | EP1107299B1 (ko) |
JP (1) | JP4409014B2 (ko) |
KR (1) | KR100655035B1 (ko) |
CN (1) | CN1168132C (ko) |
DE (1) | DE60028912T2 (ko) |
HK (1) | HK1035261A1 (ko) |
MY (1) | MY125340A (ko) |
SG (1) | SG90205A1 (ko) |
TW (1) | TW487981B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101327528B1 (ko) * | 2012-06-14 | 2013-11-08 | 주식회사 케이엔제이 | 웨이퍼 칩 연마방법 |
Families Citing this family (47)
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JP4649745B2 (ja) | 2001-02-01 | 2011-03-16 | ソニー株式会社 | 発光素子の転写方法 |
JP4669162B2 (ja) * | 2001-06-28 | 2011-04-13 | 株式会社ディスコ | 半導体ウェーハの分割システム及び分割方法 |
US6686225B2 (en) * | 2001-07-27 | 2004-02-03 | Texas Instruments Incorporated | Method of separating semiconductor dies from a wafer |
JP2003045901A (ja) * | 2001-08-01 | 2003-02-14 | Sony Corp | 素子の転写方法及びこれを用いた素子の配列方法、画像表示装置の製造方法 |
JP2003077940A (ja) * | 2001-09-06 | 2003-03-14 | Sony Corp | 素子の転写方法及びこれを用いた素子の配列方法、画像表示装置の製造方法 |
JP3892703B2 (ja) | 2001-10-19 | 2007-03-14 | 富士通株式会社 | 半導体基板用治具及びこれを用いた半導体装置の製造方法 |
TWI241674B (en) | 2001-11-30 | 2005-10-11 | Disco Corp | Manufacturing method of semiconductor chip |
JP4055405B2 (ja) * | 2001-12-03 | 2008-03-05 | ソニー株式会社 | 電子部品及びその製造方法 |
US7042072B1 (en) * | 2002-08-02 | 2006-05-09 | Amkor Technology, Inc. | Semiconductor package and method of manufacturing the same which reduces warpage |
JP4307825B2 (ja) | 2002-08-28 | 2009-08-05 | リンテック株式会社 | 半導体ウエハの保護構造、半導体ウエハの保護方法、これらに用いる積層保護シートおよび半導体ウエハの加工方法 |
WO2004047057A1 (ja) * | 2002-11-19 | 2004-06-03 | Ishikawa Seisakusho,Ltd. | 画素制御素子の選択転写方法、画素制御素子の選択転写方法に使用される画素制御素子の実装装置、画素制御素子転写後の配線形成方法、及び、平面ディスプレイ基板 |
JP4599075B2 (ja) * | 2003-03-26 | 2010-12-15 | 株式会社東芝 | 半導体製造装置及び半導体装置の製造方法 |
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1999
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- 2000-11-27 US US09/723,083 patent/US6656819B1/en not_active Expired - Lifetime
- 2000-11-28 SG SG200006870A patent/SG90205A1/en unknown
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KR101327528B1 (ko) * | 2012-06-14 | 2013-11-08 | 주식회사 케이엔제이 | 웨이퍼 칩 연마방법 |
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US6656819B1 (en) | 2003-12-02 |
TW487981B (en) | 2002-05-21 |
KR100655035B1 (ko) | 2006-12-07 |
CN1168132C (zh) | 2004-09-22 |
EP1107299B1 (en) | 2006-06-21 |
JP4409014B2 (ja) | 2010-02-03 |
DE60028912T2 (de) | 2007-02-15 |
SG90205A1 (en) | 2002-07-23 |
EP1107299A2 (en) | 2001-06-13 |
HK1035261A1 (en) | 2001-11-16 |
DE60028912D1 (de) | 2006-08-03 |
CN1298204A (zh) | 2001-06-06 |
JP2001156027A (ja) | 2001-06-08 |
EP1107299A3 (en) | 2004-06-16 |
MY125340A (en) | 2006-07-31 |
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