KR100929620B1 - 반도체장치와 전자장치 - Google Patents

반도체장치와 전자장치 Download PDF

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Publication number
KR100929620B1
KR100929620B1 KR1020020063624A KR20020063624A KR100929620B1 KR 100929620 B1 KR100929620 B1 KR 100929620B1 KR 1020020063624 A KR1020020063624 A KR 1020020063624A KR 20020063624 A KR20020063624 A KR 20020063624A KR 100929620 B1 KR100929620 B1 KR 100929620B1
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South Korea
Prior art keywords
wiring
electrode
package substrate
semiconductor chip
circuit
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Expired - Fee Related
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KR1020020063624A
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English (en)
Korean (ko)
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KR20030032878A (ko
Inventor
모토오 스와
유우이치 마브치
아츠시 나카무라
히데시 후쿠모토
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가부시키가이샤 히타치세이사쿠쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Semiconductor Integrated Circuits (AREA)
KR1020020063624A 2001-10-18 2002-10-17 반도체장치와 전자장치 Expired - Fee Related KR100929620B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2001-00320554 2001-10-18
JP2001320554A JP4387076B2 (ja) 2001-10-18 2001-10-18 半導体装置

Publications (2)

Publication Number Publication Date
KR20030032878A KR20030032878A (ko) 2003-04-26
KR100929620B1 true KR100929620B1 (ko) 2009-12-03

Family

ID=19137927

Family Applications (1)

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KR1020020063624A Expired - Fee Related KR100929620B1 (ko) 2001-10-18 2002-10-17 반도체장치와 전자장치

Country Status (4)

Country Link
US (2) US6803659B2 (enExample)
JP (1) JP4387076B2 (enExample)
KR (1) KR100929620B1 (enExample)
TW (1) TW586211B (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101232645B1 (ko) * 2010-12-21 2013-02-13 한국과학기술원 전원 핀을 포함하는 3차원 집적 회로 및 3차원 집적 회로의 전원 핀 배치 방법
CN115244681A (zh) * 2020-03-30 2022-10-25 华为技术有限公司 一种裸芯片、封装结构、电子设备及制备方法

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TW571375B (en) * 2002-11-13 2004-01-11 Advanced Semiconductor Eng Semiconductor package structure with ground and method for manufacturing thereof
TW571410B (en) * 2002-12-24 2004-01-11 Via Tech Inc BGA package with the same power ballout assignment for wire bonding packaging and flip chip packaging
TWI229401B (en) * 2003-02-19 2005-03-11 Via Tech Inc A wafer lever test and bump process and a chip structure with test pad
JP4708716B2 (ja) * 2003-02-27 2011-06-22 ルネサスエレクトロニクス株式会社 半導体集積回路装置、半導体集積回路装置の設計方法
US7183786B2 (en) * 2003-03-04 2007-02-27 Avago Technologies General Ip (Singapore) Pte. Ltd. Modifying a semiconductor device to provide electrical parameter monitoring
US6992387B2 (en) * 2003-06-23 2006-01-31 Intel Corporation Capacitor-related systems for addressing package/motherboard resonance
US7279796B2 (en) * 2003-08-08 2007-10-09 Intel Corporation Microelectronic die having a thermoelectric module
JP4195883B2 (ja) * 2004-02-04 2008-12-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層モジュール
JP3999759B2 (ja) * 2004-04-02 2007-10-31 富士通株式会社 基板及び電子機器
JP4647243B2 (ja) * 2004-05-24 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
JP4552524B2 (ja) * 2004-06-10 2010-09-29 パナソニック株式会社 複合型電子部品
TWI237380B (en) * 2004-11-19 2005-08-01 Advanced Semiconductor Eng Build-up via for suppressing simultaneous switching noise
JP4640950B2 (ja) * 2005-05-16 2011-03-02 ルネサスエレクトロニクス株式会社 半導体装置
US7250673B2 (en) * 2005-06-06 2007-07-31 Triquint Semiconductor, Inc. Signal isolation in a package substrate
US7745944B2 (en) 2005-08-31 2010-06-29 Micron Technology, Inc. Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts
US7701052B2 (en) * 2005-10-21 2010-04-20 E. I. Du Pont De Nemours And Company Power core devices
US8063480B2 (en) * 2006-02-28 2011-11-22 Canon Kabushiki Kaisha Printed board and semiconductor integrated circuit
US7768075B2 (en) 2006-04-06 2010-08-03 Fairchild Semiconductor Corporation Semiconductor die packages using thin dies and metal substrates
JP2009111138A (ja) * 2007-10-30 2009-05-21 Mitsubishi Electric Corp 半導体集積回路パッケージ及び回路基板
JP2009231891A (ja) 2008-03-19 2009-10-08 Nec Electronics Corp 半導体装置
US8717093B2 (en) * 2010-01-08 2014-05-06 Mindspeed Technologies, Inc. System on chip power management through package configuration
JP2011187662A (ja) * 2010-03-08 2011-09-22 Renesas Electronics Corp 半導体パッケージ、基板、電子部品、及び半導体パッケージの実装方法
JP5579879B2 (ja) * 2010-03-18 2014-08-27 コンバーサント・インテレクチュアル・プロパティ・マネジメント・インコーポレイテッド オフセットダイスタッキングを用いたマルチチップパッケージ
CN104584701B (zh) * 2012-06-22 2018-11-13 株式会社尼康 基板、拍摄单元及拍摄装置
JP6207422B2 (ja) * 2014-02-19 2017-10-04 ルネサスエレクトロニクス株式会社 電子装置
JP6631114B2 (ja) * 2015-09-17 2020-01-15 富士電機株式会社 半導体装置及び半導体装置の計測方法
KR20180134464A (ko) * 2017-06-08 2018-12-19 에스케이하이닉스 주식회사 반도체 장치 및 시스템
JP7226899B2 (ja) * 2018-04-27 2023-02-21 ラピスセミコンダクタ株式会社 電子機器及び配線基板
JP7110073B2 (ja) 2018-11-26 2022-08-01 株式会社東芝 集積回路及びそれを備えた電子回路
TWI723343B (zh) * 2019-02-19 2021-04-01 頎邦科技股份有限公司 具立體電感之半導體結構及其製造方法

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH09148478A (ja) * 1995-11-21 1997-06-06 Hitachi Ltd 半導体集積回路装置
JPH09223758A (ja) * 1996-02-19 1997-08-26 Hitachi Ltd 半導体装置
JPH1056105A (ja) * 1996-05-30 1998-02-24 Lsi Logic Corp 半導体デバイスアセンブリ
JP2001144205A (ja) * 1999-11-10 2001-05-25 Canon Inc 多端子素子及びプリント配線板

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JP2716005B2 (ja) 1995-07-04 1998-02-18 日本電気株式会社 ワイヤボンド型半導体装置
JPH1134886A (ja) 1997-07-16 1999-02-09 Toyoda Mach Works Ltd 操舵装置
US6396136B2 (en) * 1998-12-31 2002-05-28 Texas Instruments Incorporated Ball grid package with multiple power/ground planes
JP2001035960A (ja) * 1999-07-21 2001-02-09 Mitsubishi Electric Corp 半導体装置および製造方法

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH09148478A (ja) * 1995-11-21 1997-06-06 Hitachi Ltd 半導体集積回路装置
JPH09223758A (ja) * 1996-02-19 1997-08-26 Hitachi Ltd 半導体装置
JPH1056105A (ja) * 1996-05-30 1998-02-24 Lsi Logic Corp 半導体デバイスアセンブリ
JP2001144205A (ja) * 1999-11-10 2001-05-25 Canon Inc 多端子素子及びプリント配線板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101232645B1 (ko) * 2010-12-21 2013-02-13 한국과학기술원 전원 핀을 포함하는 3차원 집적 회로 및 3차원 집적 회로의 전원 핀 배치 방법
CN115244681A (zh) * 2020-03-30 2022-10-25 华为技术有限公司 一种裸芯片、封装结构、电子设备及制备方法

Also Published As

Publication number Publication date
US6803659B2 (en) 2004-10-12
JP2003124383A (ja) 2003-04-25
KR20030032878A (ko) 2003-04-26
TW586211B (en) 2004-05-01
US7095117B2 (en) 2006-08-22
US20030080353A1 (en) 2003-05-01
JP4387076B2 (ja) 2009-12-16
US20050029648A1 (en) 2005-02-10

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