KR0143876B1 - 반도체기억 장치 및 그 결함구제방법 - Google Patents

반도체기억 장치 및 그 결함구제방법 Download PDF

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Publication number
KR0143876B1
KR0143876B1 KR1019940027362A KR19940027362A KR0143876B1 KR 0143876 B1 KR0143876 B1 KR 0143876B1 KR 1019940027362 A KR1019940027362 A KR 1019940027362A KR 19940027362 A KR19940027362 A KR 19940027362A KR 0143876 B1 KR0143876 B1 KR 0143876B1
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KR
South Korea
Prior art keywords
region
diagram showing
circuit
present
circuit diagram
Prior art date
Application number
KR1019940027362A
Other languages
English (en)
Inventor
가즈히꼬 가지가야
가즈유끼 미야자와
마나부 쯔노자끼
가즈요시 오시마
다까시 야마자끼
유지 사까이
지로 사와다
야스노리 야마구찌
데쯔로 마쯔모또
신지 우도
히로시 요시오까
히로까즈 사이또
미쯔히로 다까노
마꼬또 모리노
신이찌 미야따께
에이지 미야모또
야스히로 가사마
아끼라 엔도
료이찌 호리
쥰 에또
마사시 호리구찌
신이찌 이께나가
아쯔시 구마따
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
오노 미노루
히다찌초엘에스아이 엔지니어링 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63277132A external-priority patent/JP2707516B2/ja
Priority claimed from JP63279239A external-priority patent/JPH03102695A/ja
Priority claimed from JP1014423A external-priority patent/JPH02195596A/ja
Priority claimed from JP1065840A external-priority patent/JP2762292B2/ja
Application filed by 미다 가쓰시게, 가부시끼가이샤 히다찌세이사꾸쇼, 오노 미노루, 히다찌초엘에스아이 엔지니어링 가부시끼가이샤 filed Critical 미다 가쓰시게
Application granted granted Critical
Publication of KR0143876B1 publication Critical patent/KR0143876B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
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    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
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Abstract

반도체기억장치와 그 결합구제방법에 관한 것으로써, 대기억용량화를 도모하기 위해, 장방향의 영역의 짧은 변을 횡단하는 중앙선을 따라서 연장하는 제1의 영역, 장방형영역의 긴변을 횡단하는 중앙선을 따라서 제1의 영역과 교차하도록 연장하는 제2의 영역, 장방형영역내에 있어서, 제1의 영역과 제2의 영역에 의해서 4개로 분할된 제3, 제4, 제5 및 제6의 영역, 제3, 제4, 제5 및 제6의 각 영역에 형성된 메모리어레이, 제1의 영역과 상기 제2의 영역에 각 영역의 메모리어레이에 관련해서 형성된 주변회로 및 제1의 영역을 따라서 지그재그형상으로 상기 제1의 영역에 형성되며, 또한 반도체기판과 외부를 전기적으로 접속하는 여러개의 본딩패드를 구비한다.
이러한 반도체기업장치를 이용하는 것에 의해 대기억용량화를 도모한 DRAM의 고속화가 도모된다.

Description

반도체기억장치 및 그 결함구제방법
제 1도는 본 발명이 적용된 다이나믹형 RAM의 1실시예의 기본적인 레이아우트도.
제 2도는 본 발명에 관한 다이나믹형 RAM의 1실시예를 도시한 전체 레이아우트도.
제 3도는 그 본딩패드의 상세한 배치를 도시한 레이아우트도.
제 4도는 그 어드레스할당의 1실시예를 도시한 블록도.
제 5도는 본 발명에 관한 다이나믹형 RAM에 있어서의 제어신호에 착안한 블록도.
제 6도는 본 발명에 관한 다이나믹형 RAM의 동작시퀀스에 관한 블록도.
제 7도는 그 전원공급선과 그것에 관련된 것 중에서 전원회로와 패드의 관계를 구체적으로 설명하기 위한 레이아우트도.
제 8도는 그 회로의 접지선과 그것에 관련된 내부 전원회로와 패드의 관계를 구체적으로 설명하기 위한 레이아우트도.
제 9도 a와 b는 본 발명에 관한 입력보호회로의 1실시예를 도시한 구체적인 레이아우트도와 그 단면도.
제 10도는 외부전원전압용 패드에 마련되는 입력보호회로의 1실시예를 도시한 구체적인 레이아우트도.
제 11도는 반도체칩의 주변부의 1실시예를 도시한 레이아우트도.
제 12도는 그 코너부의 개략적인 단면도.
제 13도는 그 가장 바깥둘레의 개략적인 단면도.
제 14도는 본 발명에 관한 다이나믹형 RAM의 다른 1실시예를 도시한 기본적인 레이아우트도.
제 15도는 상기 다이나믹형 RAM의 다른 1실시예를 도시한 기본적인 레이아우트도.
제 16도는 상기 다이나믹형 RAM의 또 다른 1실시예를 도시한 기본적인 레이아우트도.
제 17도a∼c는 메모리매트의 다른 1실시예의 기본적인 구성과 그것을 조합해서 구성되는 메모리블럭의 다른 1실시예의 레이아우트도.
제 18도a∼c는 상기 메모리매트의 다른 1실시예의 기본적인 구성과 그것을 조합해서 구성되는 메모리블럭의 다른 1실시예의 레이아우트도.
제 19도a∼c는 상기 메모리매트의 다른 1실시예의 기본적인 구성과 그것을 조합해서 구성되는 메모리블럭의 다른 다른 1실시예의 레이아우트도.
제 20도a∼c는 상기 메모리매트의 또 다른 1실시예의 기본적인 구성과 그것을 조합해서 구성되는 메모리블럭의 다른 1실시예의 레이아우트도.
제 21도a, b는 상기 서브블럭의 다른 1실시예의 기본적인 구성과 그것을 조합해서 구성되는 메모리블럭의 다른 1실시예의 레이아우트도.
제 22도는 본 발명에 관한 다이나믹형 RAM에 사용되는 리이드 프레임의 1실시예를 도시한 평면도.
제 23도a∼c는 상기 리이드프레임과 반도체칩의 접속예를 도시한 개략 측면도.
제 24도a, b는 본 발명에 관한 다이나믹형 RAM의 1실시예를 도시한 외관도와 내부투시도.
제 25도a∼c는 본 발명에 관한 다이나믹형 RAM의 1실시예를 도시한 외부단자의 핀배치도.
제 26도는 ZIP형 패키지를 사용한 경우의 1실시예를 도시한 외부단자의 핀 배치도.
제 27도는 SOJ형 패키지를 사용한 경우의 1실시예를 도시한 외부단자의 핀 배치도.
제 28도는 본 발명에 관한 다이나믹형 RAM에 있어서의 RAS계의 제어회로의 1실시예를 도시한 일부 회로도.
제 29도는 상기 제어회로의 1실시예를 도시한 다른 일부 회로도.
제 30도는 상기 제어회로의 1실시예를 도시한 다른 일부 회로도.
제 31도는 본 발명에 관한 RAM에 있어서의 X어드레스버퍼의 1실시예를 도시한 회로도.
제 32도는 상기 X어드레스신호A9와 A10에 대응한 어드레스버퍼회로의 1실시예를 도시한 회로도.
제 33도는 상기 X어드레스신호 A11에 대응한 어드레스버퍼의 1실시예를 도시한 회로도.
제 34도는 상기 X어드레스신호 A8에 대응한 어드레스버퍼의 1실시예를 도시한 회로도.
제 35도는 로우계의 프리디코더의 1실시예를 도시한 일부 회로도.
제 36도는 X계의 용장회로의 1실시예를 도시한 회로도.
제 37도는 워드선을 선택을 실행하는 디코더회로의 1실시예를 도시한 일부 회로도.
제 38도는 용장워드선을 선택을 실행하는 디코더회로의 1실시예를 도시한 일부 회로도.
제 39도는 센스앰프를 활성화시키는 타이밍 발생회로의 1실시예를 도시한 회로도.
제 40도는 메모리매트에 마련되는 제어회로의 1실시예를 도시한 일부 회로도.
제 41도는 X디코더, 워드선 드라이버, 공유제어선 드라이버의 1실시예를 도시한 회로도.
제 42도는 메모리셀어레이의 1실시예를 도시한 회로도.
제 43도는 재생어드레스 카운터회로의 1실시예를 도시한 회로도.
제 44도는 CAS계의 제어회로의 1실시예를 도시한 일부 회로도.
제 45도는 Y어드레스버퍼의 1실시예를 도시한 회로도.
제 46도는 Y계의 용장회로의 1실시예를 도시한 일부 회로도.
제 47도는 Y계의 용장회로의 1실시예를 도시한 다른 일부 회로도.
제 48도는 Y계의 용장회로의 1실시예를 도시한 일부 회로도.
제 49도는 Y계의 어드레스신호의 프리디코더회로의 1실시예를 도시한 회로도.
제 50도는 칼럼선택신호를 형성하는 Y계 디코더의 1실시예를 도시한 회로도.
제 51도는 니블카운터회로의 1실시예를 도시한 회로도.
제 52도는 Y계의 제어신호를 형성하는 제어회로의 1실시예를 도시한 일부 회로도.
제 53도는 동작모드 판정회로의 1실시예를 도시한 회로도.
제 54도는 Y계의 제어회로의 1실시예를 도시한 일부 회로도.
제 55도는 WE계의 제어회로의 1실시예를 도시한 일부 회로도.
제 56도는 WE계의 제어회로의 1실시예를 도시한 다른 일부 회로도.
제 57도는 데이터입력버퍼의 1실시예를 도시한 회로도.
제 58도는 메인앰프 제어회로의 1실시예를 도시한 회로도.
제 59도는 메인앰프의 1실시예를 도시한 회로도.
제 60도는 메인앰프의 데이터의 출력제어회로의 1실시예를 도시한 회로도.
제 61도는 메인앰프의 출력제어회로의 1실시예를 도시한 회로도.
제 62도는 데이터출력버퍼의 1실시예를 도시한 회로도.
제 63도는 테스트회로의 1실시예를 도시한 일부 회로도.
제 64도는 테스트회로의 1실시예를 도시한 다른 일부 회로도.
제 65도는 동작모드를 지정하는 제어회로의 1실시예를 도시한 회로도.
제 66도는 그 밖의 제어회로의 1실시예를 도시한 회로도.
제 67도는 기판백바이어스 전압발생회로의 1실시예를 도시한 회로도.
제 68도는 내부승압전압 발생회로의 1실시예를 도시한 회로도.
제 69도는 내부강압전압 발생회로의 1실시예를 도시한 회로도.
제 70도는 RAS계의 동작의 1예를 도시한 타이밍도.
제 71도는 RAS계의 동작의 1예를 도시한 타이밍도.
제 72도는 RAS계의 동작의 1예를 도시한 타이밍도.
제 73도는 X어드레스버퍼의 동작의 1예를 도시한 타이밍도.
제 74도는 CAS계의 동작의 1예를 도시한 타이밍도.
제 75도는 CAS계의 어드레스선택동작의 1예를 도시한 타이밍도.
제 76도는 라이트동작의 1예를 도시한 타이밍도.
제 77도는 Y어드레스버퍼의 동작의 1예를 도시한 타이밍도.
제 78도는 테스트모드의 동작의 1예를 도시한 타이밍도.
제 79도는 CAS계의 동작의 1예를 도시한 타이밍도.
제 80도는 CAS계의 동작의 1예를 도시한 타이밍도.
제 81도는 CAS계의 동작의 1예를 도시한 타이밍도.
제 82도는 본 발명에 관한 결함구제방법의 다른 1실시예를 도시한 블럭도.
제 83도는 본 발명에 관한 결함구제방법의 다른 1실시예를 도시한 블록도.
제 84도a∼c는 워드선의 테스트방법을 설명하기 위한 1실시예의 파형도와 그 회로도.
제 85도a∼d는 신호량 마진테스트방법을 설명하기 위한 1실시예를 도시한 회로도와 그 파형도.
제 86도는 기능세트모드의 다른 1실시예를 도시한 블록도.
제 87도a∼c는 재생어드레스카운터의 다른 1실시예를 도시한 파형도와 회로도.
제 88도a, b는 내부전원 모니터방법의 다른 1실시예를 도시한 블록도와 그것을 설명하는 파형도.
제 89도a, b는 다비트 테스트방법의 원리를 설명하기 위한 회로도와 그 파형도.
제 90도는 본 발명의 1실시예를 도시한 비트선 방향의 소자구조 단면도.
제 91도a∼c는 본 발명에 관한 결함구제방법을 설명하기 위한 개념도.
제 92도는 본 발명에 관한 메인앰프와 메모리셀어레이의 레이아우트의 1실시예를 도시한 블럭도.
제 93도는 본 발명에 관한 메인앰프와 메모리셀어레이의 레이아우트의 다른 1실시예를 도시한 블럭도.
제 94도는 본 발명에 관한 반도체칩의 1실시예를 도시한 기본적인 레이아우트도.
제 95도는 본 발명에 관한 메모리셀어레이의 1실시예를 도시한 패턴도.
제 96도a, b는 그 비트선 교차부를 설명하기 위한 단면도와 모식도.
제 97도∼제99도는 비트선방향의 공유 센스앰프열부와 그것에 대응한 메모리셀어레이부의 1실시예의 패턴도.
제 100도는 그 단차완충영역의 단면도.
제 101도는 워드선방향의 메모리셀어레이부와 그것에 대응한 워드드라이버의 1실시예를 도시한 패턴도.
제 102도∼제 105도는 그것에 대응한 워드드라이버의 1실시예를 도시한 패턴도.
제 106도와 제 107도는 그것에 대응한 X디코더의 1실시예를 도시한 패턴도.
제 108도는 워드선방향에 있어서의 메모리셀어레이부와 워드클리어회로의 1실시예를 도시한 패턴도.
제 109도는 n비트의 용량에 대해서 재생사이클수를 , 동시에 활성화되는 센스앰프수를 n으로 한 발명에 있어서의 1실시예를 도시한 도면.
제 110도는 n비트의 용량에 대해서 재생사이클수를 , 동시에 활성화되는 센스앰프수를 으로 한 종래방식을 도시한 도면.
제 111도는 본 발명을 이용한 1/4 n워드×4비트구조의 다이나믹형 RAM의 1실시예를 도시한 도면.
제 112도는 종래방식의 1/4 n워드×4비트구조의 다이나믹형 RAM을 도시한 도면
제 113도는 본 발명을 사용한 니블모드의 구성을 도시한 도면.
제 114도는 종래방식의 니블모드의 구성을 도시한 도면.
제 115도a는 종래방식과 본 발명의 실시예의 n워드×1비트구성의 어드레스방식을 비교한 도면.
제 115도b는 종래방식과 본 발명의 실시예의 1/4 n워드×4비트구성의 어드레스방식을 비교한 도면.
제 116도a는 본 발명의 1실시예의 16M비트의 다이나믹형 RAM패키지의 외형 및 핀배치를 도시한 도면.
제 116도b는 본 발명의 1실시예의 4M비트의 다이나믹형 RAM패키지의 외형 및 핀배치를 도시한 도면.
제 117도a는 본 발명의 1실시예에서 채용하고 있는 스택캐패시터STC를 사용한 메모리셀구조를 도시한 도면.
제 117도b는 본 발명의 1실시예에서 채용하고 있는 고속플레이트캐패시터HSPC를 사용한 메모리셀구조를 도시한 도면.
제 118도a는 본 발명을 사용한 재생방식과 칩내의 전압컨버터를 조합한 도면.
제 118도b는 칩내의 전압 VCL이 센스앰프를 통해서 비트선을 충전하는 방법을 도시한 도면.
제 119도는 전압컨버터를 사용하지 않는 종래방식의 다이나믹형 RAM을 도시한 도면.
제 120도a, b는 Ai-1어드레스를 I/O핀에서 받아들이는 재생×4구성의 다이나믹형 RAM을 도시한 도면과 타이밍도.
제 121도a는 본 발명의 다른 실시예를 도시한 도면.
제 121도b는 칼럼어드레스신호 와 비포(before) 로우어드레스신호 시에만 재생사이클로 변경하는 회로도.
제 122도는 제13도b에 도시한 재생사이클 전환어드레스신호 Axi-1, 에서 센스앰프 활성화시간을 만드는 회로도.
제 123도a는 단상구동형의 피크전류증가 방지회로를 도시한 도면.
제 123도b는 2상구동형의 피크전류증가 방지회로를 도시한 도면.
제 124도a, b는 본 발명의 다른 실시예를 도시한 도면.
제 125도는 본 발명의 1실시예를 사용한 다이나믹형 RAM의 칩레이아우트도.
제 126도a는 본실시예의 재생사이클수를 으로 한 경우를 도시한 도면.
제 126도b는 본실시예의 재생사이클수를 으로 한 경우를 도시한 도면.
제 127도는 본 발명이 적용된 다이나믹형 RAM의 전압강압회로의 1실시예를 도시한 회로도.
제 128도는 제 127도의 전압강압회로를 포함하는 다이나믹형 RAM의 1실시예를 도시한 블록도.
명세서는 등록번호,공개번호,출원번호가 같은 다른 목록을 참조하시오.

Claims (1)

  1. 청구항은 등록번호,공개번호,출원번호가 같은 다른 목록을 참조하시오.
KR1019940027362A 1988-11-01 1994-10-26 반도체기억 장치 및 그 결함구제방법 KR0143876B1 (ko)

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JP88-279239 1988-11-07
JP63279239A JPH03102695A (ja) 1988-11-07 1988-11-07 半導体装置
JP89-14423 1989-01-24
JP1014423A JPH02195596A (ja) 1989-01-24 1989-01-24 半導体集積回路装置
JP89-65840 1989-03-20
JP1065840A JP2762292B2 (ja) 1989-03-20 1989-03-20 半導体記憶装置

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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6212089B1 (en) * 1996-03-19 2001-04-03 Hitachi, Ltd. Semiconductor memory device and defect remedying method thereof
USRE40552E1 (en) 1990-04-06 2008-10-28 Mosaid Technologies, Inc. Dynamic random access memory using imperfect isolating transistors
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
GB9007790D0 (en) * 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
US5822256A (en) * 1994-09-06 1998-10-13 Intel Corporation Method and circuitry for usage of partially functional nonvolatile memory
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
JP3796319B2 (ja) * 1997-03-24 2006-07-12 株式会社日立製作所 ダイナミック型ｒａｍ
US5880987A (en) * 1997-07-14 1999-03-09 Micron Technology, Inc. Architecture and package orientation for high speed memory devices
KR19990050806A (ko) * 1997-12-17 1999-07-05 윤종용 불 휘발성 메모리 장치
US6560680B2 (en) 1998-01-21 2003-05-06 Micron Technology, Inc. System controller with Integrated low latency memory using non-cacheable memory physically distinct from main memory
US6397299B1 (en) 1998-01-21 2002-05-28 Micron Technology, Inc. Reduced latency memory configuration method using non-cacheable memory physically distinct from main memory
JP3996267B2 (ja) * 1998-05-12 2007-10-24 エルピーダメモリ株式会社 半導体記憶装置
US6115300A (en) * 1998-11-03 2000-09-05 Silicon Access Technology, Inc. Column redundancy based on column slices
KR100464947B1 (ko) * 1998-12-30 2005-05-20 주식회사 하이닉스반도체 디램의리프레시방법
JP3540190B2 (ja) * 1999-03-15 2004-07-07 日本電気株式会社 半導体記憶装置
US6456152B1 (en) 1999-05-17 2002-09-24 Hitachi, Ltd. Charge pump with improved reliability
JP3434741B2 (ja) * 1999-07-15 2003-08-11 エヌイーシーマイクロシステム株式会社 半導体記憶装置
JP2001184881A (ja) * 1999-12-28 2001-07-06 Toshiba Corp 不揮発性半導体メモリの読み出し回路
DE10055001A1 (de) * 2000-11-07 2002-05-16 Infineon Technologies Ag Speicheranordnung mit einem zentralen Anschlussfeld
US6449203B1 (en) * 2001-03-08 2002-09-10 Micron Technology, Inc. Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
US6751159B2 (en) * 2001-10-26 2004-06-15 Micron Technology, Inc. Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode
US6838331B2 (en) * 2002-04-09 2005-01-04 Micron Technology, Inc. Method and system for dynamically operating memory in a power-saving error correction mode
US6751143B2 (en) * 2002-04-11 2004-06-15 Micron Technology, Inc. Method and system for low power refresh of dynamic random access memories
JP2004040447A (ja) * 2002-07-03 2004-02-05 Toyota Industries Corp Ａｇｃ回路
US7047471B2 (en) * 2003-03-03 2006-05-16 Hewlett-Packard Development Company, L.P. Voltage margin testing of bladed servers
US7443836B2 (en) * 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
KR100569585B1 (ko) * 2003-12-05 2006-04-10 주식회사 하이닉스반도체 내부 전원 드라이버 제어 회로
JP4345725B2 (ja) * 2005-06-30 2009-10-14 セイコーエプソン株式会社 表示装置及び電子機器
US20140002582A1 (en) * 2012-06-29 2014-01-02 Monkeymedia, Inc. Portable proprioceptive peripatetic polylinear video player
US10171043B2 (en) * 2015-10-05 2019-01-01 Telefonaktiebolaget Lm Ericsson (Publ) Amplification device incorporating limiting
US10910081B2 (en) * 2018-12-17 2021-02-02 Micron Technology, Inc. Management of test resources to perform reliability testing of memory components
US11101015B2 (en) 2018-12-17 2021-08-24 Micron Technology, Inc. Multi-dimensional usage space testing of memory components

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5248441A (en) * 1975-05-28 1977-04-18 Hitachi Ltd Memory system
JPS57203290A (en) * 1981-06-09 1982-12-13 Mitsubishi Electric Corp Ic memory
JPS58137191A (ja) * 1982-02-08 1983-08-15 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ
JPH0640573B2 (ja) * 1983-12-26 1994-05-25 株式会社日立製作所 半導体集積回路装置
US4688197A (en) * 1983-12-30 1987-08-18 Texas Instruments Incorporated Control of data access to memory for improved video system
US4648032A (en) * 1985-02-13 1987-03-03 International Business Machines Corporation Dual purpose screen/memory refresh counter
JPS6150281A (ja) * 1985-07-26 1986-03-12 Hitachi Ltd メモリ
JPS6228995A (ja) * 1985-07-29 1987-02-06 Nec Corp メモリ集積回路
US4754425A (en) * 1985-10-18 1988-06-28 Gte Communication Systems Corporation Dynamic random access memory refresh circuit selectively adapted to different clock frequencies
JPS62146489A (ja) * 1985-12-20 1987-06-30 Nec Corp ダイナミツクメモリ
JPS62241198A (ja) * 1986-04-14 1987-10-21 Hitachi Ltd ダイナミツク型ｒａｍ
JP2511415B2 (ja) * 1986-06-27 1996-06-26 沖電気工業株式会社 半導体装置
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
JPS63157397A (ja) * 1986-12-22 1988-06-30 Matsushita Electronics Corp 半導体メモリ
JPH0821682B2 (ja) * 1987-04-24 1996-03-04 株式会社日立製作所 半導体装置の製造方法
KR960009249B1 (ko) * 1987-04-24 1996-07-16 미다 가쓰시게 반도체 메모리
US5196910A (en) * 1987-04-24 1993-03-23 Hitachi, Ltd. Semiconductor memory device with recessed array region
US4956811A (en) * 1987-09-16 1990-09-11 Hitachi, Ltd. Semiconductor memory
US4933907A (en) * 1987-12-03 1990-06-12 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory device and operating method therefor
JPH0793003B2 (ja) * 1988-09-01 1995-10-09 三菱電機株式会社 ダイナミックランダムアクセスメモリ装置およびその動作方法
KR100213602B1 (ko) * 1988-05-13 1999-08-02 가나이 쓰도무 다이나믹형 반도체 기억장치
KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
US5579256A (en) * 1988-11-01 1996-11-26 Hitachi, Ltd. Semiconductor memory device and defect remedying method thereof
JPH05175409A (ja) * 1991-12-24 1993-07-13 Sony Corp 樹脂封止型半導体装置
JPH0668667A (ja) * 1992-08-19 1994-03-11 Hitachi Ltd 半導体集積回路装置

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