JP6434424B2 - 3dメモリ - Google Patents
3dメモリ Download PDFInfo
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- JP6434424B2 JP6434424B2 JP2015555280A JP2015555280A JP6434424B2 JP 6434424 B2 JP6434424 B2 JP 6434424B2 JP 2015555280 A JP2015555280 A JP 2015555280A JP 2015555280 A JP2015555280 A JP 2015555280A JP 6434424 B2 JP6434424 B2 JP 6434424B2
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- 230000015654 memory Effects 0.000 title claims description 178
- 230000004888 barrier function Effects 0.000 claims description 153
- 238000000034 method Methods 0.000 claims description 91
- 239000000463 material Substances 0.000 claims description 86
- 238000003860 storage Methods 0.000 claims description 63
- 230000008569 process Effects 0.000 claims description 30
- 150000004767 nitrides Chemical class 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 20
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 22
- 239000011232 storage material Substances 0.000 description 18
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 13
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 11
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000001351 cycling effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011143 downstream manufacturing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004077 HF-HNO3 Inorganic materials 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical group CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Description
Claims (42)
- 縦型メモリであって、
メモリセルの積層体を備え、該積層体のセルが、
制御ゲート、
垂直の寸法を有する電荷蓄積構造体、及び
前記電荷蓄積構造体と前記制御ゲートとの間の誘電体およびバリア膜
を備え、前記バリア膜が、前記電荷蓄積構造体と前記制御ゲートとの間に全体的に位置し、前記電荷蓄積構造体及び前記バリア膜の各々が、個々の垂直の寸法を有し、前記電荷蓄積構造体の前記垂直の寸法が前記バリア膜の前記垂直の寸法と実質的に等しいかそれ以上であり、
前記誘電体が、前記電荷蓄積構造体及び前記バリア膜を囲み、前記バリア膜の第1の側面おける、前記バリア膜と前記電荷蓄積構造体との間の第1の誘電体と、前記バリア膜の前記第1の側面とは反対側の前記バリア膜の第2の側面における、前記バリア膜と前記制御ゲートとの間の第2の誘電体とを含む、メモリ。 - 請求項1に記載のメモリにおいて、前記バリア膜が面を有し、前記電荷蓄積構造体が、前記バリア膜の前記面に対向して前記バリア膜の前記面に実質的に平行な面を有し、前記バリア膜の前記面の各部が、前記電荷蓄積構造体の前記面から実質的に等しい距離で離隔されている、前記メモリ。
- 請求項1に記載のメモリにおいて、前記電荷蓄積構造体が、前記バリア膜に対向する実質的に平坦な側部を有し、前記制御ゲートが、前記バリア膜に対向する実質的に平坦な側部を有し、前記バリア膜が、前記電荷蓄積構造体の前記実質的に平坦な側部に対向して実質的に平行な第1の実質的に平坦な側部及び前記制御ゲートの前記実質的に平坦な側部に対向して実質的に平行な第2の実質的に平坦な側部を有する、前記メモリ。
- 請求項1に記載のメモリにおいて、前記バリア膜の前記垂直の寸法と実質的に等しいかそれ以上である前記電荷蓄積構造体の前記垂直の寸法が、前記バリア膜の前記垂直の寸法に実質的に等しい前記電荷蓄積構造体の前記垂直の寸法である、前記メモリ。
- 請求項1に記載のメモリであって、前記電荷蓄積構造体に隣接するピラーをさらに備え、誘電体が前記ピラーと前記電荷蓄積構造体の間にもある、前記メモリ。
- 請求項5に記載のメモリにおいて、前記ピラーがポリシリコンからなり、前記電荷蓄積構造体がポリシリコンからなり、前記誘電体が酸化物からなり、前記バリア膜が窒化物からなる、前記メモリ。
- 請求項1に記載のメモリにおいて、前記メモリセルの積層体がメモリセルのNANDストリングからなる、前記メモリ。
- 請求項1に記載のメモリにおいて、前記バリア膜が全体として、前記電荷蓄積構造体の側部に対応する平面と、前記電荷蓄積構造体の前記側部に対向する前記制御ゲートの側部に対応する平面との間にある、前記メモリ。
- 請求項1に記載のメモリにおいて、前記電荷蓄積構造体及び前記バリア膜が、前記制御ゲートに隣接する制御ゲート凹部に形成された、前記メモリ。
- 縦型のピラーを備えたメモリセルの縦型積層体であって、前記積層体のセルが、
前記ピラーに隣接して延伸する第1の側面を有する電荷蓄積構造体、
前記電荷蓄積構造体の前記第1の側面とは反対側の第2の側面に沿って前記電荷蓄積構造体に隣接する誘電体及びバリア膜、及び
前記電荷蓄積構造体から前記誘電体及び前記バリア膜の前記反対側に隣接する制御ゲートを備え、
前記メモリセルの前記バリア膜が前記バリア膜の垂直の寸法にわたって実質的に均一な厚さを有し、前記バリア膜が、前記電荷蓄積構造体の前記第2の側面と前記制御ゲートとの間の水平の寸法内に全体的に延伸し、
前記誘電体が前記電荷蓄積構造体及び前記バリア膜の両方よりも上及び下の両方に延伸する、積層体。 - 請求項10に記載の積層体において、前記電荷蓄積構造体が垂直の断面において略長方形である、前記積層体。
- 請求項10に記載の積層体において、前記制御ゲートが、ドーピングされたポリシリコンからなる、前記積層体。
- 請求項10に記載の積層体において、前記ピラーがポリシリコンからなり、前記電荷蓄積構造体がポリシリコンからなり、前記誘電体が酸化物からなり、前記バリア膜が窒化物からなる、前記積層体。
- 請求項10に記載の積層体は、メモリセルのNANDストリングである前記積層体。
- 請求項10に記載の積層体において、前記電荷蓄積構造体及び前記バリア膜が制御ゲート凹部に形成された、前記積層体。
- メモリセルの縦型積層体であって、前記積層体のセルが、
第1の垂直の寸法を有する電荷蓄積構造体、及び
第2の垂直の寸法を有する制御ゲートを備え、前記制御ゲートの前記第2の垂直の寸法と前記電荷蓄積構造体の前記第1の垂直の寸法とが実質的に等しく、
前記セルが、前記電荷蓄積構造体と前記制御ゲートとの間に誘電体及びバリア膜をさらに備え、前記制御ゲートの前記第2の垂直の寸法が前記バリア膜の垂直の寸法と実質的に等しく、前記バリア膜が、前記電荷蓄積構造体と前記制御ゲートとの間の水平の寸法内に全体的に位置し、
前記誘電体が前記電荷蓄積構造体及び前記バリア膜を囲む、積層体。 - 請求項16に記載の積層体において、前記バリア膜が垂直の断面において略長方形を有する、前記積層体。
- 請求項17に記載の積層体において、前記メモリセルの縦断面において、前記セルの前記バリア膜の表面積が前記セルの前記電荷蓄積構造体の表面積よりも小さい、前記積層体。
- 請求項16に記載の積層体において、前記電荷蓄積構造体がポリシリコンからなり、前記制御ゲートがポリシリコンからなり、前記バリア膜が窒化物からなる、前記積層体。
- 請求項16に記載の積層体において、前記誘電体が前記電荷蓄積構造体と前記バリア膜の間にあり、前記誘電体が前記制御ゲートと前記バリア膜の間に更にある、前記積層体。
- 請求項16に記載の積層体において、前記電荷蓄積構造体及び前記バリア膜が、前記セルを前記積層体の垂直に隣接するセルから分離する段状誘電体層間で前記制御ゲートに隣接する制御ゲート凹部に少なくとも部分的に形成された、前記積層体。
- 縦型メモリアレイであって、
複数の縦型メモリストリングを備え、該複数の縦型メモリストリングの各ストリングが、
縦型ピラー、
少なくとも2つの垂直に間隔を置いた段状誘電体層、及び
前記少なくとも2つの段状誘電体層のうちの垂直に隣接する2つの段状誘電体層間のメモリセルを備え、該メモリセルが、
垂直の寸法を有する電荷蓄積構造体、
制御ゲート、
前記電荷蓄積構造体と前記縦型ピラーの間の誘電体層、及び
前記電荷蓄積構造体と前記制御ゲートの間のバリア膜を備え、該バリア膜が垂直の寸法を有し、前記バリア膜の前記垂直の寸法と前記電荷蓄積構造体の前記垂直の寸法とが実質的に等しく、
前記制御ゲートが、垂直の寸法を有し、前記制御ゲートの前記垂直の寸法が前記電荷蓄積構造体の前記垂直の寸法よりも大きい、メモリアレイ。 - 請求項22に記載のメモリアレイにおいて、前記バリア膜が第1の面を有し、前記電荷蓄積構造体が、前記バリア膜の前記第1の面に対向して前記バリア膜の前記第1の面に実質的に平行に延伸する面を有し、前記バリア膜の前記第1の面の各部が前記電荷蓄積構造体の前記面から実質的に等しい距離で離隔された、前記メモリアレイ。
- 請求項22に記載のメモリアレイにおいて、前記電荷蓄積構造体が前記バリア膜に対向する平坦な側部を有し、前記制御ゲートが前記バリア膜に対向する平坦な側部を有し、前記バリア膜が、前記電荷蓄積構造体の前記平坦な側部に対向して実質的に平行な第1の平坦な側部及び前記制御ゲートの前記平坦な側部に対向して実質的に平行な第2の平坦な側部を有する、前記メモリアレイ。
- 請求項22に記載のメモリアレイにおいて、前記ピラーがポリシリコンからなり、前記電荷蓄積構造体がポリシリコンからなり、前記制御ゲートがポリシリコンからなり、前記バリア膜が窒化物からなる、前記メモリアレイ。
- 請求項22に記載のメモリアレイにおいて、前記メモリストリングがNANDメモリストリングである、前記メモリアレイ。
- 請求項22に記載のメモリアレイにおいて、前記電荷蓄積構造体及び前記バリア膜が、前記隣接段状誘電体層間で前記制御ゲートに隣接する制御ゲート凹部に形成された、前記メモリアレイ。
- メモリ積層体の形成方法であって、
垂直に隣接する段状誘電体層間に複数の制御ゲート及び制御ゲート凹部を形成すること、
前記制御ゲート凹部における前記複数の制御ゲート上に誘電体材料の第1層を形成すること、
前記制御ゲート凹部において前記誘電体材料の第1層上にバリア材料を形成すること、
前記バリア材料の一部分を除去して前記制御ゲートに隣接するバリア膜を形成すること、
前記バリア膜上に誘電体材料の第2層を形成することであって、前記誘電体材料の第1層及び前記誘電体材料の第2層のうちの少なくとも1つが、各バリア膜と個々の前記垂直に隣接する段状誘電体層との間に延伸し、
前記誘電体材料の第2層上に電荷蓄積構造体材料を形成すること、及び
前記電荷蓄積構造体材料の一部分を除去して、各々が前記バリア膜のそれぞれの対応する垂直の寸法に実質的に等しい垂直の寸法を有する電荷蓄積構造体を形成することを備え、前記バリア膜が、個々の前記制御ゲートと前記電荷蓄積構造体との間に延伸する水平の寸法内に位置し、前記誘電体材料の第1層及び前記誘電体材料の第2層のうちの少なくとも1つが、各電荷蓄積構造体と個々の前記垂直に隣接する段状誘電体層との間に延伸する、方法。 - 請求項28に記載の方法であって、
前記バリア材料の前記一部分を除去する前に、前記バリア材料上に犠牲材料を形成し、前記犠牲材料の一部分を除去すること、及び
前記誘電体材料の第2層を形成する前に、残存する前記犠牲材料を除去することをさらに備える前記方法。 - 請求項28に記載の方法において、前記バリア材料の一部分を除去して前記バリア膜を形成することが、前記バリア材料の前記一部分を除去して、隣接する前記制御ゲートの対応する垂直の寸法に実質的に等しい垂直の寸法を有するように前記バリア膜の各々を形成することを含む、前記方法。
- 請求項28に記載の方法において、前記複数の制御ゲートを形成することが、複数のポリシリコン制御ゲートを形成することからなる、前記方法。
- 請求項28に記載の方法において、バリア材料を形成することが、窒化物を形成することからなる、前記方法。
- 請求項28に記載の方法において、電荷蓄積構造体材料を形成することが、ポリシリコンを形成することからなる、前記方法。
- 請求項28に記載の方法において、前記メモリ積層体を形成することが、NANDメモリ積層体を形成することを含む、前記方法。
- メモリ積層体の形成方法であって、
段状誘電体層間に複数の制御ゲート及び制御ゲート凹部を形成すること、
前記制御ゲート凹部において前記複数の制御ゲート上に誘電体材料の第1層を形成すること、
前記制御ゲート凹部において前記誘電体材料の第1層上にバリア材料を形成すること、
前記バリア材料上に誘電体材料の第2層を形成すること、
前記誘電体材料の第2層上に電荷蓄積構造体材料を形成すること、
前記電荷蓄積構造体材料の一部分を除去して、各々がバリア膜のそれぞれの対応する垂直の寸法に実質的に等しい垂直の寸法を有する電荷蓄積構造体を形成すること、及び
前記バリア材料の一部分を除去して個々の前記制御ゲート及び電荷蓄積構造体の隣接する垂直の面の間に延伸する前記バリア膜を形成すること、及び
前記複数の制御ゲート凹部の露出表面上に誘電体材料の第3層を形成することを備え、
前記バリア材料の前記一部分を除去する前に、前記バリア膜上に犠牲材料を形成し、前記犠牲材料の一部を除去するここと、
前記誘電体材料の第2層を形成する前に、残っている前記犠牲材料を除去すること
を更に備える方法。 - 請求項35に記載の方法であって、
前記バリア材料の前記一部分を除去する前に、前記バリア材料上に犠牲材料を形成し、該犠牲材料の一部分を除去すること、及び
前記誘電体材料の第2層を形成する前に、残存する前記犠牲材料を除去することをさらに備える前記方法。 - 請求項35に記載の方法において、前記バリア材料の一部分を除去して前記バリア膜を形成することが、前記バリア材料の前記一部分を除去して、前記制御ゲートのそれぞれの対応する垂直の寸法に実質的に等しい垂直の寸法を有するように前記バリア膜の各々を形成することを含む、前記方法。
- 請求項35に記載の方法において、前記複数の制御ゲートを形成することが、複数のポリシリコン制御ゲートを形成することからなる、前記方法。
- 請求項35に記載の方法において、バリア材料を形成することが、窒化物を形成することからなる、前記方法。
- 請求項35に記載の方法において、電荷蓄積構造体材料を形成することが、ポリシリコンを形成することからなる、前記方法。
- 請求項35に記載の方法において、前記メモリ積層体を形成することが、NANDメモリ積層体を形成することを含む、前記方法。
- 請求項35に記載の方法において、前記バリア材料の一部分を除去することが、インサイチュ蒸気生成プロセスによって前記バリア材料の一部分を誘電体に変換することを含み、
前記方法が、前記バリア材料を覆う誘電体材料をエッチングすることをさらに備える、
前記方法。
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US20140203344A1 (en) | 2014-07-24 |
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US20150140797A1 (en) | 2015-05-21 |
US20160133752A1 (en) | 2016-05-12 |
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