JP6149277B2 - 電子部品実装方法、電子部品実装システムおよび基板 - Google Patents
電子部品実装方法、電子部品実装システムおよび基板 Download PDFInfo
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- JP6149277B2 JP6149277B2 JP2013507779A JP2013507779A JP6149277B2 JP 6149277 B2 JP6149277 B2 JP 6149277B2 JP 2013507779 A JP2013507779 A JP 2013507779A JP 2013507779 A JP2013507779 A JP 2013507779A JP 6149277 B2 JP6149277 B2 JP 6149277B2
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- H—ELECTRICITY
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- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/04—Apparatus for manufacture or treatment
- H10P72/0446—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
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- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7428—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
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- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
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- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
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- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07178—Means for aligning
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- H10W72/072—Connecting or disconnecting of bump connectors
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- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07232—Compression bonding, e.g. thermocompression bonding
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- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
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- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/29—Bond pads specially adapted therefor
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
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- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/941—Dispositions of bond pads
- H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/011—Manufacture or treatment of pads or other interconnections to be direct bonded
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/011—Manufacture or treatment of pads or other interconnections to be direct bonded
- H10W80/016—Cleaning
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/301—Bonding techniques, e.g. hybrid bonding
- H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W80/00—Direct bonding of chips, wafers or substrates
- H10W80/301—Bonding techniques, e.g. hybrid bonding
- H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/20—Configurations of stacked chips
- H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
- H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011076616 | 2011-03-30 | ||
| JP2011076616 | 2011-03-30 | ||
| JP2011159429 | 2011-07-20 | ||
| JP2011159429 | 2011-07-20 | ||
| PCT/JP2012/058567 WO2012133760A1 (ja) | 2011-03-30 | 2012-03-30 | 電子部品実装方法、電子部品実装システムおよび基板 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017050510A Division JP6383449B2 (ja) | 2011-03-30 | 2017-03-15 | 電子部品実装方法および電子部品実装システム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2012133760A1 JPWO2012133760A1 (ja) | 2014-07-28 |
| JP6149277B2 true JP6149277B2 (ja) | 2017-06-21 |
Family
ID=46931457
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013507779A Active JP6149277B2 (ja) | 2011-03-30 | 2012-03-30 | 電子部品実装方法、電子部品実装システムおよび基板 |
| JP2017050510A Active JP6383449B2 (ja) | 2011-03-30 | 2017-03-15 | 電子部品実装方法および電子部品実装システム |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017050510A Active JP6383449B2 (ja) | 2011-03-30 | 2017-03-15 | 電子部品実装方法および電子部品実装システム |
Country Status (2)
| Country | Link |
|---|---|
| JP (2) | JP6149277B2 (https=) |
| WO (1) | WO2012133760A1 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI841852B (zh) * | 2020-06-30 | 2024-05-11 | 日商芝浦機械電子裝置股份有限公司 | 安裝裝置及安裝方法 |
Families Citing this family (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013243333A (ja) * | 2012-04-24 | 2013-12-05 | Tadatomo Suga | チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体 |
| US9543197B2 (en) * | 2012-12-19 | 2017-01-10 | Intel Corporation | Package with dielectric or anisotropic conductive (ACF) buildup layer |
| JP2015005637A (ja) * | 2013-06-21 | 2015-01-08 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
| KR102158960B1 (ko) * | 2013-07-05 | 2020-09-23 | 에베 그룹 에. 탈너 게엠베하 | 접촉면의 본딩을 위한 방법 |
| WO2015046334A1 (ja) * | 2013-09-27 | 2015-04-02 | 株式会社ダイセル | 半導体素子三次元実装用充填材 |
| EP2889900B1 (en) * | 2013-12-19 | 2019-11-06 | IMEC vzw | Method for aligning micro-electronic components using an alignment liquid and electrostatic alignment as well as corresponding assembly of aligned micro-electronic components |
| JP6341554B2 (ja) * | 2013-12-19 | 2018-06-13 | 国立大学法人東京工業大学 | 半導体装置の製造方法 |
| FR3016474A1 (fr) * | 2014-01-14 | 2015-07-17 | Commissariat Energie Atomique | Procede de placement et de collage de puces sur un substrat recepteur |
| JP6367084B2 (ja) | 2014-10-30 | 2018-08-01 | 株式会社東芝 | 半導体チップの接合方法及び半導体チップの接合装置 |
| TW202325758A (zh) * | 2015-08-28 | 2023-07-01 | 日商昭和電工材料股份有限公司 | 緩衝片用組成物及緩衝片 |
| CN105470173B (zh) * | 2015-12-15 | 2018-08-14 | 上海微电子装备(集团)股份有限公司 | 一种芯片接合系统及方法 |
| JP6478939B2 (ja) * | 2016-03-31 | 2019-03-06 | 東レエンジニアリング株式会社 | 実装装置および実装方法 |
| JP2018098441A (ja) * | 2016-12-16 | 2018-06-21 | 株式会社ディスコ | ダイボンダー |
| US11605662B2 (en) | 2017-01-11 | 2023-03-14 | Sony Semiconductor Solutions Corporation | Imaging element, imaging device, electronic device, and method of manufacturing imaging element |
| JP6849468B2 (ja) * | 2017-02-13 | 2021-03-24 | ファスフォードテクノロジ株式会社 | 半導体製造装置および半導体装置の製造方法 |
| FR3063832B1 (fr) * | 2017-03-08 | 2019-03-22 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede d'auto-assemblage de composants microelectroniques |
| JP6598811B2 (ja) * | 2017-03-23 | 2019-10-30 | Towa株式会社 | 半導体パッケージ配置装置、製造装置、半導体パッケージの配置方法および電子部品の製造方法 |
| JP6640142B2 (ja) * | 2017-03-31 | 2020-02-05 | Towa株式会社 | 切断装置、半導体パッケージの貼付方法及び電子部品の製造方法 |
| US10269756B2 (en) * | 2017-04-21 | 2019-04-23 | Invensas Bonding Technologies, Inc. | Die processing |
| US11264351B2 (en) | 2017-05-19 | 2022-03-01 | Shindengen Electric Manufacturing Co., Ltd. | Method of manufacturing chip module |
| KR102400826B1 (ko) * | 2017-09-13 | 2022-05-23 | 제뉴인 솔루션스 피티이. 엘티디. | 폴리머 레진 몰드 컴파운드 기반 기판을 위한 커팅 방법 및 그 시스템 |
| US10186549B1 (en) * | 2017-09-20 | 2019-01-22 | Asm Technology Singapore Pte Ltd | Gang bonding process for assembling a matrix of light-emitting elements |
| TWI905469B (zh) * | 2017-10-30 | 2025-11-21 | 日商索尼半導體解決方案公司 | 固體攝像裝置及電子機器 |
| JP6916104B2 (ja) * | 2017-12-22 | 2021-08-11 | 東レエンジニアリング株式会社 | 実装方法および実装装置 |
| JP6990577B2 (ja) * | 2017-12-22 | 2022-01-12 | 東レエンジニアリング株式会社 | 実装方法および実装装置 |
| US10727219B2 (en) | 2018-02-15 | 2020-07-28 | Invensas Bonding Technologies, Inc. | Techniques for processing devices |
| US11749645B2 (en) | 2018-06-13 | 2023-09-05 | Adeia Semiconductor Bonding Technologies Inc. | TSV as pad |
| US11393779B2 (en) | 2018-06-13 | 2022-07-19 | Invensas Bonding Technologies, Inc. | Large metal pads over TSV |
| JP6906586B2 (ja) * | 2018-06-21 | 2021-07-21 | 株式会社東芝 | 半導体チップの接合方法及び半導体チップの接合装置 |
| JP2021535613A (ja) | 2018-09-04 | 2021-12-16 | 中芯集成電路(寧波)有限公司 | ウェハレベルパッケージ方法及びパッケージ構造 |
| CN110970322B (zh) * | 2018-09-30 | 2024-07-09 | 上海微电子装备(集团)股份有限公司 | 一种芯片贴片设备及芯片贴片方法 |
| TWI711088B (zh) * | 2019-01-31 | 2020-11-21 | 惠特科技股份有限公司 | 半導體元件貼合設備 |
| TWI734956B (zh) * | 2019-01-31 | 2021-08-01 | 惠特科技股份有限公司 | 半導體元件雷射焊接裝置及方法 |
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| TWI841852B (zh) * | 2020-06-30 | 2024-05-11 | 日商芝浦機械電子裝置股份有限公司 | 安裝裝置及安裝方法 |
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| JP2017135397A (ja) | 2017-08-03 |
| WO2012133760A1 (ja) | 2012-10-04 |
| JPWO2012133760A1 (ja) | 2014-07-28 |
| JP6383449B2 (ja) | 2018-08-29 |
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