WO2021084902A1 - チップ付き基板の製造方法、及び基板処理装置 - Google Patents

チップ付き基板の製造方法、及び基板処理装置 Download PDF

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WO2021084902A1
WO2021084902A1 PCT/JP2020/033410 JP2020033410W WO2021084902A1 WO 2021084902 A1 WO2021084902 A1 WO 2021084902A1 JP 2020033410 W JP2020033410 W JP 2020033410W WO 2021084902 A1 WO2021084902 A1 WO 2021084902A1
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substrate
chips
bonded
layer
manufacturing
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PCT/JP2020/033410
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English (en)
French (fr)
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隼斗 田之上
溝本　康隆
陽平 山下
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東京エレクトロン株式会社
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Priority to CN202080073979.9A priority Critical patent/CN114586135A/zh
Priority to US17/772,166 priority patent/US20220406603A1/en
Priority to JP2021554128A priority patent/JP7330284B2/ja
Priority to KR1020227017319A priority patent/KR20220091511A/ko
Publication of WO2021084902A1 publication Critical patent/WO2021084902A1/ja

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    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/7999—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto for disconnecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Definitions

  • This disclosure relates to a method for manufacturing a substrate with a chip and a substrate processing apparatus.
  • FIG. 20 of Patent Document 1 illustrates a chip-on-wafer manufacturing process.
  • the individualized first memory chips are bonded one by one to the base wafer on which the plurality of second memory chips are formed.
  • One aspect of the present disclosure provides a technique capable of suppressing poor bonding between a chip and a substrate.
  • the method for manufacturing a substrate with a chip is as follows. To prepare a laminated substrate including a plurality of the chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate via the plurality of chips. , To separate the first substrate and the plurality of chips bonded to the second substrate from the first substrate in order to bond them to one side including the device layer of the third substrate. Have.
  • FIG. 1 is a flowchart showing a method of manufacturing a substrate with a chip according to an embodiment.
  • FIG. 2 is a flowchart showing the details of S1 of FIG.
  • FIG. 3 is a flowchart showing the details of S6 of FIG.
  • FIG. 4A is a cross-sectional view showing a state in the middle of S1 of FIG.
  • FIG. 4B is a cross-sectional view showing a state at the time of completion of S1 of FIG.
  • FIG. 4C is a cross-sectional view showing a state at the time of completion of S2 of FIG.
  • FIG. 4D is a cross-sectional view showing a state at the time of completion of S3 of FIG.
  • FIG. 4E is a cross-sectional view showing a state in the middle of S4 of FIG.
  • FIG. 4F is a cross-sectional view showing a state at the time of completion of S4 of FIG.
  • FIG. 4G is a cross-sectional view showing a state at the time of completion of S5 of FIG.
  • FIG. 4H is a cross-sectional view showing a state at the time of completion of S61 of FIG. 3, which is included in S6 of FIG.
  • FIG. 4I is a cross-sectional view showing a state at the time of completion of S62 of FIG. 3, which is included in S6 of FIG.
  • FIG. 4J is a cross-sectional view showing a state at the time of completion of S63 of FIG. 3, which is included in S6 of FIG.
  • FIG. 4K is a cross-sectional view showing a state at the time of completion of S7 of FIG.
  • FIG. 5 is a plan view showing a substrate processing apparatus according to an embodiment.
  • the method for manufacturing a substrate with a chip includes, for example, S1 to S7 shown in FIG. S1 of FIG. 1 has, for example, S11 to S14 shown in FIG. Further, S6 shown in FIG. 1 has, for example, S61 to S63 shown in FIG.
  • the first substrate 1 has, for example, a silicon wafer 11, an absorption layer 12, and a bonding layer 13.
  • the absorption layer 12 may also serve as a bonding layer 13 as described later, and the first substrate 1 may have a silicon wafer 11 and an absorption layer 12.
  • the absorption layer 12 is arranged between the silicon wafer 11 and the chips 2A and 2B. Although details will be described later, the laser beam LB2 shown in FIG. 4H passes through the silicon wafer 11 and is absorbed by the absorption layer 12. Since the laser beam LB2 is absorbed by the absorption layer 12 and does not hit the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.
  • the absorption layer 12 is, for example, a silicon oxide layer, and is formed by a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, or the like.
  • the absorption layer 12 may be a silicon nitride layer, a silicon carbonitrider layer, or the like, as long as it can absorb the laser beam LB2 to the extent that damage to the chips 2A and 2B can be suppressed.
  • the silicon nitride layer is formed by a thermal nitriding method, a CVD method, or the like.
  • the silicon carbonitriding layer is formed by a CVD method or the like.
  • the bonding layer 13 is arranged between the absorbing layer 12 and the chips 2A and 2B, and comes into contact with the chips 2A and 2B.
  • the bonding layer 13 is, for example, an insulating layer such as a silicon oxide layer.
  • the bonding layer 13 may be made of a material different from that of the absorbing layer 12, or may be made of the same material. In the latter case, the absorption layer 12 may also serve as the bonding layer 13.
  • the bonding layer 13 includes an alignment mark 15 on the bonding surface 14 with the chips 2A and 2B.
  • the alignment mark 15 is imaged by a camera or the like and is used for position control of the chips 2A and 2B.
  • the position of the alignment mark 15 is not limited to the bonding surface 14 of the bonding layer 13, and may be, for example, the absorbing layer 12, or between the absorbing layer 12 and the bonding layer 13.
  • the chip 2A has a silicon wafer 21A and a device layer 22A.
  • the device layer 22A is formed on the surface of the silicon wafer 21A.
  • the device layer 22A includes semiconductor elements, circuits, terminals, and the like. After the device layer 22A is formed, the silicon wafer 21A is fragmented into a plurality of chips 2A.
  • the chip 2B has a silicon wafer 21B and a device layer 22B, similarly to the chip 2A.
  • the device layer 22B has a function different from that of the device layer 22A, and the chip 2A and the chip 2B have different thicknesses. After the device layer 22B is formed, the silicon wafer 21B is fragmented into a plurality of chips 2B.
  • the joint surface 14 of the first substrate 1 is surface-modified with plasma or the like. Specifically, the bond of SiO 2 on the joint surface 14 is cut to form an unbonded hand of Si, which enables hydrophilicization of the joint surface 14.
  • oxygen gas which is a processing gas
  • oxygen gas is excited to be turned into plasma and ionized in a reduced pressure atmosphere.
  • Oxygen ions are applied to the joint surface 14, and the joint surface 14 is modified.
  • the processing gas is not limited to oxygen gas, and may be, for example, nitrogen gas.
  • the bonding surface 14 of the first substrate 1 may be surface-modified. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is surface-modified.
  • the joint surface 14 of the first substrate 1 is made hydrophilic.
  • the first substrate 1 is held by a spin chuck, and pure water such as DIW (deionized water) is supplied to the joint surface 14 of the first substrate 1 that rotates together with the spin chuck.
  • An OH group is attached to the unbonded hands of Si on the joint surface 14, and the joint surface 14 is made hydrophilic.
  • the bonding surface 14 of the first substrate 1 but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be made hydrophilic. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is hydrophilized.
  • the chips 2A and 2B are temporarily joined to the joint surface 14 of the first substrate 1 one by one.
  • the chips 2A and 2B are joined to the first substrate 1 with the device layers 22A and 22B facing the first substrate 1.
  • Chips 2A and 2B and the first substrate 1 are bonded by van der Waals force (intermolecular force) and hydrogen bonds between OH groups. After that, heat treatment may be carried out in order to increase the bonding strength. The heat treatment causes a dehydration reaction. Since the solids are directly bonded to each other without using a liquid adhesive, it is possible to prevent misalignment due to deformation of the adhesive and inclination due to uneven thickness of the adhesive.
  • the chips 2A and 2B are permanently attached to the third substrate 6 described later without taking the step of temporarily joining the chips 2A and 2B to the first substrate 1. To join. Therefore, it is required at the same time to suppress the biting of air bubbles and foreign substances at the time of joining and to perform the position control with high accuracy.
  • the chips 2A and 2B When the chips 2A and 2B are joined to the third substrate 6 one by one as in Patent Document 1, the chips 2A and 2B may be deformed one by one in order to suppress the biting of air bubbles at the time of joining. ..
  • the bonding surfaces 24A and 24B of the chips 2A and 2B are deformed into a downwardly convex curved surface, gradually bonded to the third substrate 6 from the center toward the peripheral edge, and finally return to a flat surface.
  • Transforming the joint surfaces 24A and 24B of the chips 2A and 2B into a downwardly convex curved surface includes fixing the peripheral edges of the chips 2A and 2B and pushing down the centers of the chips 2A and 2B, respectively.
  • the distance between the fixed portion and the pressed portion is narrow. Therefore, it is difficult to deform the chips 2A and 2B one by one.
  • the chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, it does not matter if air bubbles are caught when the chips 2A and 2B are joined to the first substrate 1. Therefore, in S14, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat surfaces. Since the chips 2A and 2B are not deformed, the accuracy of the position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.
  • the chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, it does not matter if particles are caught when the chips 2A and 2B are joined to the first substrate 1. Therefore, the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be dirty to the extent that they do not interfere with the bonding. The required cleanliness is low.
  • the plurality of chips 2A and 2B are thinned to make the thickness uniform.
  • the alternate long and short dash line shows the state immediately before S2, and the solid line shows the state at the completion of S2.
  • the silicon wafers 21A and 21B are thinned, and the device layers 22A and 22B are not thinned. Thinning includes grinding or laser machining.
  • the bonding layer 3 is formed on the surfaces of the chips 2A and 2B.
  • the bonding layer 3 is an insulating layer such as a silicon oxide layer, and is formed by a CVD method or the like. Since the chips 2A and 2B are arranged at intervals and the lower ground of the bonding layer 3 has irregularities, the surface of the bonding layer 3 also has irregularities.
  • the surface of the bonding layer 3 is flattened. Since the bonding layer 3 is a silicon oxide layer or the like and has high hardness, polishing such as CMP (Chemical Mechanical Polishing) requires time for flattening.
  • CMP Chemical Mechanical Polishing
  • the convex portion 31 of the bonding layer 3 is irradiated with the laser beam LB1.
  • the convex portion 31 absorbs the laser beam LB1 and changes its state from the solid phase to the gas phase and scatters, or scatters in the solid phase.
  • the laser beam LB1 may also irradiate the recess 32 of the bonding layer 3. If the irradiation intensity of the concave portion 32 is lower than the irradiation intensity of the convex portion 31, the surface of the bonding layer 3 can be flattened.
  • the irradiation point of the laser beam LB1 is moved by the galvano scanner or the XY ⁇ stage.
  • the galvano scanner moves the laser beam LB1.
  • the XY ⁇ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis.
  • the XYZ ⁇ stage may be used instead of the XY ⁇ stage.
  • the surface of the bonding layer 3 is further flattened by CMP or the like. Since the convex portion 31 has been selectively removed before the CMP, the waviness remaining on the surface of the bonding layer 3 after the CMP can be reduced.
  • the chips 2A and 2B are joined to the second substrate 5.
  • the second substrate 5 comes into contact with the flattened surface of the bonding layer 3 and is bonded to the chips 2A and 2B via the bonding layer 3.
  • the second substrate 5 has, for example, a silicon wafer 51 and a bonding layer 53.
  • the bonding layer 53 is an insulating layer such as a silicon oxide layer, like the bonding layer 13 of the first substrate 1, and is formed by a CVD method or the like.
  • At least one of the bonding surface 54 of the second substrate 5 and the bonding surface 34 of the bonding layer 3 may be surface-modified and hydrophilized before bonding.
  • the second substrate 5 and the bonding layer 3 are bonded by van der Waals force (intermolecular force), hydrogen bonds between OH groups, and the like. Since the solids are directly bonded to each other without using a liquid adhesive, it is possible to prevent misalignment due to deformation of the adhesive. In addition, it is possible to prevent the occurrence of inclination due to uneven thickness of the adhesive.
  • the second substrate 5 is joined to the first substrate 1 via the bonding layer 3 with its bonding surface 54 facing downward. That is, the substrates are bonded to each other. At that time, the joint surface 54 of the second substrate 5 is deformed into a downwardly convex curved surface in order to prevent air bubbles from being caught, and is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the deformation of the second substrate 5 can be realized by fixing the peripheral edge of the second substrate 5 and pressing the center of the second substrate 5.
  • the distance between the fixed portion and the pressed portion is wider than when the chips 2A and 2B are deformed one by one, so that the deformation is easy. Deformation is easy because the substrates are bonded together.
  • the arrangement of the second substrate 5 and the first substrate 1 may be reversed, the second substrate 5 may be arranged below the first substrate 1, and the joint surface 54 of the second substrate 5 may be upward. Good.
  • the joint surface 54 of the second substrate 5 is deformed into an upwardly convex curved surface in order to prevent air bubbles from being caught, and is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the second substrate 5 is first bent and deformed, but the first substrate 1 is first bent and deformed. May be good. In this case as well, the substrates are bonded to each other. However, it is preferable to hold the first substrate 1 flat and the chips 2A and 2B flat from the viewpoint of protecting the chips 2A and 2B.
  • the chips 2A and 2B are separated from the first substrate 1 as shown in FIGS. 4H, 4I and 4J.
  • S61 of FIG. 3 which is included in S6 of FIG. 1, a plurality of modified layers M are formed by the laser beam LB2 on the dividing surface D where the first substrate 1 is to be divided in the thickness direction, as shown in FIG. 4H. ..
  • the modified layer M is formed in a dot shape, and is formed above, for example, a condensing point or a condensing point.
  • the laser beam LB2 passes through the silicon wafer 11 of the first substrate 1 and forms the modified layer M on the absorption layer 12 of the first substrate 1.
  • the absorption layer 12 is arranged between the silicon wafer 11 and the chips 2A and 2B, and absorbs the laser beam LB2. Since the laser beam LB2 hardly hits the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.
  • the laser beam LB2 has a wavelength of, for example, 8.8 ⁇ m to 11 ⁇ m so as to pass through the silicon wafer 11 and be absorbed by the absorption layer 12.
  • the light source of the laser beam LB2 is, for example, a CO 2 laser.
  • the wavelength of the CO 2 laser is about 9.3 ⁇ m.
  • the laser beam LB2 is pulse-oscillated.
  • the formation position of the modified layer M is moved by the galvano scanner or the XY ⁇ stage.
  • the galvano scanner moves the laser beam LB2.
  • the XY ⁇ stage moves the first substrate 1 in the horizontal direction (X-axis direction and Y-axis direction) and rotates it around the vertical axis.
  • the XYZ ⁇ stage may be used instead of the XY ⁇ stage.
  • a plurality of modified layers M are formed at intervals in the circumferential direction and the radial direction of the first substrate 1.
  • a crack CR connecting the modified layers M is also formed.
  • the first substrate 1 is divided starting from the modified layer M as shown in FIG. 4I.
  • the upper chuck 131 holds the first substrate 1
  • the lower chuck 132 holds the second substrate 5.
  • the arrangement of the first substrate 1 and the second substrate 5 may be upside down, and the upper chuck 131 may hold the second substrate 5 and the lower chuck 132 may hold the first substrate 1.
  • the crack CR spreads in a plane shape starting from the modified layer M, and the first substrate 1 is divided by the dividing surface D.
  • the upper chuck 131 may be rotated around the vertical axis as the upper chuck 131 is raised.
  • the first substrate 1 can be threaded on the dividing surface D.
  • the lower chuck 132 may be lowered instead of the upper chuck 131 or in addition to the upper chuck 131 being raised. Further, the lower chuck 132 may be rotated about the vertical axis.
  • the chips 2A and 2B are bonded to the single side 64 including the device layer 62 of the third substrate 6 in a state of being bonded to the second substrate 5.
  • the third substrate 6 includes a silicon wafer 61 and a device layer 62.
  • the device layer 62 is formed on the surface of the silicon wafer 61.
  • the device layer 62 includes semiconductor elements, circuits, terminals, and the like, and is electrically connected to the device layers 22A and 22B of the chips 2A and 2B.
  • At least one of the bonding surface 64 of the third substrate 6 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be surface-modified and hydrophilized before bonding.
  • the third substrate 6 and the chips 2A and 2B are joined by van der Waals force (intermolecular force) and hydrogen bonds between OH groups. Since the solids are directly bonded to each other without using a liquid adhesive, it is possible to prevent misalignment due to deformation of the adhesive. In addition, it is possible to prevent the occurrence of inclination due to uneven thickness of the adhesive.
  • the third substrate 6 is bonded to the second substrate 5 via the chips 2A and 2B with its bonding surface 64 facing downward. That is, the substrates are bonded to each other. At that time, the joint surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface in order to prevent air bubbles from being caught, and is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the deformation of the third substrate 6 can be realized by fixing the peripheral edge of the third substrate 6 and pressing the center of the third substrate 6.
  • the third substrate 6 is deformed, the distance between the fixed portion and the pressed portion is wider than when the chips 2A and 2B are deformed one by one, so that the deformation is easy. Deformation is easy because the substrates are bonded together.
  • the arrangement of the third substrate 6 and the second substrate 5 may be reversed, the third substrate 6 may be arranged below the second substrate 5, and the joint surface 64 of the third substrate 6 may be upward. Good.
  • the joint surface 64 of the third substrate 6 is deformed into an upwardly convex curved surface in order to prevent air bubbles from being caught, is gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • the substrates are bonded to each other.
  • the third substrate 6 is first bent and deformed, but the second substrate 5 is first bent and deformed. May be good. In this case as well, the substrates are bonded to each other.
  • the substrate 7 with a chip can be obtained.
  • the chipped substrate 7 includes a third substrate 6 and a plurality of chips 2A and 2B.
  • the substrate 7 with a chip further includes a second substrate 5.
  • the second substrate 5 may be separated from the chips 2A and 2B, and the substrate with a chip 7 may include the third substrate 6 and the chips 2A and 2B.
  • the first substrate is used. Temporarily join to one side of 1. Since the biting of air bubbles at this stage does not matter, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat. Since it is not necessary to forcibly deform the chips 2A and 2B, the accuracy of the position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.
  • the plurality of chips 2A and 2B bonded to the first substrate 1 are bonded to the facing surface of the second substrate 5 with the first substrate 1. Subsequently, the plurality of chips 2A and 2B bonded to the first substrate 1 and the second substrate 5 are separated from the first substrate 1. Next, the plurality of chips 2A and 2B separated from the first substrate 1 are bonded to the single side 64 including the device layer 62 of the third substrate 6 in a state of being bonded to the second substrate 5.
  • the joint surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface in order to prevent air bubbles from being caught, gradually joined from the center to the peripheral edge, and finally returns to a flat surface.
  • Deforming the third substrate 6 is easier than deforming the chips 2A and 2B one by one. This is because the boards are bonded together. Therefore, as compared with the case where the chips 2A and 2B are permanently bonded to the third substrate 6 without taking the step of temporarily bonding the chips 2A and 2B to the first substrate 1 as in Patent Document 1.
  • a substrate 7 with a chip can be obtained, which has no air bubbles and has good position accuracy.
  • the substrate processing apparatus 100 that implements S61 and S62 of FIG. 3 will be described with reference to FIG. 5 and the like.
  • the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other
  • the X-axis direction and the Y-axis direction are the horizontal direction
  • the Z-axis direction is the vertical direction.
  • the substrate processing device 100 includes a loading / unloading section 101, a transport section 110, a laser machining section 120, a dividing section 130, and a control section 140.
  • the loading / unloading section 101 has a mounting section 102 on which the cassette C is mounted.
  • the cassette C accommodates a plurality of laminated substrates 8 shown in FIG. 4G and the like at intervals in the vertical direction.
  • the laminated substrate 8 includes a plurality of chips 2A and 2B, a first substrate 1, and a second substrate 5.
  • the laminated substrate 8 is divided into a first divided body 81 and a second divided body 82 on the dividing surface D. After that, the first divided body 81 and the second divided body 82 are separately housed in the cassette C.
  • the first divided body 81 includes the silicon wafer 11, and after being carried out to the outside of the substrate processing apparatus 100, can be reused as a new first substrate 1 again.
  • the second divided body 82 includes the chips 2A and 2B, is carried out to the outside of the substrate processing apparatus 100, and then is provided to S63 in FIG. 3 and S7 in FIG.
  • the number of mounting portions 102 and the number of cassettes C are not limited to those shown in FIG.
  • the transport unit 110 is arranged next to the carry-in / out unit 101, the laser processing unit 120, and the division unit 130, and conveys the laminated substrate 8 and the like to these.
  • the transport unit 110 has a holding mechanism for holding the laminated substrate 8 and the like.
  • the holding mechanism can move in the horizontal direction (both directions in the X-axis direction and the Y-axis direction) and in the vertical direction, and can rotate about the vertical axis.
  • the laser processing unit 120 forms a plurality of modified layers M with the laser beam LB2 on the dividing surface D where the first substrate 1 is to be divided in the thickness direction.
  • the modified layer M is formed in a dot shape, for example, a condensing point or a condensing point above the condensing point.
  • the laser processing unit 120 includes, for example, a stage 121 that holds the first substrate 1 and an optical system 122 that irradiates the first substrate 1 held by the stage 121 with the laser beam LB2.
  • the stage 121 is, for example, an XY ⁇ stage or an XYZ ⁇ stage.
  • the optical system 122 includes, for example, a condenser lens.
  • the condenser lens focuses the laser beam LB2 toward the first substrate 1.
  • the optical system 122 may further include a galvano scanner.
  • the dividing unit 130 divides the first substrate 1 starting from the modified layer M.
  • the dividing portion 130 includes, for example, an upper chuck 131 and a lower chuck 132.
  • the upper chuck 131 holds the first substrate 1, and the lower chuck 132 holds the second substrate 5.
  • the arrangement of the first substrate 1 and the second substrate 5 may be upside down.
  • the crack CR spreads in a plane shape starting from the modified layer M, and the first substrate 1 is divided by the dividing surface D.
  • the laminated substrate 8 is divided into a first divided body 81 and a second divided body 82 on the dividing surface D.
  • the upper chuck 131 may rotate around the vertical axis.
  • the first substrate 1 can be threaded on the dividing surface D.
  • the control unit 140 is, for example, a computer, and includes a CPU (Central Processing Unit) 141 and a storage medium 142 such as a memory, as shown in FIG.
  • the storage medium 142 stores programs that control various processes executed by the substrate processing apparatus 100.
  • the control unit 140 controls the operation of the substrate processing device 100 by causing the CPU 141 to execute the program stored in the storage medium 142.
  • the control unit 140 includes an input interface 143 and an output interface 144.
  • the control unit 140 receives a signal from the outside through the input interface 143 and transmits the signal to the outside through the output interface 144.
  • the above program is stored in, for example, a computer-readable storage medium, and is installed from the storage medium in the storage medium 142 of the control unit 140.
  • Examples of the storage medium that can be read by a computer include a hard disk (HD), a flexible disk (FD), a compact disk (CD), a magnet optical desk (MO), and a memory card.
  • the program may be downloaded from the server via the Internet and installed on the storage medium 142 of the control unit 140.

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Abstract

複数の前記チップと、複数の前記チップが一時的に接合された第１基板と、複数の前記チップを介して前記第１基板に接合された第２基板とを含む積層基板を準備することと、前記第１基板及び前記第２基板に接合された複数の前記チップを、第３基板のデバイス層を含む片面に接合すべく、前記第１基板から分離することと、を有する、チップ付き基板の製造方法。

Description

チップ付き基板の製造方法、及び基板処理装置
　本開示は、チップ付き基板の製造方法、及び基板処理装置に関する。
　特許文献１の図２０には、チップオンウェハの製造工程が図示されている。この製造工程では、複数の第２メモリチップが形成されたベースウェハに対し、個片化された第１メモリチップを１つずつ接合する。
日本国特開２０１５－４６５６９号公報
　本開示の一態様は、チップと基板との接合不良を抑制できる、技術を提供する。
　本開示の一態様に係るチップ付き基板の製造方法は、
　複数の前記チップと、複数の前記チップが一時的に接合された第１基板と、複数の前記チップを介して前記第１基板に接合された第２基板とを含む積層基板を準備することと、
　前記第１基板及び前記第２基板に接合された複数の前記チップを、第３基板のデバイス層を含む片面に接合すべく、前記第１基板から分離することと、
を有する。
　本開示の一態様によれば、チップと基板との接合不良を抑制できる。
図１は、一実施形態に係るチップ付き基板の製造方法を示すフローチャートである。 図２は、図１のＳ１の詳細を示すフローチャートである。 図３は、図１のＳ６の詳細を示すフローチャートである。 図４Ａは、図１のＳ１の途中の状態を示す断面図である。 図４Ｂは、図１のＳ１の完了時の状態を示す断面図である。 図４Ｃは、図１のＳ２の完了時の状態を示す断面図である。 図４Ｄは、図１のＳ３の完了時の状態を示す断面図である。 図４Ｅは、図１のＳ４の途中の状態を示す断面図である。 図４Ｆは、図１のＳ４の完了時の状態を示す断面図である。 図４Ｇは、図１のＳ５の完了時の状態を示す断面図である。 図４Ｈは、図１のＳ６に含まれる、図３のＳ６１の完了時の状態を示す断面図である。 図４Ｉは、図１のＳ６に含まれる、図３のＳ６２の完了時の状態を示す断面図である。 図４Ｊは、図１のＳ６に含まれる、図３のＳ６３の完了時の状態を示す断面図である。 図４Ｋは、図１のＳ７の完了時の状態を示す断面図である。 図５は、一実施形態に係る基板処理装置を示す平面図である。
　以下、本開示の実施形態について図面を参照して説明する。なお、各図面において同一の又は対応する構成には同一の符号を付し、説明を省略することがある。
　チップ付き基板の製造方法は、例えば図１に示すＳ１～Ｓ７を有する。図１のＳ１は、例えば図２に示すＳ１１～Ｓ１４を有する。また、図１に示すＳ６は、例えば図３に示すＳ６１～Ｓ６３を有する。
　先ず、図１のＳ１では、図４Ａ及び図４Ｂに示すように、第１基板１とチップ２Ａ、２Ｂとを接合する。図１のＳ１に含まれる、図２のＳ１１では、第１基板１とチップ２Ａ、２Ｂを準備する。
　第１基板１は、例えば、シリコンウェハ１１と、吸収層１２と、接合層１３とを有する。なお、吸収層１２は後述するように接合層１３を兼ねてもよく、第１基板１はシリコンウェハ１１と吸収層１２とを有すればよい。
　吸収層１２は、シリコンウェハ１１とチップ２Ａ、２Ｂとの間に配置される。詳しくは後述するが図４Ｈに示すレーザー光線ＬＢ２は、シリコンウェハ１１を通り、吸収層１２で吸収される。レーザー光線ＬＢ２が、吸収層１２で吸収され、チップ２Ａ、２Ｂに当らないので、チップ２Ａ、２Ｂの破損を抑制できる。吸収層１２は、例えばシリコン酸化層であり、熱酸化法、又はＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｏｎ）法などで形成される。
　なお、吸収層１２は、チップ２Ａ、２Ｂの破損を抑制できる程度に、レーザー光線ＬＢ２を吸収できればよく、シリコン窒化層、又はシリコン炭窒化層などであってもよい。シリコン窒化層は、熱窒化法、又はＣＶＤ法などで形成される。シリコン炭窒化層はＣＶＤ法などで形成される。
　接合層１３は、図４Ａに示すように吸収層１２とチップ２Ａ、２Ｂとの間に配置され、チップ２Ａ、２Ｂに接触する。接合層１３は、例えば、シリコン酸化層などの絶縁層である。接合層１３は、吸収層１２とは異なる材質でもよいし、同じ材質でもよい。後者の場合、吸収層１２が接合層１３を兼ねてもよい。
　接合層１３は、チップ２Ａ、２Ｂとの接合面１４に、アライメント用マーク１５を含む。アライメント用マーク１５は、カメラなどで撮像され、チップ２Ａ、２Ｂの位置制御に用いられる。なお、アライメント用マーク１５の位置は、接合層１３の接合面１４には限定されず、例えば吸収層１２、又は吸収層１２と接合層１３の間でもよい。
　一方、チップ２Ａは、シリコンウェハ２１Ａと、デバイス層２２Ａとを有する。デバイス層２２Ａは、シリコンウェハ２１Ａの表面に形成される。デバイス層２２Ａは、半導体素子、回路、又は端子などを含む。デバイス層２２Ａの形成後、シリコンウェハ２１Ａが複数のチップ２Ａに個片化される。
　チップ２Ｂは、チップ２Ａと同様に、シリコンウェハ２１Ｂと、デバイス層２２Ｂとを有する。デバイス層２２Ｂはデバイス層２２Ａとは異なる機能を有し、チップ２Ａとチップ２Ｂとは異なる厚みを有する。デバイス層２２Ｂの形成後、シリコンウェハ２１Ｂが複数のチップ２Ｂに個片化される。
　図１のＳ１に含まれる、図２のＳ１２では、第１基板１の接合面１４をプラズマなどで表面改質する。具体的には、接合面１４のＳｉＯ２の結合を切断し、Ｓｉの未結合手を形成し、接合面１４の親水化を可能にする。
　例えば減圧雰囲気下において処理ガスである酸素ガスが励起されてプラズマ化され、イオン化される。酸素イオンが接合面１４に照射され、接合面１４が改質される。処理ガスは、酸素ガスには限定されず、例えば窒素ガスなどでもよい。
　上記Ｓ１２では、第１基板１の接合面１４のみならず、チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂも、表面改質してもよい。第１基板１の接合面１４と、チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂとの少なくとも一方が表面改質される。
　図１のＳ１に含まれる、図２のＳ１３では、第１基板１の接合面１４を親水化する。例えば、スピンチャックで第１基板１を保持し、スピンチャックと共に回転する第１基板１の接合面１４にＤＩＷ（脱イオン水）などの純水を供給する。接合面１４のＳｉの未結合手にＯＨ基が付き、接合面１４が親水化される。
　上記Ｓ１３では、第１基板１の接合面１４のみならず、チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂも、親水化してもよい。第１基板１の接合面１４と、チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂとの少なくとも一方が親水化される。
　図１のＳ１に含まれる、図２のＳ１４では、チップ２Ａ、２Ｂを、１つずつ、第１基板１の接合面１４に一時的に接合する。チップ２Ａ、２Ｂは、デバイス層２２Ａ、２２Ｂを第１基板１に向けた状態で、第１基板１に接合される。
　チップ２Ａ、２Ｂと第１基板１とは、ファンデルワールス力（分子間力）及びＯＨ基同士の水素結合などで接合される。その後、接合強度を高めるべく、加熱処理が実施されてもよい。加熱処理によって、脱水反応が生じる。液体の接着剤を使用せずに、固体同士を直接貼り合わせるので、接着剤の変形などによる位置ずれと、接着剤の厚みムラなどによる傾きの発生とを防止できる。
　ところで、上記特許文献１では、本開示の技術とは異なり、第１基板１にチップ２Ａ、２Ｂを一時的に接合するステップを踏むことなく、後述の第３基板６にチップ２Ａ、２Ｂを永久的に接合する。それゆえ、接合時に、気泡や異物の噛み込みを抑制することと、位置制御を精度良く実施することの両方が同時に求められる。
　上記特許文献１のようにチップ２Ａ、２Ｂを１つずつ第３基板６に接合する場合、接合時の気泡の噛み込みを抑制するには、チップ２Ａ、２Ｂを１つずつ変形させればよい。チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂは、下に凸の曲面に変形され、中心から周縁に向けて徐々に第３基板６と接合され、最終的に平坦面に戻る。
　チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂを下に凸の曲面に変形させることは、チップ２Ａ、２Ｂのそれぞれの周縁を固定し、チップ２Ａ、２Ｂのそれぞれの中心を押下げることを含む。但し、チップ２Ａ、２Ｂの個々のサイズは小さいので、固定個所と押下個所との間隔が狭い。それゆえ、チップ２Ａ、２Ｂを１つずつ変形させるのは困難である。
　本実施形態によれば、チップ２Ａ、２Ｂは、第１基板１に一時的に接合され、後で第１基板１から分離される。それゆえ、チップ２Ａ、２Ｂと第１基板１との接合時に気泡が噛み込んでも問題にはならない。従って、上記Ｓ１４では、チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂを平坦面のまま、第１基板１の接合面１４に接合できる。チップ２Ａ、２Ｂを変形させないので、チップ２Ａ、２Ｂの位置制御の精度を向上でき、チップ２Ａ、２Ｂを目的の位置に正確に置くことができる。
　また、本実施形態によれば、チップ２Ａ、２Ｂは、第１基板１に一時的に接合され、後で第１基板１から分離される。それゆえ、チップ２Ａ、２Ｂと第１基板１との接合時にパーティクルが噛み込んでも問題にはならない。従って、第１基板１の接合面１４、及びチップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂは、接合に支障をきたさない程度に、汚れていてもよい。要求される清浄度が低くて済む。
　次に、図１のＳ２では、図４Ｃに示すように、複数のチップ２Ａ、２Ｂを薄化し、厚みを均一化する。図４Ｃにおいて、二点鎖線はＳ２の直前の状態を、実線はＳ２の完了時の状態を示す。チップ２Ａ、２Ｂのうち、シリコンウェハ２１Ａ、２１Ｂが薄化され、デバイス層２２Ａ、２２Ｂは薄化されない。薄化は、研削加工、又はレーザー加工を含む。
　次に、図１のＳ３では、図４Ｄに示すように、チップ２Ａ、２Ｂの表面に、接合層３を形成する。接合層３は、第１基板１の接合層１３と同様に、シリコン酸化層などの絶縁層であり、ＣＶＤ法などで形成される。チップ２Ａ、２Ｂ同士は間隔をおいて配置され、接合層３の下地面は凹凸を有するので、接合層３の表面も凹凸を有する。
　次に、図１のＳ４では、図４Ｅ及び図４Ｆに示すように、接合層３の表面を平坦化する。接合層３は、シリコン酸化層などであり、高い硬度を有するので、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）などの研磨は、平坦化に時間を要する。
　そこで、先ず、図４Ｅに示すように、接合層３の凸部３１にレーザー光線ＬＢ１を照射する。凸部３１は、レーザー光線ＬＢ１を吸収し、固相から気相に状態変化し飛散するか、又は固相のまま飛散する。なお、レーザー光線ＬＢ１は、接合層３の凹部３２にも照射されてもよい。凹部３２の照射強度が凸部３１の照射強度よりも低ければ、接合層３の表面を平坦化できる。
　レーザー光線ＬＢ１の照射点は、ガルバノスキャナ又はＸＹθステージによって移動される。ガルバノスキャナは、レーザー光線ＬＢ１を移動させる。ＸＹθステージは、第１基板１を、水平方向（Ｘ軸方向及びＹ軸方向）に移動させ、鉛直軸周りに回転させる。ＸＹθステージの代わりに、ＸＹＺθステージが用いられてもよい。
　続いて、図４Ｆに示すように、接合層３の表面を、ＣＭＰなどで更に平坦化する。ＣＭＰの前に凸部３１を選択的に除去済みであるので、ＣＭＰの後に接合層３の表面に残るうねりを低減できる。
　次に、図１のＳ５では、図４Ｇに示すように、チップ２Ａ、２Ｂと第２基板５を接合する。第２基板５は、接合層３の平坦化された表面に接触し、接合層３を介してチップ２Ａ、２Ｂと接合される。
　第２基板５は、例えば、シリコンウェハ５１と、接合層５３とを有する。接合層５３は、第１基板１の接合層１３と同様に、シリコン酸化層などの絶縁層であり、ＣＶＤ法などで形成される。
　第２基板５の接合面５４と、接合層３の接合面３４との少なくとも一方には、接合前に、表面改質及び親水化が施されてもよい。第２基板５と接合層３とは、ファンデルワールス力（分子間力）及びＯＨ基同士の水素結合などで接合される。液体の接着剤を使用せずに、固体同士を直接貼り合わせるので、接着剤の変形などによる位置ずれを防止できる。また、接着剤の厚みムラなどによる傾きの発生を防止できる。
　第２基板５は、その接合面５４を下に向けて、接合層３を介して第１基板１に接合される。つまり、基板同士が貼り合わされる。その際、第２基板５の接合面５４は、気泡の噛み込みを防止すべく、下に凸の曲面に変形され、中心から周縁に向けて徐々に接合され、最終的に平坦面に戻る。
　第２基板５の変形は、第２基板５の周縁を固定し、第２基板５の中心を押下することで実現できる。第２基板５を変形させる場合、チップ２Ａ、２Ｂを１つずつ変形させる場合に比べて、固定個所と押下個所との間隔が広いので、変形が容易である。変形が容易であるのは、基板同士の貼り合わせだからである。
　なお、第２基板５と第１基板１の配置は逆でもよく、第２基板５が第１基板１の下方に配置されてもよく、第２基板５の接合面５４は上向きであってもよい。この場合、第２基板５の接合面５４は、気泡の噛み込みを防止すべく、上に凸の曲面に変形され、中心から周縁に向けて徐々に接合され、最終的に平坦面に戻る。
　なお、第２基板５と第１基板１の接合は、中心から周縁に向けて徐々に実施するべく、最初に第２基板５を曲げ変形させるが、最初に第１基板１を曲げ変形させてもよい。この場合も、基板同士が貼り合わされる。但し、第１基板１を平坦に保持し、チップ２Ａ、２Ｂを平坦に保持することが、チップ２Ａ、２Ｂの保護の観点からは好ましい。
　次に、図１のＳ６では、図４Ｈ、図４Ｉ及び図４Ｊに示すように、チップ２Ａ、２Ｂを第１基板１から分離する。図１のＳ６に含まれる、図３のＳ６１では、図４Ｈに示すように、第１基板１を厚み方向に分割する予定の分割面Ｄに、レーザー光線ＬＢ２で複数の改質層Ｍを形成する。改質層Ｍは、点状に形成され、例えば集光点又は集光点よりも上方に形成される。
　レーザー光線ＬＢ２は、第１基板１のシリコンウェハ１１を通り、第１基板１の吸収層１２に改質層Ｍを形成する。吸収層１２は、シリコンウェハ１１とチップ２Ａ、２Ｂとの間に配置され、レーザー光線ＬＢ２を吸収する。レーザー光線ＬＢ２がチップ２Ａ、２Ｂにほとんど当らないので、チップ２Ａ、２Ｂの破損を抑制できる。
　レーザー光線ＬＢ２は、シリコンウェハ１１を透過し、吸収層１２で吸収されるべく、例えば８．８μｍ～１１μｍの波長を有する。レーザー光線ＬＢ２の光源は、例えばＣＯ２レーザーである。ＣＯ２レーザーの波長は、約９．３μｍである。レーザー光線ＬＢ２は、パルス発振される。
　改質層Ｍの形成位置は、ガルバノスキャナ又はＸＹθステージによって移動される。ガルバノスキャナは、レーザー光線ＬＢ２を移動させる。ＸＹθステージは、第１基板１を、水平方向（Ｘ軸方向及びＹ軸方向）に移動させ、鉛直軸周りに回転させる。ＸＹθステージの代わりに、ＸＹＺθステージが用いられてもよい。
　改質層Ｍは、第１基板１の周方向及び径方向に間隔をおいて複数形成される。改質層Ｍの形成時に、改質層Ｍ同士をつなぐクラックＣＲも形成される。
　図１のＳ６に含まれる、図３のＳ６２では、図４Ｉに示すように、改質層Ｍを起点に第１基板１を分割する。先ず、上チャック１３１が第１基板１を保持し、下チャック１３２が第２基板５を保持する。但し、第１基板１と第２基板５の配置は上下逆でもよく、上チャック１３１が第２基板５を保持し、下チャック１３２が第１基板１を保持してもよい。次に、上チャック１３１が下チャック１３２に対して上昇すると、改質層Ｍを起点にクラックＣＲが面状に広がり、第１基板１が分割面Ｄにて分割される。
　上記Ｓ６２では、上チャック１３１の上昇と共に、上チャック１３１の鉛直軸周りの回転を実施してもよい。第１基板１を分割面Ｄでねじ切ることができる。なお、上チャック１３１の上昇の代わりに、又は上チャック１３１の上昇に加えて、下チャック１３２の下降が実施されてもよい。また、下チャック１３２の鉛直軸周りの回転が実施されてもよい。
　図１のＳ６に含まれる、図３のＳ６３では、図４Ｊに示すように、チップ２Ａ、２Ｂに付着する第１基板１の残留物１６をＣＭＰなどによって除去する。残留物１６は、吸収層１２の一部と、接合層１３とを含む。残留物１６の除去後、チップ２Ａ、２Ｂのデバイス層２２Ａ、２２Ｂが再び露出する。
　次に、図１のＳ７では、図４Ｋに示すように、チップ２Ａ、２Ｂを、第２基板５に接合した状態で、第３基板６のデバイス層６２を含む片面６４に接合する。第３基板６は、シリコンウェハ６１と、デバイス層６２とを含む。
　デバイス層６２は、シリコンウェハ６１の表面に形成される。デバイス層６２は、半導体素子、回路、又は端子などを含み、チップ２Ａ、２Ｂのデバイス層２２Ａ、２２Ｂと電気的に接続される。
　第３基板６の接合面６４と、チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂとの少なくとも一方には、接合前に、表面改質及び親水化が施されてもよい。第３基板６とチップ２Ａ、２Ｂとは、ファンデルワールス力（分子間力）及びＯＨ基同士の水素結合などで接合される。液体の接着剤を使用せずに、固体同士を直接貼り合わせるので、接着剤の変形などによる位置ずれを防止できる。また、接着剤の厚みムラなどによる傾きの発生を防止できる。
　第３基板６は、その接合面６４を下に向けて、チップ２Ａ、２Ｂを介して第２基板５に接合される。つまり、基板同士が貼り合わされる。その際、第３基板６の接合面６４は、気泡の噛み込みを防止すべく、下に凸の曲面に変形され、中心から周縁に向けて徐々に接合され、最終的に平坦面に戻る。
　第３基板６の変形は、第３基板６の周縁を固定し、第３基板６の中心を押下することで実現できる。第３基板６を変形させる場合、チップ２Ａ、２Ｂを１つずつ変形させる場合に比べて、固定個所と押下個所との間隔が広いので、変形が容易である。変形が容易であるのは、基板同士の貼り合わせだからである。
　なお、第３基板６と第２基板５の配置は逆でもよく、第３基板６が第２基板５の下方に配置されてもよく、第３基板６の接合面６４は上向きであってもよい。この場合、第３基板６の接合面６４は、気泡の噛み込みを防止すべく、上に凸の曲面に変形され、中心から周縁に向けて徐々に接合され、最終的に平坦面に戻る。この場合も、基板同士が貼り合わされる。
　なお、第３基板６と第２基板５の接合は、中心から周縁に向けて徐々に実施するべく、最初に第３基板６を曲げ変形させるが、最初に第２基板５を曲げ変形させてもよい。この場合も、基板同士が貼り合わされる。
　上記Ｓ７によって、チップ付き基板７が得られる。チップ付き基板７は、第３基板６と複数のチップ２Ａ、２Ｂを含む。チップ付き基板７は、更に第２基板５を含む。なお、第２基板５はチップ２Ａ、２Ｂから分離されてもよく、チップ付き基板７は第３基板６とチップ２Ａ、２Ｂを含めばよい。
　以上説明したように、本実施形態によれば、チップ付き基板７を得るのに、複数のチップ２Ａ、２Ｂを１つずつ第３基板６の片面に接合するのではなく、先ずは第１基板１の片面に一時的に接合する。この段階での気泡の噛み込みは問題にはならないので、チップ２Ａ、２Ｂの接合面２４Ａ、２４Ｂを、平坦面のまま、第１基板１の接合面１４に接合できる。チップ２Ａ、２Ｂを無理に変形させずに済むので、チップ２Ａ、２Ｂの位置制御の精度を向上でき、チップ２Ａ、２Ｂを目的の位置に正確に置くことができる。
　その後、第１基板１に接合された複数のチップ２Ａ、２Ｂを、第２基板５の第１基板１との対向面に接合する。続いて、第１基板１及び第２基板５に接合された複数のチップ２Ａ、２Ｂを、第１基板１から分離する。次に、第１基板１から分離した複数のチップ２Ａ、２Ｂを、第２基板５に接合した状態で、第３基板６のデバイス層６２を含む片面６４に接合する。
　その際、第３基板６の接合面６４は、気泡の噛み込みを防止すべく、下に凸の曲面に変形され、中心から周縁に向けて徐々に接合され、最終的に平坦面に戻る。第３基板６を変形させることは、チップ２Ａ、２Ｂを１つずつ変形させることに比べて容易である。基板同士の貼り合わせだからである。それゆえ、上記特許文献１のように第１基板１にチップ２Ａ、２Ｂを一時的に接合するステップを踏むことなく、第３基板６にチップ２Ａ、２Ｂを永久的に接合する場合に比べて、気泡の噛み込みが無く、位置精度も良好な、チップ付き基板７が得られる。
　次に、図５等を参照して、図３のＳ６１及びＳ６２を実施する基板処理装置１００について説明する。図５において、Ｘ軸方向、Ｙ軸方向及びＺ軸方向は互いに垂直な方向であって、Ｘ軸方向及びＹ軸方向は水平方向、Ｚ軸方向は鉛直方向である。基板処理装置１００は、搬入出部１０１と、搬送部１１０と、レーザー加工部１２０と、分割部１３０と、制御部１４０とを有する。
　搬入出部１０１は、カセットＣが載置される載置部１０２を有する。カセットＣは、図４Ｇ等に示す積層基板８を、鉛直方向に間隔をおいて複数枚収容する。積層基板８は、複数のチップ２Ａ、２Ｂと、第１基板１と、第２基板５とを含む。積層基板８は、図４Ｉに示すように、分割面Ｄにて第１分割体８１と第２分割体８２とに分割される。その後、第１分割体８１と第２分割体８２とは、別々に、カセットＣに収容される。第１分割体８１は、シリコンウェハ１１を含み、基板処理装置１００の外部に搬出された後、再び、新しい第１基板１として再利用可能である。一方、第２分割体８２は、チップ２Ａ、２Ｂを含み、基板処理装置１００の外部に搬出された後、図３のＳ６３、及び図１のＳ７等に供される。なお、載置部１０２の数、及びカセットＣの数は、図５に示すものには限定されない。
　搬送部１１０は、搬入出部１０１、レーザー加工部１２０及び分割部１３０の隣に配置され、これらに対して積層基板８等を搬送する。搬送部１１０は、積層基板８等を保持する保持機構を有する。保持機構は、水平方向（Ｘ軸方向及びＹ軸方向の両方向）及び鉛直方向への移動、並びに鉛直軸を中心とする回転が可能である。
　レーザー加工部１２０は、図４Ｈに示すように、第１基板１を厚み方向に分割する予定の分割面Ｄにレーザー光線ＬＢ２で複数の改質層Ｍを形成する。改質層Ｍは、点状に形成され、例えば集光点又は集光点の上方に形成される。レーザー加工部１２０は、例えば、第１基板１を保持するステージ１２１と、ステージ１２１で保持された第１基板１にレーザー光線ＬＢ２を照射する光学系１２２とを含む。ステージ１２１は、例えばＸＹθステージ又はＸＹＺθステージである。光学系１２２は、例えば集光レンズを含む。集光レンズは、レーザー光線ＬＢ２を第１基板１に向けて集光する。光学系１２２は、更にガルバノスキャナを含んでもよい。
　分割部１３０は、図４Ｉに示すように、改質層Ｍを起点に第１基板１を分割する。分割部１３０は、例えば、上チャック１３１と下チャック１３２とを含む。上チャック１３１が第１基板１を保持し、下チャック１３２が第２基板５を保持する。但し、第１基板１と第２基板５の配置は上下逆でもよい。次に、上チャック１３１が下チャック１３２に対して上昇すると、改質層Ｍを起点にクラックＣＲが面状に広がり、第１基板１が分割面Ｄにて分割される。言い換えると、積層基板８が分割面Ｄにて第１分割体８１と第２分割体８２とに分割される。上チャック１３１の上昇と共に、上チャック１３１の鉛直軸周りの回転を実施してもよい。第１基板１を分割面Ｄでねじ切ることができる。
　制御部１４０は、例えばコンピュータであり、図５に示すように、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）１４１と、メモリなどの記憶媒体１４２とを備える。記憶媒体１４２には、基板処理装置１００において実行される各種の処理を制御するプログラムが格納される。制御部１４０は、記憶媒体１４２に記憶されたプログラムをＣＰＵ１４１に実行させることにより、基板処理装置１００の動作を制御する。また、制御部１４０は、入力インターフェース１４３と、出力インターフェース１４４とを備える。制御部１４０は、入力インターフェース１４３で外部からの信号を受信し、出力インターフェース１４４で外部に信号を送信する。
　上記プログラムは、例えばコンピュータによって読み取り可能な記憶媒体に記憶され、その記憶媒体から制御部１４０の記憶媒体１４２にインストールされる。コンピュータによって読み取り可能な記憶媒体としては、例えば、ハードディスク（ＨＤ）、フレキシブルディスク（ＦＤ）、コンパクトディスク（ＣＤ）、マグネットオプティカルデスク（ＭＯ）、メモリーカードなどが挙げられる。なお、プログラムは、インターネットを介してサーバからダウンロードされ、制御部１４０の記憶媒体１４２にインストールされてもよい。
　以上、本開示に係るチップ付き基板の製造方法、及び基板処理装置の実施形態について説明したが、本開示は上記実施形態などに限定されない。特許請求の範囲に記載された範疇内において、各種の変更、修正、置換、付加、削除、及び組み合わせが可能である。それらについても当然に本開示の技術的範囲に属する。
　本出願は、２０１９年１０月２９日に日本国特許庁に出願した特願２０１９－１９６３８６号に基づく優先権を主張するものであり、特願２０１９－１９６３８６号の全内容を本出願に援用する。
１　　第１基板
１１　シリコンウェハ
１２　吸収層
１６　残留物
２Ａ、２Ｂ　　チップ
３　　接合層
５　　第２基板
６　　第３基板
７　　チップ付き基板
８　　積層基板
１００　基板処理装置
１１０　搬送部
１２０　レーザー加工部
１３０　分割部
ＬＢ２　レーザー光線
Ｄ　　　分割面
Ｍ　　　改質層

Claims (16)

  1. 　複数のチップと、複数の前記チップが一時的に接合された第１基板と、複数の前記チップを介して前記第１基板に接合された第２基板とを含む積層基板を準備することと、
    　前記第１基板及び前記第２基板に接合された複数の前記チップを、第３基板のデバイス層を含む片面に接合すべく、前記第１基板から分離することと、
    を有する、チップ付き基板の製造方法。
  2. 　複数の前記チップと前記第１基板との分離は、前記第１基板を厚み方向に分割する予定の分割面にレーザー光線で複数の改質層を形成することと、複数の前記改質層を起点に前記第１基板を分割することと、を含む、請求項１に記載のチップ付き基板の製造方法。
  3. 　前記第１基板は、シリコンウェハと、前記シリコンウェハと前記チップとの間にて前記レーザー光線を吸収する吸収層とを含み、
    　前記レーザー光線は、前記シリコンウェハを通り、前記吸収層に前記改質層を形成する、請求項２に記載のチップ付き基板の製造方法。
  4. 　前記吸収層は、シリコン酸化層である、請求項３に記載のチップ付き基板の製造方法。
  5. 　前記レーザー光線の波長は、８．８μｍ～１１μｍである、請求項２～４のいずれか１項に記載のチップ付き基板の製造方法。
  6. 　複数の前記チップと前記第１基板との分離は、前記第１基板の前記分割面での分割後に、前記チップに付着する前記第１基板の残留物を除去することを更に含む、請求項２～５のいずれか１項に記載のチップ付き基板の製造方法。
  7. 　前記第１基板から分離した複数の前記チップを、前記第２基板に接合した状態で、前記第３基板の前記デバイス層を含む片面に接合することを更に有する、請求項１～６のいずれか１項に記載のチップ付き基板の製造方法。
  8. 　複数の前記チップを、１つずつ、前記第１基板の片面に一時的に接合することと、
    　前記第１基板に接合された複数の前記チップを、前記第２基板の前記第１基板との対向面に接合することと、
    を更に有する、請求項１～７のいずれか１項に記載のチップ付き基板の製造方法。
  9. 　複数のチップを、１つずつ、第１基板の片面に一時的に接合することと、
    　前記第１基板に接合された複数の前記チップを、第２基板の前記第１基板との対向面に接合することと、
    　前記第１基板及び前記第２基板に接合された複数の前記チップを、前記第１基板から分離することと、
    　前記第１基板から分離した複数の前記チップを、前記第２基板に接合した状態で、第３基板のデバイス層を含む片面に接合することと、
    を有する、チップ付き基板の製造方法。
  10. 　複数の前記チップと前記第１基板との接合後、複数の前記チップと前記第２基板との接合前に、複数の前記チップを薄化し、厚みを均一化することを更に有する、請求項８又は９に記載のチップ付き基板の製造方法。
  11. 　複数の前記チップの薄化後、複数の前記チップと前記第２基板との接合前に、前記チップと前記第２基板とを接合する接合層を、前記チップの表面に形成することを更に有する、請求項１０に記載のチップ付き基板の製造方法。
  12. 　前記接合層の形成後、複数の前記チップと前記第２基板の接合前に、前記接合層の前記第３基板との接触面を平坦化することを更に有する、請求項１１に記載のチップ付き基板の製造方法。
  13. 　複数のチップと、複数の前記チップが一時的に接合された第１基板と、複数の前記チップを介して前記第１基板に接合された第２基板とを含む積層基板を搬送する搬送部と、
    　前記第１基板を厚み方向に分割する予定の分割面にレーザー光線で複数の改質層を形成するレーザー加工部と、
    　複数の前記改質層を起点に前記第１基板を分割する分割部とを有する、基板処理装置。
  14. 　前記第１基板は、シリコンウェハと、前記シリコンウェハと前記チップとの間にて前記レーザー光線を吸収する吸収層とを含み、
    　前記レーザー光線は、前記シリコンウェハを通り、前記吸収層に前記改質層を形成する、請求項１３に記載の基板処理装置。
  15. 　前記吸収層は、シリコン酸化層である、請求項１４に記載の基板処理装置。
  16. 　前記レーザー加工部は、前記レーザー光線の光源であるＣＯ２レーザーを含む、請求項１４又は１５に記載の基板処理装置。
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