JP5982097B2 - 積層半導体メモリ装置、これを含むメモリシステム及び貫通電極の欠陥リペア方法 - Google Patents

積層半導体メモリ装置、これを含むメモリシステム及び貫通電極の欠陥リペア方法 Download PDF

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JP5982097B2
JP5982097B2 JP2011121586A JP2011121586A JP5982097B2 JP 5982097 B2 JP5982097 B2 JP 5982097B2 JP 2011121586 A JP2011121586 A JP 2011121586A JP 2011121586 A JP2011121586 A JP 2011121586A JP 5982097 B2 JP5982097 B2 JP 5982097B2
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input
defect
electrode
memory device
semiconductor memory
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JP2011253607A5 (https=
JP2011253607A (ja
Inventor
台榮 ▲呉▼
台榮 ▲呉▼
光一 朴
光一 朴
潤碩 梁
潤碩 梁
寧洙 孫
寧洙 孫
始弘 金
始弘 金
升浚 ▲ペ▼
升浚 ▲ぺ▼
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/232—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising connection or disconnection of parts of a device in response to a measurement
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2011121586A 2010-06-01 2011-05-31 積層半導体メモリ装置、これを含むメモリシステム及び貫通電極の欠陥リペア方法 Active JP5982097B2 (ja)

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KR1020100051733A KR101728068B1 (ko) 2010-06-01 2010-06-01 적층 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 관통전극 결함리페어 방법
KR10-2010-0051733 2010-06-01

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JP2011253607A JP2011253607A (ja) 2011-12-15
JP2011253607A5 JP2011253607A5 (https=) 2014-06-05
JP5982097B2 true JP5982097B2 (ja) 2016-08-31

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US (1) US8654593B2 (https=)
JP (1) JP5982097B2 (https=)
KR (1) KR101728068B1 (https=)
CN (1) CN102270504B (https=)
TW (1) TWI532051B (https=)

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Also Published As

Publication number Publication date
TW201201218A (en) 2012-01-01
CN102270504B (zh) 2016-08-31
US8654593B2 (en) 2014-02-18
TWI532051B (zh) 2016-05-01
KR20110131976A (ko) 2011-12-07
US20110292742A1 (en) 2011-12-01
KR101728068B1 (ko) 2017-04-19
JP2011253607A (ja) 2011-12-15
CN102270504A (zh) 2011-12-07

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