KR101728068B1 - 적층 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 관통전극 결함리페어 방법 - Google Patents

적층 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 관통전극 결함리페어 방법 Download PDF

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KR101728068B1
KR101728068B1 KR1020100051733A KR20100051733A KR101728068B1 KR 101728068 B1 KR101728068 B1 KR 101728068B1 KR 1020100051733 A KR1020100051733 A KR 1020100051733A KR 20100051733 A KR20100051733 A KR 20100051733A KR 101728068 B1 KR101728068 B1 KR 101728068B1
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input
memory chip
output buffers
electrodes
memory
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KR20110131976A (ko
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오태영
박광일
양윤석
손영수
김시홍
배승준
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삼성전자 주식회사
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Priority to KR1020100051733A priority Critical patent/KR101728068B1/ko
Priority to US13/085,776 priority patent/US8654593B2/en
Priority to TW100115493A priority patent/TWI532051B/zh
Priority to CN201110141841.0A priority patent/CN102270504B/zh
Priority to JP2011121586A priority patent/JP5982097B2/ja
Publication of KR20110131976A publication Critical patent/KR20110131976A/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/232—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising connection or disconnection of parts of a device in response to a measurement
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
KR1020100051733A 2010-06-01 2010-06-01 적층 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 관통전극 결함리페어 방법 Active KR101728068B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020100051733A KR101728068B1 (ko) 2010-06-01 2010-06-01 적층 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 관통전극 결함리페어 방법
US13/085,776 US8654593B2 (en) 2010-06-01 2011-04-13 Stacked semiconductor memory device, memory system including the same, and method of repairing defects of through silicon vias
TW100115493A TWI532051B (zh) 2010-06-01 2011-05-03 堆疊式半導體記憶體裝置、包括其之記憶體系統及修復直通矽穿孔缺陷之方法
CN201110141841.0A CN102270504B (zh) 2010-06-01 2011-05-30 堆叠半导体存储器件、存储器系统及修复硅通孔缺陷的方法
JP2011121586A JP5982097B2 (ja) 2010-06-01 2011-05-31 積層半導体メモリ装置、これを含むメモリシステム及び貫通電極の欠陥リペア方法

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Application Number Priority Date Filing Date Title
KR1020100051733A KR101728068B1 (ko) 2010-06-01 2010-06-01 적층 반도체 메모리 장치, 이를 포함하는 메모리 시스템, 및 관통전극 결함리페어 방법

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KR20110131976A KR20110131976A (ko) 2011-12-07
KR101728068B1 true KR101728068B1 (ko) 2017-04-19

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US (1) US8654593B2 (https=)
JP (1) JP5982097B2 (https=)
KR (1) KR101728068B1 (https=)
CN (1) CN102270504B (https=)
TW (1) TWI532051B (https=)

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TWI501361B (zh) 2012-12-27 2015-09-21 財團法人工業技術研究院 矽穿孔修補電路
US9679615B2 (en) 2013-03-15 2017-06-13 Micron Technology, Inc. Flexible memory system with a controller and a stack of memory
US8890607B2 (en) 2013-03-15 2014-11-18 IPEnval Consultant Inc. Stacked chip system
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KR102104578B1 (ko) * 2013-08-30 2020-04-27 에스케이하이닉스 주식회사 데이터 비트 인버전 기능을 갖는 반도체 장치
KR102111742B1 (ko) 2014-01-14 2020-05-15 삼성전자주식회사 적층 반도체 패키지
KR101583939B1 (ko) 2014-06-10 2016-01-22 한양대학교 에리카산학협력단 리페어 가능한 관통 전극을 갖는 반도체 장치
KR102125340B1 (ko) 2014-06-19 2020-06-23 삼성전자주식회사 신호 전달을 위한 주 경로 및 우회 경로를 갖는 집적 회로 및 그것을 포함하는 집적 회로 패키지
KR20160006991A (ko) * 2014-07-10 2016-01-20 에스케이하이닉스 주식회사 복수의 채널 및 관통 비아를 포함하는 반도체 장치
KR101503737B1 (ko) * 2014-07-15 2015-03-20 연세대학교 산학협력단 반도체 장치
KR102313949B1 (ko) * 2014-11-11 2021-10-18 삼성전자주식회사 스택 반도체 장치 및 이를 포함하는 메모리 장치
TWI556247B (zh) 2014-11-12 2016-11-01 財團法人工業技術研究院 錯誤容忍穿矽孔介面及其控制方法
US9627088B2 (en) * 2015-02-25 2017-04-18 Ememory Technology Inc. One time programmable non-volatile memory and read sensing method thereof
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KR102451996B1 (ko) * 2016-03-31 2022-10-07 삼성전자주식회사 기준 전압의 셀프 트레이닝을 수행하는 수신 인터페이스 회로 및 이를 포함하는 메모리 시스템
KR102498883B1 (ko) * 2018-01-31 2023-02-13 삼성전자주식회사 전류를 분산시키는 관통 전극들을 포함하는 반도체 장치
KR20190105346A (ko) * 2018-03-05 2019-09-17 삼성전자주식회사 메모리 패키지 및 메모리 장치
KR102471416B1 (ko) * 2018-05-23 2022-11-29 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 메모리 모듈
US12300688B2 (en) * 2018-07-02 2025-05-13 Shanghai Denglin Technologies Co. Ltd Configurable random-access memory (RAM) array including through-silicon via (TSV) bypassing physical layer
CN109817540B (zh) * 2019-01-30 2021-06-08 上海华虹宏力半导体制造有限公司 晶圆检测缺陷的分类方法
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TW201201218A (en) 2012-01-01
CN102270504B (zh) 2016-08-31
JP5982097B2 (ja) 2016-08-31
US8654593B2 (en) 2014-02-18
TWI532051B (zh) 2016-05-01
KR20110131976A (ko) 2011-12-07
US20110292742A1 (en) 2011-12-01
JP2011253607A (ja) 2011-12-15
CN102270504A (zh) 2011-12-07

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