TWI524471B - 具有主/從可組態設定的微電子元件 - Google Patents
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Description
本發明關於具有主/從可組態設定的微電子元件。
微電子裝置通常包含複數半導體晶片。此等晶片往往具有扁平的長方形主體,其中之大型正面具有連接至晶片內部電路之接觸點。每一個別晶片可以包含於一封裝套件之中,該封裝套件具有外部接頭,該等接頭又電性連接至一諸如印刷電路板之電路面板,且將晶片之接觸點連接至電路面板之導體。或者,該等晶片可以彼此堆疊於一電性連接組件之中,以限制晶片在電路板上的佔用面積。
該複數半導體晶片通常以半導體晶片陣列之形式彼此協調運作,其中一半導體晶片充當一主控晶片(master chip)以控制往返於其他從屬晶片(slave chip)之資料的傳輸。此等主控晶片包含從屬晶片之中所沒有的電路,諸如串行器(serializer)/解串器(deserializer),以控制輸入-輸出信號之流動。因此,在此等組件之中,僅有主控晶片可以執行主控晶片所需之操作。若該特別晶片無法正常運作,則整個半導體晶片陣列可能變得沒有作用。
在本揭示的一特色之中,一半導體晶片可以包含可連接至一
晶片外資料匯流排之複數資料線,以供在該半導體晶片與至少一其他半導體晶片之間傳送資料信號。該半導體晶片亦可以包含晶片選擇控制,以供將該半導體晶片指定成一主控晶片或一從屬晶片,以及主控晶片電路,被組構成用以在其中該晶片選擇控制將該半導體晶片指定成一主控晶片之一狀態中執行做為一主控晶片之操作。該主控晶片電路可以包含用以在位於資料線之上或位於資料匯流排之上之一第一格式之第一資料信號與位於半導體晶片之一外部資料輸入-輸出介面上之一第二格式之第二資料信號之間進行轉換之電路。該主控晶片電路可以包含一串行器/解串器("SerDes"),被組構成用以在第一資料信號與第二資料信號之間進行轉換,該第二資料信號被串行化自該第一資料信號,而該第一資料信號則被解串化自該第二資料信號。
依據另一特色,該半導體晶片可以是一DRAM晶片,而該晶片外資料匯流排可以是一直通矽通孔(TSV)匯流排。
依據又另一特色,該晶片可以包含具有至少二狀態之一保險絲,且其中該晶片選擇控制被組構成用以依據該保險絲之該至少二狀態被致能或禁能。此外,該保險絲之一狀態可以被組構成藉由電氣信號或雷射光於該至少二狀態之間變換。
依據另一特色,該晶片選擇控制可以是能夠依據來自一微控制器之一信號而被組態設定。
依據另一特色,該半導體晶片另包含一開關。當晶片選擇控制將該半導體晶片指定成一主控晶片之時,該複數資料線中之一資料線可以藉由該開關連接該主控晶片電路,而當晶片選擇控制未將該半導體晶片
指定成一主控晶片之時,該複數資料線中之一資料線可以藉由該開關斷離該主控晶片電路。該開關可以是對應至該複數資料線中之每一者之複數開關。
依據又另一特色,該外部輸入-輸出介面可以連接至不同於該資料匯流排之一輸入-輸出匯流排。當該半導體晶片被指定成一從屬晶片之時,該輸入-輸出介面可以被設定成一高阻抗,或者一終端阻抗(termination impedance)可以施加於該輸入-輸出介面。
依據仍另一特色,一微電子組件可以包含複數半導體晶片,直接透過一資料匯流排彼此電性互連。每一半導體晶片之組態均可以被擇一設定成一主控晶片或者一從屬晶片。此外,每一晶片均可以具有一晶片選擇控制,此晶片選擇控制具有一第一狀態及一第二狀態。當該複數半導體晶片中之一第一晶片之晶片選擇控制係處於該第一狀態之時,該第一晶片被組構成用以執行主控晶片操作,而當該第一晶片之晶片選擇控制係處於該第二狀態之時,該第一晶片未被組構成用以執行主控晶片操作。該主控晶片操作可以包含在位於資料匯流排上之一第一格式之第一資料信號與位於第一半導體晶片之一外部資料輸入-輸出介面上之一第二格式之第二資料信號之間進行轉換。
依據又另一特色,在晶片選擇控制自該第二狀態轉移至該第一狀態之時,該複數半導體晶片中之一第二晶片即可以停止執行主控晶片操作。
依據另一特色,該主控晶片電路可以包含一SerDes,被組構成用以在第一資料信號與第二資料信號之間進行轉換,該第二資料信號被
串行化自該第一資料信號,而該第一資料信號則被解串化自該第二資料信號。
依據仍另一特色,在晶片選擇控制自該第一狀態轉移至該第二狀態之時,該第一晶片即可以停止發送信號至該第一晶片中負責執行主控晶片操作之部分。
100‧‧‧微電子組件
110‧‧‧半導體晶片
110a-d‧‧‧半導體晶片
112‧‧‧導電接觸
114‧‧‧導電接合材料
116‧‧‧矽通孔
120‧‧‧基板
202‧‧‧記憶體電路
204‧‧‧主控電路
206‧‧‧晶片選擇控制
208‧‧‧開關
210‧‧‧TSV匯流排
212‧‧‧I/O串行器/解串器/SerDes電路
214‧‧‧輸入-輸出介面
222‧‧‧記憶體儲存陣列
224‧‧‧位址控制邏輯
226‧‧‧解碼器
260‧‧‧TSV匯流排
302‧‧‧開關
304‧‧‧開關
306‧‧‧及閘
308a-d‧‧‧開關
402‧‧‧或閘
406‧‧‧及閘
506‧‧‧晶片選擇控制
圖1係一截面視圖,例示依據本揭示之特色之一微電子元件。
圖2係一方塊圖,例示依據本揭示之特色之一微電子晶片之電路。
圖3係一功能方塊圖,例示依據本揭示之特色之開關電路。
圖4係一功能方塊圖,例示依據本揭示之特色之其他開關電路。
圖1例示一示範性微電子組件,其包含四個堆疊半導體晶片110a-d或者"複數晶片"。每一晶片110均可以藉由導電接觸112、導電接合材料114、以及直通矽通孔或穿孔(以下稱"TSV" 116)電性連接至堆疊中的另一晶片110。晶片110a-d之堆疊可以或可以不進一步電性連接一基板120,諸如一封裝套件之一基板,用以將該封裝套件與一電路面板(圖中未顯示)互連。晶片110a-d可以執行任何數目之功能,使得晶片之間能夠維持一主/從關係。例如,晶片110a-d中的每一者均可以是一記憶體儲存陣列晶片或者可以包含一或多個記憶體儲存陣列。在一實例之中,每一晶片均可以是一動態隨機存取記憶體("DRAM")晶片。在一特別的實例之中,每一晶片110可以是一高密度記憶體晶片,諸如一第三代雙倍資料率同步動態隨機存取
記憶體("DDR3 SDRAM")。
圖2例示依據本揭示一特色之一晶片110。特別是,晶片110可以包含特定之功能區塊,諸如記憶體電路202、主控電路204、晶片選擇控制206、以及開關208,其全部均電性連接至一TSV匯流排210。雖然在圖2之中每一功能區塊之間的連接均被描繪成單一連線,但其應理解,連接的電路區塊之間可以存在多重連線之連接。舉例而言,TSV匯流排210可以是一晶片外或"晶片間"資料匯流排,其包含眾多資料線,用以直接連接微電子組件100(亦稱作堆疊組件)(圖1)中之每一記憶體晶片上的對應內部資料線組以及堆疊組件100中之一第二記憶體晶片及其他類似記憶體晶片上的對應內部資料線。TSV匯流排210可以透過開關208(圖2)、302(圖3、4)連接,以傳送資料至堆疊組件內被指定成一"主控"晶片之一晶片110之主控電路204並自其接收資料。在本文的闡述之中,"相連"、"相連的"、"可連接"、以及"連接"等詞可以表示二或多個構件之間的直接或間接耦接。因此,一第一構件與一第二構件可以透過一第三構件彼此連接。
主控電路204包含晶片110做為一主控晶片所需要的電路,以控制一外部資料輸入-輸出介面214與TSV匯流排210之間的資料流。例如,主控電路204可以包含I/O串行器/解串器212(本文以下稱其為"SerDes電路")。舉例而言,主控電路204及SerDes電路,當作用之時,可被用以進行位於晶片內的資料線上或者晶片間的資料匯流排上之一第一格式之資料信號與位於晶片110之任何外部資料輸入-輸出介面214上之一第二格式之資料信號之間的轉換。此外部資料輸入-輸出介面可以包含晶片110之"DQ"介面,用以在被指定為一主控者之晶片110與一電路面板或電路板之間轉
移資料,舉例而言,諸如透過位於基板120上之一組對應之封裝套件接頭。記憶體電路202包含執行一DRAM晶片之讀取/寫入指令所需要的電路。例如,記憶體電路202可以包含供資料儲存之一或多個記憶體儲存陣列222、供讀取及寫入記憶體儲存陣列222之位址控制邏輯224、以及解碼器226。
依據所揭示晶片之一特色,晶片選擇控制206可被用以將晶片110擇一指定成一主控晶片或一從屬晶片。例如,晶片選擇控制206可以自一常設保險絲(圖中未顯示)接收一狀態輸入M,當其處於一第一狀態之時,允許晶片110執行一主控晶片之功能。反之,當該常設保險絲係處於一第二狀態之時,晶片110將僅做為一從屬晶片,此時主控電路204將被禁能。在又另一實例之中,其可以藉由晶片上儲存狀態可被改變任意多次之諸如非揮發性記憶體之一可重設組態元件,控制晶片選擇控制206之狀態。以此種方式,晶片110之指定可被從一從屬晶片改變成一主控晶片,或者反過來被從一主控晶片改變成一從屬晶片,且可改變任意多次,包含在晶片110已被安裝並使用於一電子裝置之後亦然。
雖然被晶片選擇控制206使用以控制一特定晶片究竟做為一主控或從屬晶片之狀態輸入M可以單獨被儲存於每一晶片110之上,但狀態輸入M亦可以被儲存於他處。例如,例示於圖1的微電子組件100之內的另一元件,例如一保險絲陣列,或者位於記憶體晶片110之外的一晶片上的非揮發性記憶體,均可以儲存微電子組件100之內的每一記憶體晶片110之對應狀態輸入M。在另一實例之中,狀態輸入M可以被儲存於一晶片上之一保險絲陣列或者非揮發性記憶體,該晶片連接至微電子組件預定連接或已連接之一系統中之一模組板卡或者例如"母板"之電路面板。
顯示於圖1之微電子組件100之晶片110可以藉由匯流排彼此連接,諸如顯示於圖2之中連接內部資料匯流排線的TSV匯流排210。此外,微電子組件100亦可以包含用以互連每一晶片110之晶片選擇控制信號、位址、及資料接頭的匯流排。
在一實施例之中,僅有微電子組件100之主控晶片可以具有一個與基板120之致能連接。例如,若圖2之晶片110a被專用做為一主控晶片,則晶片110a可以是有作用地將其主控電路204連接至基板120的唯一晶片。以此種方式,位於通往基板120的高頻接頭上的寄生負載得以降低。在微電子組件100內之任何單一晶片110a-d可以被指定成一主控晶片的一個例子當中,其資料接頭中的每一者均可以耦接至一外部匯流排以供驅動資料至基板120。例如,圖2之TSV匯流排260可以將晶片110a連接至圖1所示之基板120。
在此實施例之中,微電子組件100之中已被指定為從屬晶片之晶片110可以利用各別的內部資料匯流排禁能其主控電路204,此外,並且可以將其主控電路204設成一個相對於TSV匯流排260之非作用模式。例如,一從屬晶片110可以從TSV匯流排260藉由進入一高阻抗模式而禁能其主控電路204,其中一高阻抗被施用於介於主控電路204與TSV匯流排260之間的連接。或者,一從屬晶片110可以進入一輸出終端模式,舉例而言,其中一終端阻抗被主控電路204施加於輸入-輸出介面214。以此種方式,僅有主控晶片會驅動來自微電子組件100的作用資料。
在一實施例之中,位於一系統之內的單一元件或晶片可以將一特別微電子組件100之內,或者複數微電子組件之內,的每一晶片擇一
指定成一主控晶片或從屬晶片。
若晶片選擇控制206之組態被設定成使得晶片110做為一主控晶片,則一群開關電路將對應的一組內部資料信號線及TSV匯流排的資料信號線與主控電路204連接。在圖3所描繪的實例之中,當Ck在相對於微電子組件100之一晶片110之一讀取或寫入操作期間被致能之時,一群128個開關電路208將對應的一群128條內部資料信號線Di(127:0)及128條TSV匯流排210之信號線與主控電路204連接。反之,當晶片選擇控制206被禁能而使得晶片110之組態被設定成一從屬晶片之時,開關電路208將使得對應的該群128條資料信號線Di(127:0)及TSV匯流排210的128條信號線自主控電路204斷離。
圖3例示晶片110a內之開關電路206之一實施例。如先前於圖1之中所示,晶片110a可以是一微電子組件的一部分,該微電子組件包含藉由TSV 116電性互連之複數垂直堆疊之晶片110a-d。此等晶片的其中一者可以被指定為一主控晶片。依據圖3之功能示意圖,當晶片110a未被指定成主控晶片之時,每一開關304將一特別晶片i之一資料信號Di(127:0)自包含晶片110a之I/O串行器/解串器212斷離。
晶片選擇控制206之輸出,例示性地顯示為圖3中之"及閘"306,控制開關304。具體而言,開關304將會維持禁能直到晶片選擇控制206致能開關304為止,此使得特別資料線Di連接SerDes電路212。通往晶片選擇控制206之二輸入被標記成"Ck"及"M"。當任何讀取或寫入指令被送達堆疊中的任何晶片110a-d之時,Ck輸入將被致能於,例如,一高電壓處。如前所述,邏輯閘306之M輸入將被禁能於,例如,一低電壓處,除非晶
片110a已被指定成一主控晶片。因此,對於任何讀取或寫入指令,開關304均將無法被致能,除非晶片110a已被指定成一主控晶片。
針對送達堆疊中之任何晶片110a-d之任何讀取或寫入指令,開關302之Ck輸入將致能(導通)開關302。在一特別的實例之中,該讀取或寫入指令接著可以傳播至開關308a-d。開關308a-d各自受一輸入Ckij所控制,其中"j"可以代表晶片"i"之內讀取或寫入指令可以定址到的的不同記憶庫(memory bank)。例如,僅有在讀取或寫入指令被定址到晶片"i"的記憶庫"0"之時,開關308a才會致能,且從而將TSV匯流排之一資料線連接到一晶片中對應之一總體性資料線。以此種方式,讀取/寫入指令可以傳播至適當晶片中的正確記憶庫。雖然其例示四個開關308a-d,但其應理解,晶片110a可以包含較少或較多的開關308,取決於晶片110a之內所存在的記憶庫數目。
圖2之晶片選擇控制之一選替性實施例506顯示於圖4。在此實施例之中,開關302係由邏輯"或閘"402之輸出"Cko"所控制。邏輯閘402之輸入係邏輯"及閘"306與406之輸出。如前配合圖3所述,當任何讀取或寫入指令有作用之時,"Ck"將被致能,無論指令定址到哪一個晶片皆然。相形之下,邏輯閘406之輸入"Cki"僅在有讀取或寫入指令定址到所選晶片"i"之內的其中一個記憶庫之時被致能。若晶片110a被指定為主控晶片,則邏輯閘306之輸入"M"將被致能,而若晶片110a被指定為一從屬晶片,則邏輯閘406之輸入"S"被致能。因此,若晶片110a被指定為一主控晶片,則當任何讀取或寫入指令定址到微電子組件100中的任何晶片之時,邏輯閘402之輸出"Cko"將致能開關302。然而,當晶片110a被指定為一從屬晶片之時,
輸出Cko將僅在讀取或寫入指令定址到晶片110a時致能開關302。以此種方式,相較於圖3所示之實施例,TSV上來自資料線的負載被降低,其中在圖3所示實施例之中,每當一讀取或寫入指令生效時,所有晶片上的所有資料線Di均具有一從開關308通往TSV匯流排之連接。
為求簡明起見,圖4僅顯示一個開關308,然而,如同圖3之開關308a-d,圖4之晶片110a具有的開關308之數量可以與晶片110a內所包含的記憶庫所需要的一樣多。唯有當輸入"Ckij"指出讀取或寫入指令被定址到晶片"i"的記憶庫"j"之時,開關308會關合,並將微電子組件中之一特別從屬晶片之一內部資料線連接至TSV匯流排中之一對應資料線。
圖1中之晶片110a-d全部均可以包含圖2所示之功能區塊。因此,微電子組件100無須包含一個內含與其他晶片不同功能區塊的特製主控晶片,因為每一晶片110a-d均可以在任何特定時間點被指定成主控晶片。例如,其可以藉由將晶片110a之晶片選擇電路206之組態設成一個表示主控晶片之狀態以先將晶片110a指定成主控晶片。若其主控電路204發生問題,舉例而言,則晶片110a可以被從一主控晶片改變成一從屬晶片,而晶片110b則被從一從屬晶片改變成主控晶片。因此,晶片110a將斷離其本身之內部資料線以及其本身從主控電路204,例如晶片110a上的SerDes電路212,通往TSV匯流排之連接。晶片110b之主控電路204將被連接至堆疊組件之資料線及TSV匯流排。
圖3及圖4之中所示之開關並未限於一特別之構造,因為能夠在二節點之間執行致能及禁能連接功能的任何結構均可以使用。舉例而言,雖然顯示於圖3及圖4中的晶片110可以包含NMOS、PMOS、或CMOS
開關,但晶片110並不限於此等特別結構。
若晶片110a-b之晶片選擇電路206包含一常設保險絲,則其可以藉由施加一雷射或電氣信號至該常設保險絲而變換該常設保險絲之狀態。例如,其可以施加一雷射光至一晶片110之常設保險絲,以將晶片110從一從屬晶片改變成一主控晶片,或者從一主控晶片改變成一從屬晶片。
雖然圖1顯示晶片110a-d之組態被透過TSV設定於一具有電性連接的微電子組件100之中,但晶片110a-d可以被配置於適合該等預定由晶片110a-d執行之功能的任何組態之中。或者,顯示於圖2之晶片110a可以充當單一半導體晶片。此外,在前述的任一實施例之中,該等半導體晶片可以是實施於任何適當之記憶體技術之中,並不限於DRAM或者任何有關DRAM之特定標準。
本發明前述實施例之各種特徵均可以在未脫離本發明之範疇或精神下以不同於具體描述於上的方式結合。本揭示預計涵蓋本發明前述實施例之所有此等組合及變異。
100‧‧‧微電子組件
110a-d‧‧‧半導體晶片
112‧‧‧導電接觸
114‧‧‧導電接合材料
116‧‧‧矽通孔
120‧‧‧基板
Claims (16)
- 一種半導體晶片,包含:複數資料線,可連接至一晶片外資料匯流排,以供在該半導體晶片與至少一其他半導體晶片之間傳送資料信號;一晶片選擇控制,用以將該半導體晶片指定成一主控晶片或者一從屬晶片;以及主控晶片電路,被組構成用以在其中該晶片選擇控制將該半導體晶片指定成一主控晶片之一狀態中執行做為一主控晶片之操作,該主控晶片電路包含用以在位於該等資料線上或位於該資料匯流排上之一第一格式之第一資料信號與位於該半導體晶片之一外部資料輸入-輸出介面上之一第二格式之第二資料信號之間進行轉換之電路,該半導體晶片進一步包含:控制邏輯,其耦接以接收該晶片選擇控制的一位址和一輸出;以及一組開關,其耦接在該資料匯流排和此晶片的該些資料線之間,且經配置以在該晶片選擇控制指定該半導體晶片為一主控晶片的狀態下,使得信號能在該資料匯流排和該些資料線之間傳送,以及當該晶片選擇控制指定該半導體晶片為一從屬晶片時,僅在所接收的該位址定義在該半導體晶片內的位址之時,使得信號能在該資料匯流排和該半導體晶片的該些資料線之間傳送。
- 如申請專利範圍第1項之半導體晶片,其中該主控晶片電路包含一串行器/解串器(SerDes),被組構成用以在該第一資料信號與第二資料信號之間進行轉換,該第二資料信號被串行化自該第一資料信號,而該第一資料信號被解串化自該第二資料信號。
- 如申請專利範圍第1項之半導體晶片,其中該半導體晶片係一DRAM晶片。
- 如申請專利範圍第1項之半導體晶片,其中該晶片外資料匯流排係一直通矽通孔(TSV)匯流排。
- 如申請專利範圍第1項之半導體晶片,其中該晶片另包含具有至少二狀態之一保險絲,且其中該晶片選擇控制被組構成用以依據該保險絲之該至少二狀態被致能或禁能。
- 如申請專利範圍第1項之半導體晶片,其中該保險絲之一狀態被組構成藉由電氣信號或雷射光於該至少二狀態之間變換。
- 如申請專利範圍第1項之半導體晶片,其中該晶片選擇控制之組態能夠依據來自一微控制器之一信號加以設定。
- 如申請專利範圍第1項之半導體晶片,其中該外部輸入-輸出介面連接至不同於該資料匯流排之一輸入-輸出匯流排。
- 如申請專利範圍第8項之半導體晶片,其中當該半導體晶片被指定成一從屬晶片之時,該輸入-輸出介面被設成一高阻抗。
- 如申請專利範圍第8項之半導體晶片,其中當該半導體晶片被指定成一從屬晶片之時,一終端阻抗被施加於該輸入-輸出介面。
- 一種微電子組件,包含:複數半導體晶片,直接透過一資料匯流排彼此電性互連,每一半導體晶片之組態均可被擇一設定成一主控晶片或一從屬晶片,每一晶片均具有:一晶片選擇控制,具有一第一狀態與一第二狀態,其中,當該複數半導體晶片中之一第一晶片之該晶片選擇控制係處於該第一 狀態之時,該第一晶片被組構成用以執行主控晶片操作,並且當該第一晶片之該晶片選擇控制係處於該第二狀態之時,該第一晶片未被組構成用以執行主控晶片操作,該主控晶片操作包含在位於該資料匯流排上之一第一格式之第一資料信號與位於該第一晶片之一外部資料輸入-輸出介面上之一第二格式之第二資料信號之間進行轉換,以及該複數半導體晶片中的每個半導體晶片具有:控制邏輯,其耦接以接收此晶片的該晶片選擇控制的一位址和一輸出;以及一組開關,其耦接在該資料匯流排和此晶片的資料線之間,且經配置以在此晶片的該晶片選擇控制是在該第一狀態且所接收的該位址定義在該複數半導體晶片的任一者內的位址之狀態下,使得信號能在該資料匯流排和此晶片的該些資料線之間傳送,以及當此晶片的該晶片選擇控制是在該第二狀態之時,僅在所接收的該位址定義在此晶片內的位址之時,使得信號能在該資料匯流排和此晶片的該些資料線之間傳送。
- 如申請專利範圍第11項之微電子組件,其中該晶片選擇控制之狀態係由一保險絲控制。
- 如申請專利範圍第11項之微電子組件,其中在該第一晶片的該晶片選擇控制自該第二狀態轉移至該第一狀態之時,該複數半導體晶片中之一第二晶片即停止執行主控晶片操作。
- 如申請專利範圍第11項之微電子組件,其中該晶片選擇控制之組態被設定成用以接收來自一微控制器之一狀態控制信號。
- 如申請專利範圍第11項之微電子組件,其中該主控晶片電路包含 一串行器/解串器(SerDes),被組構成用以在該第一資料信號與第二資料信號之間進行轉換,該第二資料信號被串行化自該第一資料信號,而該第一資料信號被自解串化該第二資料信號。
- 如申請專利範圍第11項之微電子組件,其中,在該第一晶片的該晶片選擇控制自該第一狀態轉移至該第二狀態之時,該第一晶片即停止發送信號至該第一晶片中負責執行主控晶片操作的部分。
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JP5650984B2 (ja) * | 2010-10-29 | 2015-01-07 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
KR102252786B1 (ko) * | 2014-09-24 | 2021-05-17 | 에스케이하이닉스 주식회사 | 멀티 칩 패키지 |
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KR102416942B1 (ko) * | 2017-11-13 | 2022-07-07 | 에스케이하이닉스 주식회사 | 적층 반도체 장치 및 반도체 시스템 |
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US11868252B2 (en) * | 2019-12-06 | 2024-01-09 | Micron Technology, Inc. | Memory with post-packaging master die selection |
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