JP5864180B2 - 半導体パッケージ及びその製造方法 - Google Patents

半導体パッケージ及びその製造方法 Download PDF

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Publication number
JP5864180B2
JP5864180B2 JP2011206550A JP2011206550A JP5864180B2 JP 5864180 B2 JP5864180 B2 JP 5864180B2 JP 2011206550 A JP2011206550 A JP 2011206550A JP 2011206550 A JP2011206550 A JP 2011206550A JP 5864180 B2 JP5864180 B2 JP 5864180B2
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Prior art keywords
insulating layer
wiring
semiconductor chip
layer
sealing insulating
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Japanese (ja)
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JP2013069808A5 (enExample
JP2013069808A (ja
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健太 内山
健太 内山
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011206550A priority Critical patent/JP5864180B2/ja
Priority to US13/604,912 priority patent/US9041211B2/en
Publication of JP2013069808A publication Critical patent/JP2013069808A/ja
Publication of JP2013069808A5 publication Critical patent/JP2013069808A5/ja
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
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    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
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    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
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    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
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    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
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    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
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    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
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    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
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    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
JP2011206550A 2011-09-21 2011-09-21 半導体パッケージ及びその製造方法 Active JP5864180B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011206550A JP5864180B2 (ja) 2011-09-21 2011-09-21 半導体パッケージ及びその製造方法
US13/604,912 US9041211B2 (en) 2011-09-21 2012-09-06 Semiconductor package and method for manufacturing the semiconductor package embedded with semiconductor chip

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Application Number Priority Date Filing Date Title
JP2011206550A JP5864180B2 (ja) 2011-09-21 2011-09-21 半導体パッケージ及びその製造方法

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JP2013069808A JP2013069808A (ja) 2013-04-18
JP2013069808A5 JP2013069808A5 (enExample) 2014-09-04
JP5864180B2 true JP5864180B2 (ja) 2016-02-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11373955B2 (en) 2020-02-25 2022-06-28 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the semiconductor package

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11049845B2 (en) * 2012-09-14 2021-06-29 Longitude Licensing Limited Semiconductor device having wires connecting connection pads
KR101999114B1 (ko) * 2013-06-03 2019-07-11 에스케이하이닉스 주식회사 반도체 패키지
KR102161173B1 (ko) * 2013-08-29 2020-09-29 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US9443758B2 (en) * 2013-12-11 2016-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Connecting techniques for stacked CMOS devices
TWI517343B (zh) * 2014-03-25 2016-01-11 恆勁科技股份有限公司 覆晶堆疊封裝結構及其製作方法
JP6388202B2 (ja) * 2014-08-07 2018-09-12 パナソニックＩｐマネジメント株式会社 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ
JP2016048768A (ja) * 2014-08-28 2016-04-07 日立化成株式会社 配線板及び半導体装置の製造方法
KR20160047424A (ko) 2014-09-26 2016-05-02 인텔 코포레이션 와이어-접합 멀티-다이 스택을 구비한 집적 회로 패키지
US10325853B2 (en) 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
JP6620989B2 (ja) * 2015-05-25 2019-12-18 パナソニックＩｐマネジメント株式会社 電子部品パッケージ
JP6922887B2 (ja) * 2016-03-01 2021-08-18 ソニーグループ株式会社 半導体装置、電子モジュール、電子機器、および半導体装置の製造方法
JP6771308B2 (ja) * 2016-05-02 2020-10-21 三菱電機株式会社 回路基板および半導体集積回路の実装構造
US9818729B1 (en) * 2016-06-16 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure and method
US10840180B2 (en) 2016-10-06 2020-11-17 Mitsui Mining & Smelting Co., Ltd. Production method for multilayer wiring board
KR102179799B1 (ko) 2016-10-06 2020-11-17 미쓰이금속광업주식회사 다층 배선판의 제조 방법
JP7112962B2 (ja) * 2016-11-28 2022-08-04 三井金属鉱業株式会社 多層配線板の製造方法
CN110114870B (zh) * 2016-12-28 2023-07-21 株式会社村田制作所 电路模块
CN108695265A (zh) * 2017-04-11 2018-10-23 财团法人工业技术研究院 芯片封装结构及其制造方法
US11139262B2 (en) * 2019-02-07 2021-10-05 Micron Technology, Inc. Use of pre-channeled materials for anisotropic conductors
CN113518718A (zh) * 2019-03-08 2021-10-19 H.B.富乐公司 用于封装电子部件的系统和方法
US11398408B2 (en) * 2019-09-24 2022-07-26 Advanced Semiconductor Engineering, Inc. Semiconductor substrate with trace connected to via at a level within a dielectric layer
KR20220008168A (ko) 2020-07-13 2022-01-20 삼성전자주식회사 반도체 패키지
CN112103193B (zh) 2020-08-21 2021-12-03 珠海越亚半导体股份有限公司 一种嵌埋结构及制备方法、基板
US11854964B2 (en) * 2021-08-27 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of semiconductor device with conductive bumps
JP7669236B2 (ja) * 2021-09-03 2025-04-28 富士フイルム株式会社 半導体実装構造体
TWI848848B (zh) * 2023-11-08 2024-07-11 同欣電子工業股份有限公司 減少基板於構裝製程發生翹曲的方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100533673B1 (ko) 1999-09-03 2005-12-05 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조 방법, 회로 기판 및 전자 기기
JP2007150346A (ja) 1999-09-03 2007-06-14 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
JP2002134653A (ja) * 2000-10-23 2002-05-10 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法
US6680529B2 (en) * 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
JP2006222164A (ja) * 2005-02-08 2006-08-24 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
KR100813625B1 (ko) * 2006-11-15 2008-03-14 삼성전자주식회사 반도체 소자 패키지
JP5496445B2 (ja) 2007-06-08 2014-05-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2009260165A (ja) * 2008-04-21 2009-11-05 Casio Comput Co Ltd 半導体装置
JP2009289862A (ja) * 2008-05-28 2009-12-10 Casio Comput Co Ltd 半導体装置
JP5147755B2 (ja) 2009-02-20 2013-02-20 新光電気工業株式会社 半導体装置及びその製造方法
TWI501376B (zh) * 2009-10-07 2015-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
JP5715334B2 (ja) * 2009-10-15 2015-05-07 ルネサスエレクトロニクス株式会社 半導体装置
JP5460388B2 (ja) * 2010-03-10 2014-04-02 新光電気工業株式会社 半導体装置及びその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11373955B2 (en) 2020-02-25 2022-06-28 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the semiconductor package
US11810864B2 (en) 2020-02-25 2023-11-07 Samsung Electronics Co., Ltd. Semiconductor package

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