JP2013069808A5 - - Google Patents
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- Publication number
- JP2013069808A5 JP2013069808A5 JP2011206550A JP2011206550A JP2013069808A5 JP 2013069808 A5 JP2013069808 A5 JP 2013069808A5 JP 2011206550 A JP2011206550 A JP 2011206550A JP 2011206550 A JP2011206550 A JP 2011206550A JP 2013069808 A5 JP2013069808 A5 JP 2013069808A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- semiconductor chip
- sealing insulating
- support
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000007789 sealing Methods 0.000 claims description 24
- 238000010030 laminating Methods 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910010272 inorganic material Inorganic materials 0.000 claims 1
- 239000011147 inorganic material Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011206550A JP5864180B2 (ja) | 2011-09-21 | 2011-09-21 | 半導体パッケージ及びその製造方法 |
| US13/604,912 US9041211B2 (en) | 2011-09-21 | 2012-09-06 | Semiconductor package and method for manufacturing the semiconductor package embedded with semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011206550A JP5864180B2 (ja) | 2011-09-21 | 2011-09-21 | 半導体パッケージ及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013069808A JP2013069808A (ja) | 2013-04-18 |
| JP2013069808A5 true JP2013069808A5 (enExample) | 2014-09-04 |
| JP5864180B2 JP5864180B2 (ja) | 2016-02-17 |
Family
ID=47879920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011206550A Active JP5864180B2 (ja) | 2011-09-21 | 2011-09-21 | 半導体パッケージ及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9041211B2 (enExample) |
| JP (1) | JP5864180B2 (enExample) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112013004495T5 (de) * | 2012-09-14 | 2015-06-11 | Ps5 Luxco S.A.R.L. | Halbleiterbauelement und Verfahren zum Herstellen eines Halbleiterbauelements |
| KR101999114B1 (ko) * | 2013-06-03 | 2019-07-11 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
| KR102161173B1 (ko) * | 2013-08-29 | 2020-09-29 | 삼성전자주식회사 | 패키지 온 패키지 장치 및 이의 제조 방법 |
| US9443758B2 (en) | 2013-12-11 | 2016-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Connecting techniques for stacked CMOS devices |
| TWI517343B (zh) * | 2014-03-25 | 2016-01-11 | 恆勁科技股份有限公司 | 覆晶堆疊封裝結構及其製作方法 |
| JP6388202B2 (ja) * | 2014-08-07 | 2018-09-12 | パナソニックIpマネジメント株式会社 | 絶縁樹脂シート、並びにそれを用いた回路基板および半導体パッケージ |
| JP2016048768A (ja) * | 2014-08-28 | 2016-04-07 | 日立化成株式会社 | 配線板及び半導体装置の製造方法 |
| RU2663688C1 (ru) | 2014-09-26 | 2018-08-08 | Интел Корпорейшн | Корпусированная интегральная схема, содержащая соединенный проволочными перемычками многокристальный пакет |
| US10325853B2 (en) | 2014-12-03 | 2019-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor packages having through package vias |
| JP6620989B2 (ja) * | 2015-05-25 | 2019-12-18 | パナソニックIpマネジメント株式会社 | 電子部品パッケージ |
| DE112017001101T5 (de) * | 2016-03-01 | 2018-11-29 | Sony Corporation | Halbleitervorrichtung, elektronisches Modul, elektronische Einrichtung und Herstellungsverfahren für eine Halbleitervorrichtung |
| JP6771308B2 (ja) * | 2016-05-02 | 2020-10-21 | 三菱電機株式会社 | 回路基板および半導体集積回路の実装構造 |
| US9818729B1 (en) * | 2016-06-16 | 2017-11-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure and method |
| US10840180B2 (en) | 2016-10-06 | 2020-11-17 | Mitsui Mining & Smelting Co., Ltd. | Production method for multilayer wiring board |
| CN109716871B (zh) * | 2016-10-06 | 2023-02-17 | 三井金属矿业株式会社 | 多层布线板的制造方法 |
| CN116709672A (zh) | 2016-11-28 | 2023-09-05 | 三井金属矿业株式会社 | 多层布线板的制造方法 |
| JP6780710B2 (ja) * | 2016-12-28 | 2020-11-04 | 株式会社村田製作所 | 回路モジュール |
| CN108695265A (zh) * | 2017-04-11 | 2018-10-23 | 财团法人工业技术研究院 | 芯片封装结构及其制造方法 |
| US11139262B2 (en) * | 2019-02-07 | 2021-10-05 | Micron Technology, Inc. | Use of pre-channeled materials for anisotropic conductors |
| EP3934913B1 (en) * | 2019-03-08 | 2024-09-11 | H.B. Fuller Company | Systems and methods for encapsulating an electronic component |
| US11398408B2 (en) * | 2019-09-24 | 2022-07-26 | Advanced Semiconductor Engineering, Inc. | Semiconductor substrate with trace connected to via at a level within a dielectric layer |
| KR102765266B1 (ko) | 2020-02-25 | 2025-02-07 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
| KR20220008168A (ko) | 2020-07-13 | 2022-01-20 | 삼성전자주식회사 | 반도체 패키지 |
| CN112103193B (zh) * | 2020-08-21 | 2021-12-03 | 珠海越亚半导体股份有限公司 | 一种嵌埋结构及制备方法、基板 |
| JP7669236B2 (ja) * | 2021-09-03 | 2025-04-28 | 富士フイルム株式会社 | 半導体実装構造体 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001018864A1 (en) | 1999-09-03 | 2001-03-15 | Seiko Epson Corporation | Semiconductor device, method of manufacture thereof, circuit board, and electronic device |
| JP2007150346A (ja) | 1999-09-03 | 2007-06-14 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
| US6271469B1 (en) * | 1999-11-12 | 2001-08-07 | Intel Corporation | Direct build-up layer on an encapsulated die package |
| JP2002134653A (ja) * | 2000-10-23 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 半導体装置とその製造方法 |
| US6680529B2 (en) * | 2002-02-15 | 2004-01-20 | Advanced Semiconductor Engineering, Inc. | Semiconductor build-up package |
| JP2006222164A (ja) * | 2005-02-08 | 2006-08-24 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| KR100813625B1 (ko) * | 2006-11-15 | 2008-03-14 | 삼성전자주식회사 | 반도체 소자 패키지 |
| JP5496445B2 (ja) | 2007-06-08 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2009260165A (ja) * | 2008-04-21 | 2009-11-05 | Casio Comput Co Ltd | 半導体装置 |
| JP2009289862A (ja) * | 2008-05-28 | 2009-12-10 | Casio Comput Co Ltd | 半導体装置 |
| JP5147755B2 (ja) * | 2009-02-20 | 2013-02-20 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
| TWI501376B (zh) * | 2009-10-07 | 2015-09-21 | 精材科技股份有限公司 | 晶片封裝體及其製造方法 |
| JP5715334B2 (ja) * | 2009-10-15 | 2015-05-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP5460388B2 (ja) * | 2010-03-10 | 2014-04-02 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
-
2011
- 2011-09-21 JP JP2011206550A patent/JP5864180B2/ja active Active
-
2012
- 2012-09-06 US US13/604,912 patent/US9041211B2/en active Active
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