JP5846185B2 - 貫通電極基板及び貫通電極基板を用いた半導体装置 - Google Patents

貫通電極基板及び貫通電極基板を用いた半導体装置 Download PDF

Info

Publication number
JP5846185B2
JP5846185B2 JP2013241392A JP2013241392A JP5846185B2 JP 5846185 B2 JP5846185 B2 JP 5846185B2 JP 2013241392 A JP2013241392 A JP 2013241392A JP 2013241392 A JP2013241392 A JP 2013241392A JP 5846185 B2 JP5846185 B2 JP 5846185B2
Authority
JP
Japan
Prior art keywords
opening
hole
electrode substrate
filler
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013241392A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015103586A5 (OSRAM
JP2015103586A (ja
Inventor
倉持　悟
悟 倉持
小岩　進雄
進雄 小岩
英範 吉岡
英範 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2013241392A priority Critical patent/JP5846185B2/ja
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to CN201480061865.7A priority patent/CN105765712B/zh
Priority to EP20163801.2A priority patent/EP3690933B1/en
Priority to EP14864041.0A priority patent/EP3073523B1/en
Priority to CN201811135601.8A priority patent/CN109616459A/zh
Priority to EP22185677.6A priority patent/EP4095895A3/en
Priority to PCT/JP2014/080649 priority patent/WO2015076301A1/ja
Priority to CN201811131924.XA priority patent/CN109616458B/zh
Publication of JP2015103586A publication Critical patent/JP2015103586A/ja
Publication of JP2015103586A5 publication Critical patent/JP2015103586A5/ja
Application granted granted Critical
Publication of JP5846185B2 publication Critical patent/JP5846185B2/ja
Priority to US15/159,323 priority patent/US10256176B2/en
Priority to US16/266,203 priority patent/US10580727B2/en
Priority to US16/743,145 priority patent/US10790221B2/en
Priority to US16/936,519 priority patent/US11362028B2/en
Priority to US17/725,627 priority patent/US12080637B2/en
Priority to US18/800,278 priority patent/US20240404934A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
    • H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09154—Bevelled, chamferred or tapered edge
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09581—Applying an insulating coating on the walls of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09854—Hole or via having special cross-section, e.g. elliptical
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0594—Insulating resist or coating with special shaped edges
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/879—Bump connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/725—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a laterally-adjacent insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photovoltaic Devices (AREA)
JP2013241392A 2013-11-21 2013-11-21 貫通電極基板及び貫通電極基板を用いた半導体装置 Active JP5846185B2 (ja)

Priority Applications (14)

Application Number Priority Date Filing Date Title
JP2013241392A JP5846185B2 (ja) 2013-11-21 2013-11-21 貫通電極基板及び貫通電極基板を用いた半導体装置
EP20163801.2A EP3690933B1 (en) 2013-11-21 2014-11-19 Through electrode substrate
EP14864041.0A EP3073523B1 (en) 2013-11-21 2014-11-19 Through electrode substrate and semiconductor device using through electrode substrate
CN201811135601.8A CN109616459A (zh) 2013-11-21 2014-11-19 贯通电极基板及利用贯通电极基板的半导体装置
CN201480061865.7A CN105765712B (zh) 2013-11-21 2014-11-19 贯通电极基板及利用贯通电极基板的半导体装置
EP22185677.6A EP4095895A3 (en) 2013-11-21 2014-11-19 Through electrode substrate and semiconductor device using through electrode substrate
PCT/JP2014/080649 WO2015076301A1 (ja) 2013-11-21 2014-11-19 貫通電極基板及び貫通電極基板を用いた半導体装置
CN201811131924.XA CN109616458B (zh) 2013-11-21 2014-11-19 贯通电极基板及利用贯通电极基板的半导体装置
US15/159,323 US10256176B2 (en) 2013-11-21 2016-05-19 Through-hole electrode substrate and semiconductor device using through-hole electrode substrate
US16/266,203 US10580727B2 (en) 2013-11-21 2019-02-04 Through-hole electrode substrate
US16/743,145 US10790221B2 (en) 2013-11-21 2020-01-15 Through-hole electrode substrate
US16/936,519 US11362028B2 (en) 2013-11-21 2020-07-23 Through-hole electrode substrate
US17/725,627 US12080637B2 (en) 2013-11-21 2022-04-21 Through-hole electrode substrate
US18/800,278 US20240404934A1 (en) 2013-11-21 2024-08-12 Through-hole electrode substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013241392A JP5846185B2 (ja) 2013-11-21 2013-11-21 貫通電極基板及び貫通電極基板を用いた半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2015227286A Division JP6044697B2 (ja) 2015-11-20 2015-11-20 貫通電極基板及び貫通電極基板を用いた半導体装置

Publications (3)

Publication Number Publication Date
JP2015103586A JP2015103586A (ja) 2015-06-04
JP2015103586A5 JP2015103586A5 (OSRAM) 2015-08-20
JP5846185B2 true JP5846185B2 (ja) 2016-01-20

Family

ID=53179561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013241392A Active JP5846185B2 (ja) 2013-11-21 2013-11-21 貫通電極基板及び貫通電極基板を用いた半導体装置

Country Status (5)

Country Link
US (6) US10256176B2 (OSRAM)
EP (3) EP3073523B1 (OSRAM)
JP (1) JP5846185B2 (OSRAM)
CN (3) CN105765712B (OSRAM)
WO (1) WO2015076301A1 (OSRAM)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5846185B2 (ja) 2013-11-21 2016-01-20 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
CN107027238B (zh) * 2016-01-29 2020-08-18 奥特斯(中国)有限公司 包括铜填充多径激光钻孔的元件载体
JP2017136711A (ja) 2016-02-02 2017-08-10 セイコーエプソン株式会社 配線基板、ｍｅｍｓデバイス、液体噴射ヘッド及び液体噴射装置
US9847477B2 (en) * 2016-04-12 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a bottom electrode of a magnetoresistive random access memory cell
JP6323768B1 (ja) 2016-06-03 2018-05-16 大日本印刷株式会社 貫通電極基板及びその製造方法、並びに実装基板
JP6341245B2 (ja) 2016-09-05 2018-06-13 大日本印刷株式会社 貫通電極基板の製造方法、貫通電極基板および半導体装置
US11078112B2 (en) * 2017-05-25 2021-08-03 Corning Incorporated Silica-containing substrates with vias having an axially variable sidewall taper and methods for forming the same
JP6809511B2 (ja) * 2018-07-06 2021-01-06 大日本印刷株式会社 貫通電極基板および半導体装置
JP7433318B2 (ja) * 2019-03-07 2024-02-19 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
KR102652986B1 (ko) 2019-03-07 2024-03-28 앱솔릭스 인코포레이티드 패키징 기판 및 이를 포함하는 반도체 장치
JP7254930B2 (ja) 2019-03-12 2023-04-10 アブソリックス インコーポレイテッド パッケージング基板及びこれを含む半導体装置
US11981501B2 (en) 2019-03-12 2024-05-14 Absolics Inc. Loading cassette for substrate including glass and substrate loading method to which same is applied
EP3913662A4 (en) 2019-03-12 2022-11-02 Absolics Inc. PACKAGING SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
WO2021157496A1 (ja) * 2020-02-07 2021-08-12 ソニーグループ株式会社 表示装置
CN111199948B (zh) * 2020-03-04 2024-11-26 日月光半导体(上海)有限公司 封装基板及其制造方法
TWI752707B (zh) * 2020-11-03 2022-01-11 財團法人工業技術研究院 具有通孔的基板及其製造方法
JP7088271B2 (ja) * 2020-12-02 2022-06-21 大日本印刷株式会社 貫通電極基板および半導体装置
JP7239045B2 (ja) * 2020-12-02 2023-03-14 大日本印刷株式会社 貫通電極基板および半導体装置
WO2024010694A1 (en) * 2022-07-07 2024-01-11 Corning Incorporated Vias including an unsymmetric tapered through-hole, devices including the vias, and methods for fabricating the vias
JP2025018626A (ja) * 2023-07-27 2025-02-06 京セラ株式会社 配線基板およびそれを用いた実装構造体
WO2025121374A1 (ja) * 2023-12-05 2025-06-12 大日本印刷株式会社 貫通電極基板及び貫通電極基板の製造方法

Family Cites Families (61)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4835141B1 (OSRAM) 1970-09-14 1973-10-26
JPS5119623B2 (OSRAM) 1972-03-15 1976-06-18
JPH04154187A (ja) * 1990-10-18 1992-05-27 Mitsubishi Materials Corp スルーホール配線板の構造及びその製造方法
JP2976955B2 (ja) 1997-12-19 1999-11-10 日本電気株式会社 半導体装置の製造方法
US6876554B1 (en) * 1999-09-02 2005-04-05 Ibiden Co., Ltd. Printing wiring board and method of producing the same and capacitor to be contained in printed wiring board
SE9903995D0 (sv) 1999-11-03 1999-11-03 Astra Ab New combination
JP3789803B2 (ja) * 2001-01-30 2006-06-28 日本特殊陶業株式会社 配線基板およびその製造方法
JP2002232101A (ja) 2001-01-31 2002-08-16 Ngk Spark Plug Co Ltd 配線基板
JP4012375B2 (ja) 2001-05-31 2007-11-21 株式会社ルネサステクノロジ 配線基板およびその製造方法
US7183650B2 (en) * 2001-07-12 2007-02-27 Renesas Technology Corp. Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate
JP2003133735A (ja) * 2001-10-23 2003-05-09 Kyocera Corp 配線基板およびその製造方法ならびに電子装置
SK9132003A3 (en) 2001-12-19 2004-02-03 Astrazeneca Ab A film coating composition, a coating film, pharmaceutical formulation comprising same and a process for its production
JP4202641B2 (ja) 2001-12-26 2008-12-24 富士通株式会社 回路基板及びその製造方法
JP2003197811A (ja) * 2001-12-27 2003-07-11 Hitachi Ltd ガラス基板及びその製造方法、並びに配線基板、半導体モジュール
JP3998984B2 (ja) * 2002-01-18 2007-10-31 富士通株式会社 回路基板及びその製造方法
JP4154478B2 (ja) 2002-02-20 2008-09-24 独立行政法人産業技術総合研究所 感光性ポリイミドを用いた貫通電極形成方法
JP4022180B2 (ja) 2002-07-11 2007-12-12 大日本印刷株式会社 多層配線基板の製造方法
JP4203277B2 (ja) 2002-07-19 2008-12-24 大日本印刷株式会社 多層配線基板
JP4319831B2 (ja) 2002-12-11 2009-08-26 大日本印刷株式会社 多層配線基板の製造方法
JP2004363212A (ja) * 2003-06-03 2004-12-24 Hitachi Metals Ltd スルーホール導体を持った配線基板
JP4241202B2 (ja) 2003-06-12 2009-03-18 大日本印刷株式会社 めっきポスト型配線基板の製造方法
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
WO2005034594A1 (ja) 2003-10-06 2005-04-14 Hoya Corporation 感光性ガラス基板の貫通孔形成方法
JP4564342B2 (ja) 2004-11-24 2010-10-20 大日本印刷株式会社 多層配線基板およびその製造方法
JP4345686B2 (ja) * 2005-02-22 2009-10-14 三菱マテリアル株式会社 絶縁回路基板およびパワーモジュール
US7485967B2 (en) * 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
JP2007067216A (ja) * 2005-08-31 2007-03-15 Sanyo Electric Co Ltd 半導体装置およびその製造方法、回路基板およびその製造方法
JP4835141B2 (ja) 2005-12-13 2011-12-14 大日本印刷株式会社 多層配線基板
JP5119623B2 (ja) 2006-08-03 2013-01-16 大日本印刷株式会社 インターポーザ基板の製造方法
JP2008124398A (ja) 2006-11-15 2008-05-29 Shinko Electric Ind Co Ltd 半導体パッケージおよびその製造方法
US20080192458A1 (en) 2007-02-12 2008-08-14 Intematix Corporation Light emitting diode lighting system
JP2009023341A (ja) 2007-06-21 2009-02-05 Dainippon Printing Co Ltd 中間転写記録媒体
JP5550076B2 (ja) * 2007-07-05 2014-07-16 オー・アー・セー・マイクロテック・アクチボラゲット 低抵抗のウエハ貫通ビア
JP5536322B2 (ja) * 2007-10-09 2014-07-02 新光電気工業株式会社 基板の製造方法
JP4722904B2 (ja) 2007-12-17 2011-07-13 イビデン株式会社 多層プリント基板の製造法
JP5331350B2 (ja) * 2008-02-18 2013-10-30 日立協和エンジニアリング株式会社 配線基板
JP5583332B2 (ja) * 2008-06-06 2014-09-03 ピーエスフォー ルクスコ エスエイアールエル スルーホール配置装置およびスルーホール配置方法
US8035219B2 (en) 2008-07-18 2011-10-11 Raytheon Company Packaging semiconductors at wafer level
JP5246103B2 (ja) 2008-10-16 2013-07-24 大日本印刷株式会社 貫通電極基板の製造方法
JP5471268B2 (ja) * 2008-12-26 2014-04-16 大日本印刷株式会社 貫通電極基板及びその製造方法
JP4900508B2 (ja) * 2008-12-26 2012-03-21 大日本印刷株式会社 貫通電極基板及びその製造方法
JP2010165804A (ja) * 2009-01-14 2010-07-29 Panasonic Corp 半導体装置およびそれを用いた電子機器ならびに半導体装置の製造方法
JPWO2010087483A1 (ja) 2009-02-02 2012-08-02 旭硝子株式会社 半導体デバイス部材用ガラス基板および半導体デバイス部材用ガラス基板の製造方法
US8925192B2 (en) * 2009-06-09 2015-01-06 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US20110048775A1 (en) * 2009-08-31 2011-03-03 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
JP5697898B2 (ja) * 2009-10-09 2015-04-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置及びその製造方法
US9420707B2 (en) 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
JP5560834B2 (ja) 2010-03-29 2014-07-30 住友ベークライト株式会社 絶縁基板、絶縁基板の製造方法、プリント配線基板および半導体装置
DE102010030760B4 (de) * 2010-06-30 2014-07-24 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement mit Durchgangskontaktierungen mit einem Verspannungsrelaxationsmechanismus und Verfahren zur Herstellung eines solchen
US9107306B2 (en) * 2010-10-14 2015-08-11 Panasonic Intellectual Property Management Co., Ltd. Hybrid substrate, method for manufacturing the same, and semiconductor integrated circuit package
US8736066B2 (en) * 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US20120229990A1 (en) * 2011-03-08 2012-09-13 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing multilayer printed wiring board
US20120235969A1 (en) * 2011-03-15 2012-09-20 Qualcomm Mems Technologies, Inc. Thin film through-glass via and methods for forming same
US9485853B2 (en) * 2011-07-25 2016-11-01 Ngk Spark Plug Co., Ltd. Wiring substrate having a plurality of connection terminals and a filling member provided therebetween
US20130048355A1 (en) 2011-08-30 2013-02-28 Ibiden Co., Ltd. Printed wiring board
CN103219302B (zh) * 2012-01-19 2016-01-20 欣兴电子股份有限公司 穿孔中介板
SE537874C2 (sv) * 2012-04-13 2015-11-03 Silex Microsystems Ab CTE-anpassad interposer och metod att tillverka en sådan
JP2013229421A (ja) 2012-04-25 2013-11-07 Kyocer Slc Technologies Corp 配線基板
US8900008B2 (en) * 2012-05-25 2014-12-02 International Business Machines Corporation Universal press-fit connection for printed circuit boards
CN105374793A (zh) * 2013-05-08 2016-03-02 日月光半导体制造股份有限公司 具桥接结构的半导体封装构造及其制造方法
JP5846185B2 (ja) * 2013-11-21 2016-01-20 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置

Also Published As

Publication number Publication date
US20240404934A1 (en) 2024-12-05
US11362028B2 (en) 2022-06-14
CN105765712A (zh) 2016-07-13
EP3073523B1 (en) 2020-05-20
US20190172780A1 (en) 2019-06-06
CN105765712B (zh) 2018-10-30
EP3690933B1 (en) 2022-08-10
JP2015103586A (ja) 2015-06-04
WO2015076301A1 (ja) 2015-05-28
EP4095895A3 (en) 2023-03-01
US12080637B2 (en) 2024-09-03
US20220246512A1 (en) 2022-08-04
EP3690933A1 (en) 2020-08-05
US20200357733A1 (en) 2020-11-12
US20200152564A1 (en) 2020-05-14
US10580727B2 (en) 2020-03-03
US20160276257A1 (en) 2016-09-22
US10790221B2 (en) 2020-09-29
EP4095895A2 (en) 2022-11-30
CN109616459A (zh) 2019-04-12
US10256176B2 (en) 2019-04-09
CN109616458A (zh) 2019-04-12
EP3073523A4 (en) 2017-06-28
CN109616458B (zh) 2023-06-23
EP3073523A1 (en) 2016-09-28

Similar Documents

Publication Publication Date Title
WO2015076301A1 (ja) 貫通電極基板及び貫通電極基板を用いた半導体装置
US11791256B2 (en) Package substrate and method of fabricating the same
CN102263089B (zh) 具有多芯片结构的半导体集成电路
US20120068352A1 (en) Stacked chip assembly having vertical vias
WO2011086613A1 (ja) 半導体装置及びその製造方法
JP2025182074A (ja) 貫通電極基板
JP2010206021A (ja) 電子部品実装構造体、およびその製造方法
JP2009224617A (ja) 配線基板
JP6044697B2 (ja) 貫通電極基板及び貫通電極基板を用いた半導体装置
JP6372546B2 (ja) 貫通電極基板及び貫通電極基板を用いた半導体装置
JP6263859B2 (ja) 貫通電極基板の製造方法、貫通電極基板、および半導体装置
JP6642642B2 (ja) 貫通電極基板
JP4293563B2 (ja) 半導体装置及び半導体パッケージ
US11810863B2 (en) Sensor
JP6379786B2 (ja) 貫通電極基板、配線基板および半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150707

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150707

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20150707

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20150717

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150804

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151001

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20151027

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20151109

R150 Certificate of patent or registration of utility model

Ref document number: 5846185

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150