JP5820911B2 - チップサイズ両面接続パッケージ - Google Patents
チップサイズ両面接続パッケージ Download PDFInfo
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- JP5820911B2 JP5820911B2 JP2014141099A JP2014141099A JP5820911B2 JP 5820911 B2 JP5820911 B2 JP 5820911B2 JP 2014141099 A JP2014141099 A JP 2014141099A JP 2014141099 A JP2014141099 A JP 2014141099A JP 5820911 B2 JP5820911 B2 JP 5820911B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/14181—On opposite sides of the body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
Claims (7)
- 半導体基板上にLSI領域と電極接続領域を形成した半導体チップを、該半導体チップの上下にそれぞれ位置する第1の主面及び第2の主面にそれぞれ設けた外部接続用配線に接続して構成したチップサイズ両面接続パッケージであって、
前記電極接続領域に接続された複数のポスト電極と、
該複数のポスト電極にそれぞれ接続された複数の配線と、
これら複数のポスト電極及び配線の背面に設けた薄膜フィルムの絶縁基材テープと、
前記LSI領域と前記絶縁基材テープの間の空間を満たす樹脂封止部とを備えてなり、
前記第1の主面においては、前記複数のポスト電極にそれぞれ接続された前記複数の配線が前記外部接続用配線として用いられ、前記第2の主面においては、前記半導体基板を貫通して形成した貫通電極の先端が前記外部接続用配線として用いられ、
前記樹脂封止部を施す前に、前記絶縁基材テープが支持部に接続され、前記樹脂封止部を施した後で、前記絶縁基材テープが当該支持部から剥離される
ことを特徴とするチップサイズ両面接続パッケージ。 - 前記貫通電極は、前記半導体基板を貫通して形成した孔の中へ充填した低抵抗金属を含んでおり、前記複数のポスト電極は、前記貫通電極の上面領域に固定及び電気的に接続されていることを特徴とする請求項1に記載のチップサイズ両面接続パッケージ。
- 前記樹脂封止部が前記LSI領域に直接接触していることを特徴とする請求項1に記載のチップサイズ両面接続パッケージ。
- 前記支持部が剥離された後に残る前記絶縁基材テープが保護膜として使用されることを特徴とする請求項1に記載のチップサイズ両面接続パッケージ。
- 前記ポスト電極及び前記配線は、前記支持部の一つの面の全体に付けられた前記薄膜フィルムの絶縁基材テープの上に成長させて、配線用のポスト電極部品を形成し、次いで当該配線用のポスト電極部品が前記半導体基板と組み合わされ、次いで前記樹脂封止部が前記絶縁基材テープと前記半導体基板の表面との間に施されることを特徴とする請求項1に記載のチップサイズ両面接続パッケージ。
- 前記第2の主面側において、裏面絶縁層が前記半導体基板の表面に接触しているとともに、前記貫通電極の先端が露出しており、さらに、当該貫通電極の先端に連結された第2の主面配線を備えてなることを特徴とする請求項1に記載のチップサイズ両面接続パッケージ。
- 前記第2の主面側に、前記第2の主面配線に連結された外部電極をさらに備えてなる請求項6に記載のチップサイズ両面接続パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014141099A JP5820911B2 (ja) | 2008-05-09 | 2014-07-09 | チップサイズ両面接続パッケージ |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008123445 | 2008-05-09 | ||
JP2008123445 | 2008-05-09 | ||
JP2014141099A JP5820911B2 (ja) | 2008-05-09 | 2014-07-09 | チップサイズ両面接続パッケージ |
Related Parent Applications (1)
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JP2010511020A Division JP5688289B2 (ja) | 2008-05-09 | 2009-05-07 | チップサイズ両面接続パッケージの製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2014212341A JP2014212341A (ja) | 2014-11-13 |
JP5820911B2 true JP5820911B2 (ja) | 2015-11-24 |
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Family Applications (2)
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JP2010511020A Active JP5688289B2 (ja) | 2008-05-09 | 2009-05-07 | チップサイズ両面接続パッケージの製造方法 |
JP2014141099A Active JP5820911B2 (ja) | 2008-05-09 | 2014-07-09 | チップサイズ両面接続パッケージ |
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JP2010511020A Active JP5688289B2 (ja) | 2008-05-09 | 2009-05-07 | チップサイズ両面接続パッケージの製造方法 |
Country Status (5)
Country | Link |
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US (3) | US8557700B2 (ja) |
JP (2) | JP5688289B2 (ja) |
KR (1) | KR101195786B1 (ja) |
CN (1) | CN102017133B (ja) |
WO (1) | WO2009136495A1 (ja) |
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US8557700B2 (en) | 2013-10-15 |
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