JP5536322B2 - 基板の製造方法 - Google Patents

基板の製造方法 Download PDF

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Publication number
JP5536322B2
JP5536322B2 JP2008258309A JP2008258309A JP5536322B2 JP 5536322 B2 JP5536322 B2 JP 5536322B2 JP 2008258309 A JP2008258309 A JP 2008258309A JP 2008258309 A JP2008258309 A JP 2008258309A JP 5536322 B2 JP5536322 B2 JP 5536322B2
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Prior art keywords
silicon substrate
hole
oxide film
thermal oxide
substrate
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JP2008258309A
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English (en)
Japanese (ja)
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JP2009111367A5 (https=
JP2009111367A (ja
Inventor
裕一 田口
晶紀 白石
昌宏 春原
啓 村山
秀明 坂口
光敏 東
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2008258309A priority Critical patent/JP5536322B2/ja
Publication of JP2009111367A publication Critical patent/JP2009111367A/ja
Publication of JP2009111367A5 publication Critical patent/JP2009111367A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W78/00—Detachable holders for supporting packaged chips in operation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/127—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Micromachines (AREA)
JP2008258309A 2007-10-09 2008-10-03 基板の製造方法 Active JP5536322B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008258309A JP5536322B2 (ja) 2007-10-09 2008-10-03 基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007263224 2007-10-09
JP2007263224 2007-10-09
JP2008258309A JP5536322B2 (ja) 2007-10-09 2008-10-03 基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009111367A JP2009111367A (ja) 2009-05-21
JP2009111367A5 JP2009111367A5 (https=) 2011-08-11
JP5536322B2 true JP5536322B2 (ja) 2014-07-02

Family

ID=40351813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008258309A Active JP5536322B2 (ja) 2007-10-09 2008-10-03 基板の製造方法

Country Status (5)

Country Link
US (1) US7795140B2 (https=)
EP (1) EP2048923A3 (https=)
JP (1) JP5536322B2 (https=)
KR (1) KR20090036521A (https=)
TW (1) TW200919606A (https=)

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TWI445152B (zh) 2010-08-30 2014-07-11 日月光半導體製造股份有限公司 半導體結構及其製作方法
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
TWI434387B (zh) 2010-10-11 2014-04-11 日月光半導體製造股份有限公司 具有穿導孔之半導體裝置及具有穿導孔之半導體裝置之封裝結構及其製造方法
TW201241941A (en) * 2010-10-21 2012-10-16 Sumitomo Bakelite Co A method for manufacturing an electronic equipment, and the electronic equipment obtained by using the method, as well as a method for manufacturing electronics and electronic parts, and the electronics and the electronic parts obtained using the method
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US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
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KR101867998B1 (ko) * 2011-06-14 2018-06-15 삼성전자주식회사 패턴 형성 방법
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8742591B2 (en) 2011-12-21 2014-06-03 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief
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US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
CN103839870B (zh) * 2012-11-20 2016-08-17 中微半导体设备(上海)有限公司 用于tsv刻蚀中改善硅通孔侧壁粗糙度的方法
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
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Also Published As

Publication number Publication date
EP2048923A2 (en) 2009-04-15
EP2048923A3 (en) 2010-12-08
TW200919606A (en) 2009-05-01
KR20090036521A (ko) 2009-04-14
US20090093117A1 (en) 2009-04-09
JP2009111367A (ja) 2009-05-21
US7795140B2 (en) 2010-09-14

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