JP5536322B2 - 基板の製造方法 - Google Patents

基板の製造方法 Download PDF

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Publication number
JP5536322B2
JP5536322B2 JP2008258309A JP2008258309A JP5536322B2 JP 5536322 B2 JP5536322 B2 JP 5536322B2 JP 2008258309 A JP2008258309 A JP 2008258309A JP 2008258309 A JP2008258309 A JP 2008258309A JP 5536322 B2 JP5536322 B2 JP 5536322B2
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Japan
Prior art keywords
silicon substrate
hole
oxide film
thermal oxide
substrate
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JP2008258309A
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English (en)
Japanese (ja)
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JP2009111367A5 (enExample
JP2009111367A (ja
Inventor
裕一 田口
晶紀 白石
昌宏 春原
啓 村山
秀明 坂口
光敏 東
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2008258309A priority Critical patent/JP5536322B2/ja
Publication of JP2009111367A publication Critical patent/JP2009111367A/ja
Publication of JP2009111367A5 publication Critical patent/JP2009111367A5/ja
Application granted granted Critical
Publication of JP5536322B2 publication Critical patent/JP5536322B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Micromachines (AREA)
JP2008258309A 2007-10-09 2008-10-03 基板の製造方法 Active JP5536322B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008258309A JP5536322B2 (ja) 2007-10-09 2008-10-03 基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007263224 2007-10-09
JP2007263224 2007-10-09
JP2008258309A JP5536322B2 (ja) 2007-10-09 2008-10-03 基板の製造方法

Publications (3)

Publication Number Publication Date
JP2009111367A JP2009111367A (ja) 2009-05-21
JP2009111367A5 JP2009111367A5 (enExample) 2011-08-11
JP5536322B2 true JP5536322B2 (ja) 2014-07-02

Family

ID=40351813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008258309A Active JP5536322B2 (ja) 2007-10-09 2008-10-03 基板の製造方法

Country Status (5)

Country Link
US (1) US7795140B2 (enExample)
EP (1) EP2048923A3 (enExample)
JP (1) JP5536322B2 (enExample)
KR (1) KR20090036521A (enExample)
TW (1) TW200919606A (enExample)

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TWI392069B (zh) 2009-11-24 2013-04-01 日月光半導體製造股份有限公司 封裝結構及其封裝製程
WO2011125546A1 (ja) 2010-03-31 2011-10-13 京セラ株式会社 インターポーザー及びそれを用いた電子装置
DE102010029760B4 (de) 2010-06-07 2019-02-21 Robert Bosch Gmbh Bauelement mit einer Durchkontaktierung und Verfahren zu seiner Herstellung
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
TWI446420B (zh) 2010-08-27 2014-07-21 Advanced Semiconductor Eng 用於半導體製程之載體分離方法
TWI445152B (zh) 2010-08-30 2014-07-11 日月光半導體製造股份有限公司 半導體結構及其製作方法
US9007273B2 (en) 2010-09-09 2015-04-14 Advances Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
TWI434387B (zh) 2010-10-11 2014-04-11 日月光半導體製造股份有限公司 具有穿導孔之半導體裝置及具有穿導孔之半導體裝置之封裝結構及其製造方法
TW201241941A (en) * 2010-10-21 2012-10-16 Sumitomo Bakelite Co A method for manufacturing an electronic equipment, and the electronic equipment obtained by using the method, as well as a method for manufacturing electronics and electronic parts, and the electronics and the electronic parts obtained using the method
TWI527174B (zh) 2010-11-19 2016-03-21 日月光半導體製造股份有限公司 具有半導體元件之封裝結構
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
TWI445155B (zh) 2011-01-06 2014-07-11 日月光半導體製造股份有限公司 堆疊式封裝結構及其製造方法
US8853819B2 (en) 2011-01-07 2014-10-07 Advanced Semiconductor Engineering, Inc. Semiconductor structure with passive element network and manufacturing method thereof
KR101767654B1 (ko) 2011-05-19 2017-08-14 삼성전자주식회사 에어 갭 절연 구조를 갖는 관통전극을 구비한 반도체 소자 및 그 제조방법
KR101867998B1 (ko) * 2011-06-14 2018-06-15 삼성전자주식회사 패턴 형성 방법
US8541883B2 (en) 2011-11-29 2013-09-24 Advanced Semiconductor Engineering, Inc. Semiconductor device having shielded conductive vias
US8742591B2 (en) 2011-12-21 2014-06-03 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief
US8975157B2 (en) 2012-02-08 2015-03-10 Advanced Semiconductor Engineering, Inc. Carrier bonding and detaching processes for a semiconductor wafer
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8786060B2 (en) 2012-05-04 2014-07-22 Advanced Semiconductor Engineering, Inc. Semiconductor package integrated with conformal shield and antenna
US9153542B2 (en) 2012-08-01 2015-10-06 Advanced Semiconductor Engineering, Inc. Semiconductor package having an antenna and manufacturing method thereof
US8937387B2 (en) 2012-11-07 2015-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor device with conductive vias
US9159699B2 (en) * 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
US8952542B2 (en) 2012-11-14 2015-02-10 Advanced Semiconductor Engineering, Inc. Method for dicing a semiconductor wafer having through silicon vias and resultant structures
CN103839870B (zh) * 2012-11-20 2016-08-17 中微半导体设备(上海)有限公司 用于tsv刻蚀中改善硅通孔侧壁粗糙度的方法
US9406552B2 (en) 2012-12-20 2016-08-02 Advanced Semiconductor Engineering, Inc. Semiconductor device having conductive via and manufacturing process
US8841751B2 (en) 2013-01-23 2014-09-23 Advanced Semiconductor Engineering, Inc. Through silicon vias for semiconductor devices and manufacturing method thereof
US9978688B2 (en) 2013-02-28 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package having a waveguide antenna and manufacturing method thereof
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JP6235785B2 (ja) * 2013-03-18 2017-11-22 日本電子材料株式会社 プローブカード用ガイド板およびプローブカード用ガイド板の製造方法
JP2015072996A (ja) * 2013-10-02 2015-04-16 新光電気工業株式会社 半導体装置
JP5846185B2 (ja) 2013-11-21 2016-01-20 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
CN110265347A (zh) 2019-06-06 2019-09-20 深圳市华星光电技术有限公司 一种基板
EP3813101A1 (en) * 2019-10-25 2021-04-28 Ams Ag Method of producing a semiconductor body with a trench, semiconductor body with at least one trench and semiconductor device

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Also Published As

Publication number Publication date
EP2048923A3 (en) 2010-12-08
KR20090036521A (ko) 2009-04-14
US7795140B2 (en) 2010-09-14
EP2048923A2 (en) 2009-04-15
TW200919606A (en) 2009-05-01
JP2009111367A (ja) 2009-05-21
US20090093117A1 (en) 2009-04-09

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