JP5383098B2 - 半導体装置の作製方法 - Google Patents

半導体装置の作製方法 Download PDF

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Publication number
JP5383098B2
JP5383098B2 JP2008159876A JP2008159876A JP5383098B2 JP 5383098 B2 JP5383098 B2 JP 5383098B2 JP 2008159876 A JP2008159876 A JP 2008159876A JP 2008159876 A JP2008159876 A JP 2008159876A JP 5383098 B2 JP5383098 B2 JP 5383098B2
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substrate
semiconductor
semiconductor layer
region
layer
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Expired - Fee Related
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JP2008159876A
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Japanese (ja)
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JP2009027156A5 (enExample
JP2009027156A (ja
Inventor
明久 下村
秀和 宮入
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008159876A priority Critical patent/JP5383098B2/ja
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Publication of JP2009027156A5 publication Critical patent/JP2009027156A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2008159876A 2007-06-20 2008-06-19 半導体装置の作製方法 Expired - Fee Related JP5383098B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008159876A JP5383098B2 (ja) 2007-06-20 2008-06-19 半導体装置の作製方法

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2007162444 2007-06-20
JP2007162444 2007-06-20
JP2007162464 2007-06-20
JP2007162464 2007-06-20
JP2008159876A JP5383098B2 (ja) 2007-06-20 2008-06-19 半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2009027156A JP2009027156A (ja) 2009-02-05
JP2009027156A5 JP2009027156A5 (enExample) 2011-07-07
JP5383098B2 true JP5383098B2 (ja) 2014-01-08

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Family Applications (1)

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JP2008159876A Expired - Fee Related JP5383098B2 (ja) 2007-06-20 2008-06-19 半導体装置の作製方法

Country Status (7)

Country Link
US (2) US8093135B2 (enExample)
JP (1) JP5383098B2 (enExample)
KR (1) KR101478813B1 (enExample)
CN (2) CN101681843B (enExample)
SG (1) SG182214A1 (enExample)
TW (1) TWI485805B (enExample)
WO (1) WO2008156040A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009033123A (ja) * 2007-06-27 2009-02-12 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法および半導体装置の作製方法

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5315596B2 (ja) * 2006-07-24 2013-10-16 株式会社Ｓｕｍｃｏ 貼合せｓｏｉウェーハの製造方法
EP2143146A1 (en) * 2007-04-13 2010-01-13 Semiconductor Energy Laboratory Co, Ltd. Photovoltaic device and method for manufacturing the same
CN101743616B (zh) * 2007-06-28 2012-02-22 株式会社半导体能源研究所 半导体装置的制造方法
US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5507063B2 (ja) 2007-07-09 2014-05-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5452900B2 (ja) * 2007-09-21 2014-03-26 株式会社半導体エネルギー研究所 半導体膜付き基板の作製方法
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2009135453A (ja) * 2007-10-30 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、半導体装置及び電子機器
JP2010153802A (ja) 2008-11-20 2010-07-08 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
US8299537B2 (en) 2009-02-11 2012-10-30 International Business Machines Corporation Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region
US9024312B2 (en) * 2009-09-30 2015-05-05 Dai Nippon Printing Co., Ltd. Substrate for flexible device, thin film transistor substrate for flexible device, flexible device, substrate for thin film element, thin film element, thin film transistor, method for manufacturing substrate for thin film element, method for manufacturing thin film element, and method for manufacturing thin film transistor
US8288249B2 (en) * 2010-01-26 2012-10-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8461017B2 (en) 2010-07-19 2013-06-11 Soitec Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region
US8835955B2 (en) * 2010-11-01 2014-09-16 Translucent, Inc. IIIOxNy on single crystal SOI substrate and III n growth platform
JP6016532B2 (ja) 2011-09-07 2016-10-26 株式会社半導体エネルギー研究所 半導体装置
CN103137537B (zh) * 2011-11-28 2015-04-15 中国科学院上海微系统与信息技术研究所 一种图形化全耗尽绝缘体上Si/CoSi2衬底材料及其制备方法
US9178042B2 (en) * 2013-01-08 2015-11-03 Globalfoundries Inc Crystalline thin-film transistor
US9577110B2 (en) 2013-12-27 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including an oxide semiconductor and the display device including the semiconductor device
JP6524862B2 (ja) 2015-08-27 2019-06-05 株式会社Sumco Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
JP6471650B2 (ja) * 2015-08-27 2019-02-20 株式会社Sumco Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
CN108028214B (zh) * 2015-12-30 2022-04-08 玛特森技术公司 用于毫秒退火系统的气体流动控制
US9966301B2 (en) * 2016-06-27 2018-05-08 New Fab, LLC Reduced substrate effects in monolithically integrated RF circuits
JP2019054153A (ja) * 2017-09-15 2019-04-04 東芝メモリ株式会社 半導体装置の製造方法
JP6680378B2 (ja) * 2019-03-13 2020-04-15 株式会社Sumco Ｓｏｉウェーハ
US11030426B2 (en) * 2019-10-24 2021-06-08 Asianlink Technology Incorporation Electronic book for detecting page codes by using wireless radio-frequency technology

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02267950A (ja) * 1989-04-07 1990-11-01 Sony Corp 半導体基板
JP2564935B2 (ja) * 1989-04-20 1996-12-18 三菱電機株式会社 半導体装置
US5753560A (en) * 1996-10-31 1998-05-19 Motorola, Inc. Method for fabricating a semiconductor device using lateral gettering
JP3976828B2 (ja) * 1997-02-17 2007-09-19 株式会社半導体エネルギー研究所 結晶性珪素膜の作製方法
US6027988A (en) 1997-05-28 2000-02-22 The Regents Of The University Of California Method of separating films from bulk substrates by plasma immersion ion implantation
JP3844566B2 (ja) * 1997-07-30 2006-11-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
JPH11163363A (ja) * 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
US6369410B1 (en) * 1997-12-15 2002-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US6503321B2 (en) * 1998-02-17 2003-01-07 The Trustees Of Columbia University In The City Of New York Slicing of single-crystal films using ion implantation
DE19821999A1 (de) * 1998-05-15 1999-11-18 Siemens Ag SOI-Halbleiteranordnung und Verfahren zur Herstellung derselben
JP3697106B2 (ja) * 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
CN1241803A (zh) * 1998-05-15 2000-01-19 佳能株式会社 半导体衬底、半导体薄膜以及多层结构的制造工艺
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP4493749B2 (ja) * 1998-07-15 2010-06-30 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7153729B1 (en) * 1998-07-15 2006-12-26 Semiconductor Energy Laboratory Co., Ltd. Crystalline semiconductor thin film, method of fabricating the same, semiconductor device, and method of fabricating the same
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4609867B2 (ja) * 1998-07-29 2011-01-12 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び半導体装置の作製方法
US6380007B1 (en) 1998-12-28 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
JP4066574B2 (ja) * 1999-03-04 2008-03-26 富士電機デバイステクノロジー株式会社 半導体装置の製造方法
US7232742B1 (en) 1999-11-26 2007-06-19 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device that includes forming a material with a high tensile stress in contact with a semiconductor film to getter impurities from the semiconductor film
TW473800B (en) * 1999-12-28 2002-01-21 Semiconductor Energy Lab Method of manufacturing a semiconductor device
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US7045444B2 (en) 2000-12-19 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device that includes selectively adding a noble gas element
JP4316132B2 (ja) * 2000-12-19 2009-08-19 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI221645B (en) 2001-01-19 2004-10-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
US7115453B2 (en) 2001-01-29 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US7141822B2 (en) 2001-02-09 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5088993B2 (ja) 2001-02-16 2012-12-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4993810B2 (ja) * 2001-02-16 2012-08-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7052943B2 (en) 2001-03-16 2006-05-30 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP2002343799A (ja) * 2001-05-17 2002-11-29 Nec Corp Ｓｏｉ基板及び半導体装置の製造方法
TW541584B (en) 2001-06-01 2003-07-11 Semiconductor Energy Lab Semiconductor film, semiconductor device and method for manufacturing same
US6743700B2 (en) 2001-06-01 2004-06-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, semiconductor device and method of their production
FR2835097B1 (fr) * 2002-01-23 2005-10-14 Procede optimise de report d'une couche mince de carbure de silicium sur un substrat d'accueil
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7119365B2 (en) 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP2003282885A (ja) * 2002-03-26 2003-10-03 Sharp Corp 半導体装置およびその製造方法
JP4289837B2 (ja) * 2002-07-15 2009-07-01 アプライド マテリアルズ インコーポレイテッド イオン注入方法及びｓｏｉウエハの製造方法
JP4509488B2 (ja) * 2003-04-02 2010-07-21 株式会社Sumco 貼り合わせ基板の製造方法
US6972247B2 (en) * 2003-12-05 2005-12-06 International Business Machines Corporation Method of fabricating strained Si SOI wafers
US6992025B2 (en) * 2004-01-12 2006-01-31 Sharp Laboratories Of America, Inc. Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
WO2006064772A1 (ja) * 2004-12-13 2006-06-22 Matsushita Electric Industrial Co., Ltd. プラズマドーピング方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009033123A (ja) * 2007-06-27 2009-02-12 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法および半導体装置の作製方法

Also Published As

Publication number Publication date
TW200917416A (en) 2009-04-16
CN101681843B (zh) 2012-05-09
WO2008156040A1 (en) 2008-12-24
SG182214A1 (en) 2012-07-30
US8551828B2 (en) 2013-10-08
US20110117708A1 (en) 2011-05-19
KR101478813B1 (ko) 2015-01-02
TWI485805B (zh) 2015-05-21
CN102592977A (zh) 2012-07-18
KR20100033408A (ko) 2010-03-29
US8093135B2 (en) 2012-01-10
US20080318367A1 (en) 2008-12-25
CN102592977B (zh) 2015-03-25
CN101681843A (zh) 2010-03-24
JP2009027156A (ja) 2009-02-05

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