JP5322531B2 - 配線基板の製造方法 - Google Patents

配線基板の製造方法 Download PDF

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Publication number
JP5322531B2
JP5322531B2 JP2008199728A JP2008199728A JP5322531B2 JP 5322531 B2 JP5322531 B2 JP 5322531B2 JP 2008199728 A JP2008199728 A JP 2008199728A JP 2008199728 A JP2008199728 A JP 2008199728A JP 5322531 B2 JP5322531 B2 JP 5322531B2
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JP
Japan
Prior art keywords
layer
insulating layer
wiring
via hole
interlayer insulating
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Active
Application number
JP2008199728A
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English (en)
Japanese (ja)
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JP2010010639A (ja
JP2010010639A5 (enExample
Inventor
人資 近藤
朋幸 下平
正司 小平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008199728A priority Critical patent/JP5322531B2/ja
Priority to US12/469,952 priority patent/US20090288870A1/en
Publication of JP2010010639A publication Critical patent/JP2010010639A/ja
Publication of JP2010010639A5 publication Critical patent/JP2010010639A5/ja
Application granted granted Critical
Publication of JP5322531B2 publication Critical patent/JP5322531B2/ja
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1152—Replicating the surface structure of a sacrificial layer, e.g. for roughening
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1383—Temporary protective insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1388—Temporary protective conductive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2008199728A 2008-05-25 2008-08-01 配線基板の製造方法 Active JP5322531B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008199728A JP5322531B2 (ja) 2008-05-27 2008-08-01 配線基板の製造方法
US12/469,952 US20090288870A1 (en) 2008-05-25 2009-05-21 Wiring substrate and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2008137979 2008-05-27
JP2008137979 2008-05-27
JP2008199728A JP5322531B2 (ja) 2008-05-27 2008-08-01 配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2010010639A JP2010010639A (ja) 2010-01-14
JP2010010639A5 JP2010010639A5 (enExample) 2011-07-21
JP5322531B2 true JP5322531B2 (ja) 2013-10-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008199728A Active JP5322531B2 (ja) 2008-05-25 2008-08-01 配線基板の製造方法

Country Status (2)

Country Link
US (1) US20090288870A1 (enExample)
JP (1) JP5322531B2 (enExample)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5138459B2 (ja) * 2008-05-15 2013-02-06 新光電気工業株式会社 配線基板の製造方法
JP5282487B2 (ja) * 2008-08-28 2013-09-04 住友ベークライト株式会社 多層プリント配線板の製造方法、多層プリント配線板および半導体装置
JP2011100798A (ja) * 2009-11-04 2011-05-19 Panasonic Electric Works Co Ltd 回路基板
JP5483658B2 (ja) * 2010-07-29 2014-05-07 京セラＳｌｃテクノロジー株式会社 配線基板の製造方法
CN103140537B (zh) * 2010-08-10 2016-10-12 日立化成株式会社 树脂组合物、树脂固化物、配线板及配线板的制造方法
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
JP6057641B2 (ja) * 2012-09-20 2017-01-11 新光電気工業株式会社 配線基板及びその製造方法
JP6322885B2 (ja) * 2012-11-01 2018-05-16 味の素株式会社 プリント配線板の製造方法
US11102889B2 (en) * 2012-12-27 2021-08-24 Ushio Denki Kabushiki Kaisha Desmearing method and desmearing device
US8945984B2 (en) * 2013-02-28 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace methods and structures in packaging
US20140353019A1 (en) 2013-05-30 2014-12-04 Deepak ARORA Formation of dielectric with smooth surface
JP6247032B2 (ja) * 2013-07-01 2017-12-13 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
KR101531097B1 (ko) * 2013-08-22 2015-06-23 삼성전기주식회사 인터포저 기판 및 이의 제조방법
JP6228785B2 (ja) * 2013-09-02 2017-11-08 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6234132B2 (ja) 2013-09-19 2017-11-22 新光電気工業株式会社 配線基板の製造方法
JP5874720B2 (ja) 2013-12-20 2016-03-02 ウシオ電機株式会社 配線基板材料のデスミア処理方法、配線基板材料の製造方法および複合絶縁層形成材料
JP5967147B2 (ja) * 2013-12-26 2016-08-10 ウシオ電機株式会社 デスミア処理装置
JP6503633B2 (ja) * 2014-04-24 2019-04-24 味の素株式会社 回路基板の製造方法
JP6375243B2 (ja) * 2014-05-21 2018-08-15 新光電気工業株式会社 配線基板の製造方法
JP2016025217A (ja) * 2014-07-22 2016-02-08 日立化成株式会社 プリント配線板及びその製造方法並びに熱硬化性樹脂組成物及び樹脂フィルム
JP2016051870A (ja) * 2014-09-02 2016-04-11 イビデン株式会社 パッケージ基板及びパッケージ基板の製造方法
JP2016058615A (ja) * 2014-09-11 2016-04-21 凸版印刷株式会社 プリント配線板およびその製造方法
JP2016092307A (ja) * 2014-11-07 2016-05-23 株式会社アルバック 樹脂基板の加工方法
JP6507668B2 (ja) * 2015-01-26 2019-05-08 日立化成株式会社 プリント配線板の製造方法
KR20160099381A (ko) * 2015-02-12 2016-08-22 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
JP2016207893A (ja) * 2015-04-24 2016-12-08 イビデン株式会社 プリント配線板およびその製造方法
JP2016213283A (ja) * 2015-05-01 2016-12-15 ソニー株式会社 製造方法、および貫通電極付配線基板
US10388608B2 (en) * 2015-08-28 2019-08-20 Hitachi Chemical Company, Ltd. Semiconductor device and method for manufacturing same
JP6819608B2 (ja) * 2015-11-30 2021-01-27 凸版印刷株式会社 多層プリント配線基板及びその製造方法
JP6672895B2 (ja) * 2016-03-03 2020-03-25 ウシオ電機株式会社 配線基板の製造方法
JP2017199824A (ja) * 2016-04-28 2017-11-02 株式会社ジェイデバイス 半導体パッケージの製造方法
CN106376184B (zh) * 2016-07-22 2019-02-01 深南电路股份有限公司 埋入式线路制作方法和封装基板
JP2018166173A (ja) * 2017-03-28 2018-10-25 日本メクトロン株式会社 プリント配線板の製造方法、および保護フィルム
JP6658722B2 (ja) * 2017-12-25 2020-03-04 味の素株式会社 プリント配線板の製造方法
JP2019121771A (ja) * 2018-01-11 2019-07-22 イビデン株式会社 プリント配線板
JP7424741B2 (ja) * 2018-05-31 2024-01-30 株式会社レゾナック 配線基板の製造方法
JP7263710B2 (ja) * 2018-07-26 2023-04-25 株式会社レゾナック 配線基板の製造方法
JP6627944B2 (ja) * 2018-10-09 2020-01-08 味の素株式会社 回路基板の製造方法
JP7430990B2 (ja) * 2019-06-26 2024-02-14 新光電気工業株式会社 配線基板の製造方法
JP2021009911A (ja) * 2019-07-01 2021-01-28 株式会社アルバック 電子部品の製造方法
JP7120261B2 (ja) * 2020-02-05 2022-08-17 味の素株式会社 プリント配線板の製造方法及び半導体装置の製造方法
EP3890456A1 (en) * 2020-03-31 2021-10-06 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier hole cleaning by dry etching with protected insulation layer
JP7512122B2 (ja) 2020-08-06 2024-07-08 新光電気工業株式会社 配線基板の製造方法
US11393747B2 (en) * 2020-08-31 2022-07-19 Advanced Semiconductor Engineering, Inc. Substrate structure having roughned upper surface of conductive layer
KR20220074373A (ko) 2020-11-27 2022-06-03 엘지이노텍 주식회사 회로기판 및 이의 제조 방법
JP7529562B2 (ja) * 2020-12-28 2024-08-06 Tdk株式会社 電子部品及びその製造方法
JP7760246B2 (ja) * 2021-01-13 2025-10-27 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP2023039312A (ja) * 2021-09-08 2023-03-20 イビデン株式会社 プリント配線板の製造方法
JP7664135B2 (ja) * 2021-09-22 2025-04-17 新光電気工業株式会社 配線基板及び配線基板の製造方法
KR20230050025A (ko) * 2021-10-07 2023-04-14 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
JP2023150471A (ja) * 2022-03-31 2023-10-16 株式会社レゾナック プリント配線板の製造方法、プリント配線板及び半導体パッケージ
US12494433B2 (en) * 2022-06-13 2025-12-09 Apple Inc. 3D embedded redistribution layers for IC substrate packaging
JP2024067275A (ja) * 2022-11-04 2024-05-17 新光電気工業株式会社 配線基板及びその製造方法
CN118785608A (zh) * 2023-03-28 2024-10-15 奥特斯科技(重庆)有限公司 部件承载件及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4707565A (en) * 1985-03-19 1987-11-17 Nitto Boseki Co., Ltd. Substrate for printed circuit
JP2993065B2 (ja) * 1990-07-27 1999-12-20 三菱瓦斯化学株式会社 表面平滑金属箔張積層板
US6286207B1 (en) * 1998-05-08 2001-09-11 Nec Corporation Resin structure in which manufacturing cost is cheap and sufficient adhesive strength can be obtained and method of manufacturing it
JP4240243B2 (ja) * 1998-07-17 2009-03-18 日立化成工業株式会社 ビルドアップ多層配線板の製造方法
JP2001007468A (ja) * 1999-06-24 2001-01-12 Nec Kansai Ltd 配線基板，多層配線基板およびその製造方法
US7614145B2 (en) * 2001-09-05 2009-11-10 Zeon Corporation Method for manufacturing multilayer circuit board and resin base material
US6596384B1 (en) * 2002-04-09 2003-07-22 International Business Machines Corporation Selectively roughening conductors for high frequency printed wiring boards
JP2007073834A (ja) * 2005-09-08 2007-03-22 Shinko Electric Ind Co Ltd 絶縁樹脂層上の配線形成方法
JP4895795B2 (ja) * 2006-12-20 2012-03-14 新光電気工業株式会社 多層配線基板の製造方法

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JP2010010639A (ja) 2010-01-14
US20090288870A1 (en) 2009-11-26

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