JP5311116B2 - 集積回路のアレイ領域内に複数の導電線を作る方法 - Google Patents
集積回路のアレイ領域内に複数の導電線を作る方法 Download PDFInfo
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
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Description
ある実施形態において、基板に転写されるべきフィーチャーパターンの一部は、基板に対するプロセスで用いられるフォトリソグラフィ技術の最小ピッチ以下のピッチを有する。加えて、ある実施形態は、論理(logic)又はゲートアレイ、並びに、DRAM、リード・オンリー・メモリー(ROM),フラッシュメモリ及びゲートアレイのような揮発及び不揮発メモリデバイスを含む電子デバイスのアレイを有するデバイスを形成するために利用可能である。従来のフォトリソグラフィは、チップの周辺部における接触部(コンタクト)のような大きなフィーチャーを形成するために有効であるが、ピッチ増倍は、そのようなデバイスにおいて、例えば、トランジスタゲート電極及びチップのアレイ領域における導電線を形成するために有効である。メモリデバイス製造過程のマスキング処理の一例が、本明細書で図示され、説明されている。
〔発明の範囲〕
先に詳細な説明で本発明の幾つかの実施形態を開示したが、この開示は説明のためであり、本発明を限定するものではないことを理解いただきたい。開示された特定の構造及び処理は、上記で説明したものと異なってもよいこと、及び、本明細書で説明した方法は、集積回路製造以外の状況でも利用可能であることを理解されたい。
〔関連する出願の参照〕
本願は、米国特許出願第10/932,993号(2004年9月1日出願、代理人整理番号MICRON.293A;マイクロン整理番号2003−1445.00/US)、米国特許出願第10/934,778号(2004年9月2日出願;代理人整理番号MICRON.294A;マイクロン整理番号2003−1446.00/US)、米国特許出願第10/931,771号(2004年8月31日出願、代理人整理番号MICRON.295A;マイクロン整理番号2004−0068.00/US)、米国特許出願第10/934,317号(2004年9月2日出願、代理人整理番号MICRON.296A;マイクロン整理番号2004−0114.00/US)、米国特許出願−−−−−(本願と同時に出願、代理人整理番号MICRON.313A;マイクロン整理番号2004−1065.00/US)、米国仮特許出願第60/662,323号(2005年3月15日出願、代理人整理番号MICRON.316PR;マイクロン整理番号2004−1130.00/PR)、及び米国特許出願第11/134,982号(2005年5月23日出願、代理人整理番号MICRON.317A;マイクロン整理番号2004−0968.00/US)に関する。これらの関連出願の全ての内容は、その参照をもって、本明細書に含まれる。
Claims (17)
- 集積回路のアレイ領域内に複数の導電線を作る方法であって、
複数の導電性プラグに接触する基板、前記導電性プラグを覆う絶縁膜、前記絶縁膜を覆う下方マスク層、及び前記下方マスク層上にピッチ増倍技術を用いて形成されたスペーサーのアレイ、を含む積層膜を設けることであって、前記スペーサーのアレイは複数のループ状の端部を形成する、ことと、
前記下方マスク層上及び前記スペーサーのアレイ上に犠牲膜を堆積して、平坦な表面を形成することと、
前記犠牲膜の一部の上にレジストマスクを形成することであって、前記レジストマスクは、前記スペーサーのアレイ上に開口部を画定すると共に前記スペーサーのアレイの前記ループ状の端部を覆い、前記下方マスク層及び前記犠牲膜が前記レジストマスクに対して選択的にエッチング可能である、ことと、
前記レジストマスクをエッチングマスクとして用いて前記犠牲膜をエッチングし、前記下方マスク層の一部を露出させることと、
前記スペーサーのアレイ及び前記レジストマスクをエッチングマスクとして用いて前記下方マスク層をエッチングし、前記絶縁膜の一部を露出させることと、
前記犠牲膜を除去することと、
前記下方マスク層をエッチングマスクとして用いて前記絶縁膜の前記露出された部分に複数の溝をエッチングし、前記導電性プラグの少なくとも一部を露出させることと、
前記複数の溝内に金属の堆積を行うことであって、前記金属は前記導電性プラグと接触する、ことと、
平坦化処理を行って、前記金属と前記絶縁膜とが交互に現れる平坦な表面を形成することと、
を含むことを特徴とする方法。 - 前記レジストマスクは、更に、前記アレイ領域の外側の周辺領域に接続される複数の相互接続を画定する、ことを特徴とする請求項1に記載の方法。
- 前記積層膜を設けることは、フォトリソグラフィを用いて前記スペーサーのアレイを形成することを含む、ことを特徴とする請求項1に記載の方法。
- 前記複数の溝をエッチングする前に、前記スペーサーのアレイを除去することを更に含む、ことを特徴とする請求項1に記載の方法。
- 前記複数の溝をエッチングする前に、前記スペーサーのアレイ、前記レジストマスク、及び前記犠牲膜を除去することを更に含む、ことを特徴とする請求項1に記載の方法。
- 前記複数の溝をエッチングすることは、前記レジストマスクに覆われた前記ループ状の端部を前記絶縁膜に転写することなく、前記ループ状の端部以外の前記スペーサーのアレイに対応したパターンを前記絶縁膜に転写することを含む、ことを特徴とする請求項1に記載の方法。
- 前記アレイ領域はメモリアレイ領域である、ことを特徴とする請求項1に記載の方法。
- 前記アレイ領域は論理素子アレイ領域である、ことを特徴とする請求項1に記載の方法。
- 前記アレイ領域は、フラッシュメモリデバイスの一部を形成する、ことを特徴とする請求項1に記載の方法。
- 前記犠牲膜は絶縁膜である、ことを特徴とする請求項1に記載の方法。
- 前記犠牲膜は底面反射防止膜である、ことを特徴とする請求項1に記載の方法。
- 前記スペーサーは、酸化シリコン、窒化シリコン、多結晶シリコン、及びカーボンから成るグループから選択される、ことを特徴とする請求項1に記載の方法。
- 前記スペーサーは、原子層堆積プロセスを用いて堆積される、ことを特徴とする請求項1記載の方法。
- 前記スペーサーは、摂氏400度より低い温度で堆積される、ことを特徴とする請求項1に記載の方法。
- 前記スペーサーは、30ナノメートルから100ナノメートルの間のフィーチャーサイズを有する、ことを特徴とする請求項1に記載の方法。
- 前記スペーサーは、32.5ナノメートルから65ナノメートルの間のフィーチャーサイズを有する、ことを特徴する請求項1に記載の方法。
- 前記スペーサーは、前記導電性プラグのフィーチャーサイズと等しいフィーチャーサイズを有する、ことを特徴とする請求項1記載の方法。
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US11/216,477 US7611944B2 (en) | 2005-03-28 | 2005-08-31 | Integrated circuit fabrication |
PCT/US2006/007333 WO2006104634A2 (en) | 2005-03-28 | 2006-02-27 | Integrated circuit fabrication |
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EP (1) | EP1864320B1 (ja) |
JP (1) | JP5311116B2 (ja) |
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US20150004786A1 (en) | 2015-01-01 |
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