JP5111980B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5111980B2 JP5111980B2 JP2007228882A JP2007228882A JP5111980B2 JP 5111980 B2 JP5111980 B2 JP 5111980B2 JP 2007228882 A JP2007228882 A JP 2007228882A JP 2007228882 A JP2007228882 A JP 2007228882A JP 5111980 B2 JP5111980 B2 JP 5111980B2
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- JP
- Japan
- Prior art keywords
- region
- memory cell
- peripheral circuit
- cell array
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
Description
図1は、本発明の第1の実施形態に係るNAND型フラッシュメモリ等の不揮発性半導体メモリを含む半導体装置の概略を示す平面図である。
図11は、本発明の第2の実施形態に係るNAND型フラッシュメモリ等の不揮発性半導体メモリを含む半導体装置の概略を示す平面図である。なお、図1と対応する部分には図1と同一符号を付してあり、詳細な説明は省略する。
Claims (4)
- メモリセルアレイ領域と、
前記メモリセルアレイ領域の周辺に設けられた周辺回路領域と、
前記メモリセルアレイ領域と前記周辺回路領域との間に設けられた所定幅を有する、前記メモリセルアレイ領域と前記周辺回路領域とを二重露光で露光する際の境界領域とを備え、
前記メモリセルアレイ領域は、
複数の不揮発性半導体メモリセルを含むセル領域と、
前記セル領域内からその外側の領域に延在して設けられた複数の直線状配線とを備え、
前記境界領域は、前記複数の直線状配線よりも下層に設けられ、前記複数の直線状配線と電気的に接続され、かつ配線幅が前記直線状配線の幅より太い複数の下層配線とを備え、
前記周辺回路領域は、前記複数の下層配線を介して、前記複数の直線状配線に電気的に接続された複数のパターンを備え、
前記境界領域は、前記複数の直線状配線、前記複数の直線状配線と同層の配線が設けられていないことを特徴とする半導体装置。 - 前記周辺回路領域には、複数の高耐圧素子がさらに備えられ、前記直線状配線は、前記下層配線および前記高耐圧素子を介して前記周辺回路領域の複数のパターンと接続されることを特徴とする請求項1に記載の半導体装置。
- 前記複数の直線状配線の幅は、メモリセルの幅と同じ幅であり、前記複数のパターンの配線幅は前記直線状配線の幅よりも大きいことを特徴とする請求項1または2に記載の半導体装置。
- 前記セル領域以外の前記メモリセルアレイ領域には、前記複数の直線状配線の長手方向に対して垂直または平行なパターンがさらに含まれ、このパターンは前記複数の直線状配線と同じレイヤ上に形成されていることを特徴とする請求項1ないし3のいずれか1項に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007228882A JP5111980B2 (ja) | 2006-09-06 | 2007-09-04 | 半導体装置 |
US11/851,078 US7701742B2 (en) | 2006-09-06 | 2007-09-06 | Semiconductor device |
US12/729,273 US7998812B2 (en) | 2006-09-06 | 2010-03-23 | Semiconductor device |
US13/183,103 US8129776B2 (en) | 2006-09-06 | 2011-07-14 | Semiconductor device |
US13/359,791 US8313997B2 (en) | 2006-09-06 | 2012-01-27 | Method of manufacturing a semiconductor memory using two exposure masks to form a same wiring layer |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006241775 | 2006-09-06 | ||
JP2006241775 | 2006-09-06 | ||
JP2007228882A JP5111980B2 (ja) | 2006-09-06 | 2007-09-04 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008091893A JP2008091893A (ja) | 2008-04-17 |
JP5111980B2 true JP5111980B2 (ja) | 2013-01-09 |
Family
ID=39274810
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007228882A Expired - Fee Related JP5111980B2 (ja) | 2006-09-06 | 2007-09-04 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (4) | US7701742B2 (ja) |
JP (1) | JP5111980B2 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100822806B1 (ko) * | 2006-10-20 | 2008-04-18 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 형성 방법 |
US20100264547A1 (en) * | 2007-07-09 | 2010-10-21 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing |
JP2009016696A (ja) * | 2007-07-09 | 2009-01-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2009272026A (ja) * | 2008-05-12 | 2009-11-19 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2010098067A (ja) * | 2008-10-15 | 2010-04-30 | Toshiba Corp | 半導体装置 |
JP2012104694A (ja) | 2010-11-11 | 2012-05-31 | Toshiba Corp | 半導体記憶装置 |
JP2012119517A (ja) | 2010-12-01 | 2012-06-21 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
JP2012182202A (ja) | 2011-02-28 | 2012-09-20 | Toshiba Corp | 半導体記憶装置 |
JP2013207123A (ja) | 2012-03-29 | 2013-10-07 | Toshiba Corp | 半導体装置 |
JP5814867B2 (ja) | 2012-06-27 | 2015-11-17 | 株式会社東芝 | 半導体記憶装置 |
US9691719B2 (en) | 2013-01-11 | 2017-06-27 | Renesas Electronics Corporation | Semiconductor device |
US9093642B2 (en) * | 2013-01-25 | 2015-07-28 | Kabushiki Kaisha Toshiba | Non-volatile memory device and method of manufacturing the same |
US9257484B2 (en) | 2013-01-30 | 2016-02-09 | Kabushiki Kaisha Toshiba | Non-volatile memory device and method of manufacturing the same |
JP2014150234A (ja) * | 2013-01-30 | 2014-08-21 | Toshiba Corp | 不揮発性記憶装置およびその製造方法 |
US10304728B2 (en) * | 2017-05-01 | 2019-05-28 | Advanced Micro Devices, Inc. | Double spacer immersion lithography triple patterning flow and method |
Family Cites Families (22)
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US5251168A (en) * | 1991-07-31 | 1993-10-05 | Texas Instruments Incorporated | Boundary cells for improving retention time in memory devices |
JPH06181164A (ja) | 1992-12-15 | 1994-06-28 | Hitachi Ltd | 露光方法及び露光装置 |
JP3370903B2 (ja) * | 1997-06-04 | 2003-01-27 | 松下電器産業株式会社 | 半導体装置製造用のフォトマスク群と、それを用いた半導体装置の製造方法 |
JP3586072B2 (ja) | 1997-07-10 | 2004-11-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US6376879B2 (en) * | 1998-06-08 | 2002-04-23 | Kabushiki Kaisha Toshiba | Semiconductor device having MISFETs |
KR100357692B1 (ko) * | 2000-10-27 | 2002-10-25 | 삼성전자 주식회사 | 비휘발성 메모리소자 및 그 제조방법 |
KR100414211B1 (ko) * | 2001-03-17 | 2004-01-07 | 삼성전자주식회사 | 모노스 게이트 구조를 갖는 비휘발성 메모리소자 및 그제조방법 |
JP4160283B2 (ja) * | 2001-09-04 | 2008-10-01 | 株式会社東芝 | 半導体装置の製造方法 |
JP2003249578A (ja) * | 2001-09-29 | 2003-09-05 | Toshiba Corp | 半導体集積回路装置 |
US6862223B1 (en) * | 2002-07-05 | 2005-03-01 | Aplus Flash Technology, Inc. | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout |
US7154582B2 (en) * | 2003-02-14 | 2006-12-26 | Canon Kabushiki Kaisha | Exposure apparatus and method |
JP2005109236A (ja) * | 2003-09-30 | 2005-04-21 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
US7094686B2 (en) * | 2003-12-16 | 2006-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact hole printing by packing and unpacking |
JP4801986B2 (ja) * | 2005-02-03 | 2011-10-26 | 株式会社東芝 | 半導体記憶装置 |
US7611944B2 (en) * | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
JP2006310390A (ja) * | 2005-04-26 | 2006-11-09 | Toshiba Corp | 半導体装置 |
JP2006310562A (ja) * | 2005-04-28 | 2006-11-09 | Nec Electronics Corp | 半導体記憶装置およびその製造方法 |
JP2006351861A (ja) * | 2005-06-16 | 2006-12-28 | Toshiba Corp | 半導体装置の製造方法 |
JP4768469B2 (ja) * | 2006-02-21 | 2011-09-07 | 株式会社東芝 | 半導体装置の製造方法 |
JP4322897B2 (ja) * | 2006-07-07 | 2009-09-02 | エルピーダメモリ株式会社 | 半導体装置の製造方法 |
JP2009016696A (ja) | 2007-07-09 | 2009-01-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2009272026A (ja) | 2008-05-12 | 2009-11-19 | Toshiba Corp | 不揮発性半導体記憶装置 |
-
2007
- 2007-09-04 JP JP2007228882A patent/JP5111980B2/ja not_active Expired - Fee Related
- 2007-09-06 US US11/851,078 patent/US7701742B2/en not_active Expired - Fee Related
-
2010
- 2010-03-23 US US12/729,273 patent/US7998812B2/en not_active Expired - Fee Related
-
2011
- 2011-07-14 US US13/183,103 patent/US8129776B2/en not_active Expired - Fee Related
-
2012
- 2012-01-27 US US13/359,791 patent/US8313997B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20120135356A1 (en) | 2012-05-31 |
US7701742B2 (en) | 2010-04-20 |
US20110267867A1 (en) | 2011-11-03 |
US8129776B2 (en) | 2012-03-06 |
US8313997B2 (en) | 2012-11-20 |
US20080084728A1 (en) | 2008-04-10 |
US20100177546A1 (en) | 2010-07-15 |
JP2008091893A (ja) | 2008-04-17 |
US7998812B2 (en) | 2011-08-16 |
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