JP5203108B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法

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Publication number
JP5203108B2
JP5203108B2 JP2008234621A JP2008234621A JP5203108B2 JP 5203108 B2 JP5203108 B2 JP 5203108B2 JP 2008234621 A JP2008234621 A JP 2008234621A JP 2008234621 A JP2008234621 A JP 2008234621A JP 5203108 B2 JP5203108 B2 JP 5203108B2
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Japan
Prior art keywords
layer
metal layer
pad
wiring board
metal
Prior art date
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Active
Application number
JP2008234621A
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English (en)
Japanese (ja)
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JP2010067887A5 (enExample
JP2010067887A (ja
Inventor
道郎 尾川
和弘 小林
健太郎 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008234621A priority Critical patent/JP5203108B2/ja
Priority to US12/557,847 priority patent/US8399779B2/en
Publication of JP2010067887A publication Critical patent/JP2010067887A/ja
Publication of JP2010067887A5 publication Critical patent/JP2010067887A5/ja
Priority to US13/764,938 priority patent/US9024207B2/en
Priority to US13/764,931 priority patent/US20130153271A1/en
Application granted granted Critical
Publication of JP5203108B2 publication Critical patent/JP5203108B2/ja
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    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
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    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/383—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by microetching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
    • Y10T29/4916—Simultaneous circuit manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2008234621A 2008-09-12 2008-09-12 配線基板及びその製造方法 Active JP5203108B2 (ja)

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US12/557,847 US8399779B2 (en) 2008-09-12 2009-09-11 Wiring board and method of manufacturing the same
US13/764,938 US9024207B2 (en) 2008-09-12 2013-02-12 Method of manufacturing a wiring board having pads highly resistant to peeling
US13/764,931 US20130153271A1 (en) 2008-09-12 2013-02-12 Wiring board and method of manufacturing the same

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Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8240036B2 (en) 2008-04-30 2012-08-14 Panasonic Corporation Method of producing a circuit board
JP5138459B2 (ja) * 2008-05-15 2013-02-06 新光電気工業株式会社 配線基板の製造方法
KR101070098B1 (ko) * 2009-09-15 2011-10-04 삼성전기주식회사 인쇄회로기판 및 그의 제조 방법
US9332642B2 (en) 2009-10-30 2016-05-03 Panasonic Corporation Circuit board
CN102598883A (zh) * 2009-10-30 2012-07-18 松下电器产业株式会社 电路板以及在电路板上安装有元件的半导体装置
JP5504149B2 (ja) * 2009-12-28 2014-05-28 日本特殊陶業株式会社 多層配線基板
JP5603600B2 (ja) * 2010-01-13 2014-10-08 新光電気工業株式会社 配線基板及びその製造方法、並びに半導体パッケージ
US8759209B2 (en) * 2010-03-25 2014-06-24 Stats Chippac, Ltd. Semiconductor device and method of forming a dual UBM structure for lead free bump connections
US8677617B2 (en) 2010-04-28 2014-03-25 International Business Machines Corporation Printed circuit board edge connector
KR101156924B1 (ko) 2010-10-12 2012-06-21 삼성전기주식회사 인쇄회로기판의 제조방법
JP2012093646A (ja) * 2010-10-28 2012-05-17 Seiko Epson Corp 電子デバイス及びその製造方法
KR101718011B1 (ko) * 2010-11-01 2017-03-21 삼성전자주식회사 반도체 패키지 및 그 제조방법
JP2013093405A (ja) * 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法
US9165878B2 (en) * 2013-03-14 2015-10-20 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
CN103367296A (zh) * 2013-07-16 2013-10-23 天津威盛电子有限公司 一种电子基板及使用其制作集成电路的方法
KR20150017938A (ko) * 2013-08-08 2015-02-23 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP2015041729A (ja) * 2013-08-23 2015-03-02 イビデン株式会社 プリント配線板
JP5555368B1 (ja) * 2013-12-05 2014-07-23 株式会社イースタン 配線基板の製造方法
JP2015159242A (ja) * 2014-02-25 2015-09-03 京セラ株式会社 配線基板およびそれを備えた多層配線基板
KR102211741B1 (ko) * 2014-07-21 2021-02-03 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
JP2016029682A (ja) * 2014-07-25 2016-03-03 イビデン株式会社 プリント配線板
JP5795415B1 (ja) * 2014-08-29 2015-10-14 新光電気工業株式会社 配線基板及びその製造方法
US10325853B2 (en) 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
JP2016111069A (ja) 2014-12-03 2016-06-20 イビデン株式会社 パッケージ基板
JP2016115823A (ja) 2014-12-16 2016-06-23 イビデン株式会社 プリント配線板
CN107211525B (zh) 2014-12-16 2020-11-06 安费诺有限公司 用于印刷电路板的高速互连
JP6510884B2 (ja) 2015-05-19 2019-05-08 新光電気工業株式会社 配線基板及びその製造方法と電子部品装置
US9779940B2 (en) * 2015-07-01 2017-10-03 Zhuahai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Chip package
JP6632302B2 (ja) * 2015-10-02 2020-01-22 新光電気工業株式会社 配線基板及びその製造方法
US9504148B1 (en) * 2015-12-02 2016-11-22 Honeywell Federal Manufacturing & Technologies, Llc Rapid PCB prototyping by selective adhesion
KR101805785B1 (ko) * 2016-05-17 2017-12-07 (주)포인트엔지니어링 칩 실장용 기판 제조방법과 칩 실장용 기판
DE102017115252A1 (de) 2017-07-07 2019-01-10 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Schichtstapels und Schichtstapel
US10103107B1 (en) 2017-08-08 2018-10-16 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
TWI719241B (zh) * 2017-08-18 2021-02-21 景碩科技股份有限公司 可做電性測試的多層電路板及其製法
CN117320265A (zh) 2018-03-28 2023-12-29 大日本印刷株式会社 布线基板、半导体装置以及布线基板的制作方法
US11569160B2 (en) * 2018-06-06 2023-01-31 Intel Corporation Patterning of dual metallization layers
CN110783728A (zh) * 2018-11-09 2020-02-11 广州方邦电子股份有限公司 一种柔性连接器及制作方法
JP7525612B2 (ja) * 2020-07-29 2024-07-30 京セラ株式会社 回路基板およびその製造方法
KR20220098528A (ko) * 2021-01-04 2022-07-12 삼성전기주식회사 인쇄회로기판
KR20220109642A (ko) * 2021-01-29 2022-08-05 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
US20220312591A1 (en) * 2021-03-26 2022-09-29 Juniper Networks, Inc. Substrate with conductive pads and conductive layers
JP7569743B2 (ja) * 2021-04-19 2024-10-18 イビデン株式会社 配線基板
CN113286439A (zh) * 2021-07-22 2021-08-20 深圳市志金电子有限公司 一种内置引线电镀线路板制作方法
CN113873762B (zh) * 2021-09-24 2023-10-03 江门崇达电路技术有限公司 一种具有沉镍金及抗氧化两种表面处理的pcb及其制作方法
CN119965193A (zh) * 2025-02-08 2025-05-09 宏茂微电子(上海)有限公司 一种多芯片堆叠封装结构及封装方法

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3085658B2 (ja) 1997-08-28 2000-09-11 京セラ株式会社 配線基板及びその製造方法
CN100426491C (zh) * 1997-10-17 2008-10-15 揖斐电株式会社 封装基板
DE69936235T2 (de) 1998-02-26 2007-09-13 Ibiden Co., Ltd., Ogaki Mehrschichtige Leiterplatte mit gefüllten Kontaktlöchern
JPH11243280A (ja) 1998-02-26 1999-09-07 Ibiden Co Ltd フィルドビア構造を有する多層プリント配線板
JP4321913B2 (ja) * 1999-05-24 2009-08-26 イビデン株式会社 プリント配線板
JP4129665B2 (ja) * 1999-10-12 2008-08-06 日本サーキット工業株式会社 半導体パッケージ用基板の製造方法
KR100311975B1 (ko) * 1999-12-16 2001-10-17 윤종용 반도체소자 및 그 제조방법
JP3546961B2 (ja) * 2000-10-18 2004-07-28 日本電気株式会社 半導体装置搭載用配線基板およびその製造方法、並びに半導体パッケージ
KR100499006B1 (ko) 2002-12-30 2005-07-01 삼성전기주식회사 도금 인입선이 없는 패키지 기판의 제조 방법
US20050067378A1 (en) * 2003-09-30 2005-03-31 Harry Fuerhaupter Method for micro-roughening treatment of copper and mixed-metal circuitry
JP4108643B2 (ja) 2004-05-12 2008-06-25 日本電気株式会社 配線基板及びそれを用いた半導体パッケージ
JP2006186321A (ja) * 2004-12-01 2006-07-13 Shinko Electric Ind Co Ltd 回路基板の製造方法及び電子部品実装構造体の製造方法
TWI281840B (en) * 2005-05-09 2007-05-21 Phoenix Prec Technology Corp Electrically connecting structure of circuit board and method for fabricating same
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
TWI279897B (en) 2005-12-23 2007-04-21 Phoenix Prec Technology Corp Embedded semiconductor chip structure and method for fabricating the same
US7906850B2 (en) 2005-12-20 2011-03-15 Unimicron Technology Corp. Structure of circuit board and method for fabricating same
TWI295550B (en) 2005-12-20 2008-04-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
US7659193B2 (en) 2005-12-23 2010-02-09 Phoenix Precision Technology Corporation Conductive structures for electrically conductive pads of circuit board and fabrication method thereof
JP2007173727A (ja) * 2005-12-26 2007-07-05 Shinko Electric Ind Co Ltd 配線基板の製造方法
CN101507373A (zh) * 2006-06-30 2009-08-12 日本电气株式会社 布线板、使用布线板的半导体器件、及其制造方法
DE102006052202B3 (de) * 2006-11-06 2008-02-21 Infineon Technologies Ag Halbleiterbauelement sowie Verfahren zur Herstellung eines Halbleiterbauelements
JP5214139B2 (ja) 2006-12-04 2013-06-19 新光電気工業株式会社 配線基板及びその製造方法
US20080268632A1 (en) * 2007-04-30 2008-10-30 Fupo Electronics Corporation. LED epiwafer pad manufacturing process & new construction thereof
JP5101169B2 (ja) * 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
KR100896810B1 (ko) * 2007-10-16 2009-05-11 삼성전기주식회사 인쇄회로기판 및 그 제조방법

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US20130153271A1 (en) 2013-06-20
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JP2010067887A (ja) 2010-03-25
US9024207B2 (en) 2015-05-05

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