JP5001903B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5001903B2
JP5001903B2 JP2008139680A JP2008139680A JP5001903B2 JP 5001903 B2 JP5001903 B2 JP 5001903B2 JP 2008139680 A JP2008139680 A JP 2008139680A JP 2008139680 A JP2008139680 A JP 2008139680A JP 5001903 B2 JP5001903 B2 JP 5001903B2
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Prior art keywords
wiring
insulating layer
wiring board
layer
semiconductor device
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Expired - Fee Related
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JP2008139680A
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English (en)
Japanese (ja)
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JP2009289908A5 (https=
JP2009289908A (ja
Inventor
三香子 岡田
智和 石川
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2008139680A priority Critical patent/JP5001903B2/ja
Priority to TW098112219A priority patent/TWI458057B/zh
Priority to US12/423,826 priority patent/US8159057B2/en
Priority to CN2009102029677A priority patent/CN101593736B/zh
Publication of JP2009289908A publication Critical patent/JP2009289908A/ja
Publication of JP2009289908A5 publication Critical patent/JP2009289908A5/ja
Priority to US13/439,992 priority patent/US8383456B2/en
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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US12/423,826 US8159057B2 (en) 2008-05-28 2009-04-15 Semiconductor device and manufacturing method therefor
CN2009102029677A CN101593736B (zh) 2008-05-28 2009-05-22 半导体装置及其制造方法
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US8383456B2 (en) 2013-02-26
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JP2009289908A (ja) 2009-12-10
CN101593736A (zh) 2009-12-02
US20090294945A1 (en) 2009-12-03
TW201010025A (en) 2010-03-01
TWI458057B (zh) 2014-10-21

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