JP6438792B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6438792B2 JP6438792B2 JP2015028403A JP2015028403A JP6438792B2 JP 6438792 B2 JP6438792 B2 JP 6438792B2 JP 2015028403 A JP2015028403 A JP 2015028403A JP 2015028403 A JP2015028403 A JP 2015028403A JP 6438792 B2 JP6438792 B2 JP 6438792B2
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Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
まず、図1〜図4を用いて本実施の形態の半導体装置の概要構成について説明する。図1は本実施の形態の半導体装置の上面図、図2は、図1に示す半導体装置の下面図である。また、図3は、図1に示す封止体を透視して、内部構造を示す透視平面図である。また、図4は、図3のA−A線に沿った断面図である。なお、図3では、封止体40の輪郭を二点鎖線で示している。
次に、図1〜図4に示す配線基板10の配線構造の詳細について説明する。本セクションでは、配線基板10の詳細な構造を説明する前に、本願発明者が見出した課題について図面を用いて説明した後、本実施の形態の配線基板10の詳細な構造について説明する。
次に、図1〜図8を用いて説明した半導体装置PKG1の製造工程について説明する。以下の説明では、製造工程の流れを示すフロー図と、図1〜図8を必要に応じて参照しながら説明する。図9は、図1〜図8を用いて説明した半導体装置の製造工程の概要を示す説明図である。なお、本実施の形態では、説明を単純化するために、図3に示す配線基板10に半導体チップ20を搭載する実施態様について説明する。しかし、変形例としては、配線基板10に相当する複数の製品形成領域を備える、所謂多数個取り基板を準備して、複数の半導体装置を一括して組立てた後、製品形成領域毎に個片化する方法もある。この場合、組立工程を効率化することができる。
まず、配線基板準備工程では、図3に示す配線基板10を準備する。本工程で準備する配線基板10には、上面(表面、チップ搭載面)10t側にチップ搭載領域(図3に示す半導体チップ20が搭載される予定領域)が設けられ、チップ搭載領域の周囲には、開口部において絶縁膜(ソルダレジスト膜)15から露出する複数のボンディングパッド14が形成されている。また、配線基板10の上面10tとは反対側の下面(裏面、実装面)10b(図4参照)には、複数のランド(端子、外部端子、外部電極)12が形成されている。本工程では、複数のランド12には、図4に示す半田ボール11は接続されず、複数のランド12のそれぞれが開口部において、絶縁膜(ソルダレジスト膜)13から露出している。
次にダイボンド工程では、図3および図4に示すように配線基板10の上面10t上に半導体チップ20を搭載する。本実施の形態では、半導体チップ20の裏面20b(図4参照)と配線基板10の上面10tとがそれぞれ対向するように、所謂、フェイスアップ実装方式で半導体チップ20を搭載する。また、図4に示す例では、半導体チップ20は、接着材50を介して配線基板10の上面10tに接着固定される。接着材50は、例えばエポキシ樹脂などの熱硬化性樹脂からなる。
次に、ワイヤボンド工程では、図3および図4に示すように、半導体チップ20の表面20tに形成された複数のパッド21と、半導体チップ20の周囲に配置された複数のボンディングパッド14とを、複数のワイヤ(導電性部材)30を介して、それぞれ電気的に接続する。
次に、封止工程では、図4に示すように、半導体チップ20、複数のワイヤ30、および複数のボンディングパッド14を樹脂により封止し、封止体40を形成する。本工程では、配線基板10の上面10t上に搭載された半導体チップ20、複数のワイヤ30、および複数のボンディングパッド14を樹脂により封止する。
次に、ボールマウント工程では、図4に示すように、配線基板10の下面10bに形成された複数のランド12に、外部端子になる複数の半田ボール11を接合する。
例えば、図5では、差動信号を伝送する配線16SG1および配線16SG2のそれぞれの一箇所に、インピーダンス不連続点となる部分PT3を設ける例を説明した。しかし、図10〜図12に示す変形例の半導体装置PKG2のように、配線16SG1および配線16SG2のそれぞれの複数箇所に、インピーダンス不連続点となる部分PT3、PT5を設けても良い。
次に、上記した変形例1と比較して、見かけ上のインピーダンスの変化をさらに緩やかにする変形例について説明する。図13は、図5に対する変形例である半導体装置の信号伝送経路周辺の拡大平面図である。また、図14は、図13に示す差動信号伝送用の配線のうち、迂回した部分の周辺を拡大して示す拡大平面図である。また、図15は、図13に示す信号伝送経路の回路図である。また、図16は、図15に示す各部材のインピーダンスの値の例を示す説明図である。
また、上記した図5、図10、図13では、差動信号を伝送する配線16SG1および配線16SG2に設けられた、インピーダンス不連続点となる部分PT3の形状が、部分PT3において、互いに離れる方向に向かって蛇行するミアンダ形状になっている例を説明した。しかし、部分PT3の形状には種々の変形例がある。図17は、図5に対する別の変形例である半導体装置の信号伝送経路周辺の拡大平面図である。また、図18は、図8に対する別の変形例である半導体装置における差動信号の伝送経路の一部を拡大して示す拡大平面図である。
また、上記した図5、図10、図13、図17、図18では、インピーダンス不連続点となる部分PT3が、並走部の間に設けられた例を説明した。部分PT3を設ける位置には種々の変形例がある。例えば、上記実施の形態や変形例1で述べたように、部分PT3を最上層の配線層以外に設けても良い。また例えば、図19に示す半導体装置PKG6が有する16SG1および配線16SG2の部分PT3のように、異なる配線層間を電気的に接続する、ビア配線16Vの近傍に部分PT3を設けても良い。図19は、図5に対する別の変形例である半導体装置の信号伝送経路周辺の拡大平面図である。
また、上記した実施の形態および各種変形例では、図4に示すように半導体チップ20と配線基板10とをワイヤ30を介して電気的に接続した実施態様について説明した。しかし、変形例としては、ワイヤ30以外の導電性部材で半導体チップ20と配線基板10とを電気的に接続した実施態様にも適用できる。図20は、図4に対する変形例である半導体装置の断面図である。また、図21は、図20に示す半導体装置の信号伝送経路周辺の拡大平面図である。また、図22は、図21に示す信号伝送経路の回路図である。また、図23は、図22に示す各部材のインピーダンスの値の例を示す説明図である。
また、例えば、上記の通り種々の変形例について説明したが、上記で説明した各変形例同士を組み合わせて適用することができる。
10b 下面(裏面、実装面)
10s 側面
10t 上面(表面、チップ搭載面)
11 半田ボール(外部端子、電極、外部電極)
12 ランド(外部端子、電極、外部電極)
13 絶縁膜(ソルダレジスト膜)
14、14SG1、14SG2 ボンディングパッド(端子、内部端子、電極、ボンディングリード、ボンディングフィンガ)
15 絶縁膜(ソルダレジスト膜)
16、16SG1、16SG2、16VS1、16VS2 配線
16T スルーホール配線
16V ビア配線
17 絶縁層
20 半導体チップ
20b 裏面(主面、下面)
20s 側面
20t 表面(主面、上面)
21、21SG1、21SG2 パッド(電極、チップ電極)
30、30SG1、30SG2 ワイヤ(導電性部材)
31 バンプ電極(導電性部材、突起電極、柱状電極)
40 封止体
50 接着材
MP1 導体パターン(ビアランド、ダミーパターン)
PKG1、PKG2、PKG3、PKG4、PKG5、PKG6、PKG7、PKGh1 半導体装置
PT1、PT2、PT4 部分(並走部)
PT3、PT5 部分(迂回部)
RTN1、RTN2、RTN3 反射信号
SIG1、SIG2 入力信号
SP1、SP2、SP3、SP12 離間距離
VL1 仮想線
Z0、Z1、ZP2、ZP3、Z4、Z5、Z21、Z22、Z23、Z24、Z25、ZS インピーダンス
Claims (16)
- 第1面、前記第1面に形成された複数の内部端子、前記第1面とは反対側の第2面、および前記第2面に形成され、かつ、前記複数の内部端子とそれぞれ電気的に接続された複数の外部端子、および前記複数の内部端子と前記複数の外部端子をそれぞれ繋ぐ複数の配線、を有する配線基板と、
複数のパッドを有し、前記配線基板の前記第1面上に搭載された半導体チップと、
前記複数のパッドと前記複数の内部端子を、それぞれ電気的に接続する複数の導電性部材と、
を含み、
前記複数のパッドは、第1パッドと、前記第1パッドの隣に位置する第2パッドと、を有し、
前記複数の内部端子は、前記複数の導電性部材のうちの第1導電性部材を介して前記第1パッドと電気的に接続される第1内部端子と、前記複数の導電性部材のうちの第2導電性部材を介して前記第2パッドと電気的に接続され、かつ、前記第1内部端子の隣に位置する第2内部端子と、を有し、
前記複数の配線は、前記第1内部端子に繋がる第1配線と、前記第2内部端子に繋がる第2配線と、を有し、
前記第1配線および前記第2配線は、差動信号を伝送する差動対を構成し、
平面視において、前記第1配線および前記第2配線のそれぞれは、
第1の離間距離で互いに並走する第1部分と、
前記第1部分と同じ配線層に設けられ、第2の離間距離で互いに並走する第2部分と、
前記第1部分と前記第2部分との間に設けられ、互いの離間距離が前記第1の離間距離および前記第2の離間距離よりも大きくなる方向に迂回して設けられた第3部分と、
を有し、
差動対を構成する前記第1配線および前記第2配線の形状は、前記第1配線と前記第2配線の中央の第1仮想線に対して、線対称な形状になっている、半導体装置。 - 請求項1において、
前記第1配線と前記第2配線とには、それぞれ反対極性の信号電流が流れる、半導体装置。 - 請求項1において、
前記第1部分、前記第2部分、および前記第3部分は、前記複数の内部端子と同じ配線層に形成されている、半導体装置。 - 請求項1において、
前記第1配線および前記第2配線のそれぞれは、前記第3部分において、互いに離れる方向に向かって蛇行している、半導体装置。 - 請求項1において、
前記第1配線および前記第2配線がそれぞれ有する前記第3部分は、前記第1部分に対して交差する方向に延びる交差部分と、前記第1部分または前記第2部分と並走するように延びる並走部分と、をさらに有する、半導体装置。 - 請求項1において、
前記第3部分のインピーダンスは、前記半導体チップのインピーダンスよりも小さい、半導体装置。 - 請求項1において、
前記第1の離間距離と前記第2の離間距離は互いに等しい、半導体装置。 - 請求項1において、
前記複数の配線は、前記第1配線の隣に前記第1配線に沿って設けられ、前記半導体チップに基準電位を供給する第1基準電位配線と、前記第2配線の隣に前記第2配線に沿って設けられ、前記半導体チップに基準電位を供給する第2基準電位配線と、を有し、
前記第1配線および前記第2配線は、前記第1基準電位配線および前記第2基準電位配線の間に配置されている、半導体装置。 - 請求項1において、
前記複数の導電性部材は、ワイヤである、半導体装置。 - 請求項9において、
前記第3部分のインピーダンスは、前記ワイヤのインピーダンスよりも小さい、半導体装置。 - 請求項1において、
前記第1配線および前記第2配線のそれぞれは、
前記第1部分と前記第3部分との間に設けられ、第3の離間距離で互いに並走する第4部分と、
前記第4部分と前記第1部分との間に設けられ、互いの離間距離が前記第1の離間距離、前記第2の離間距離、および前記第3の離間距離よりも大きくなる方向に迂回して設けられた第5部分と、
をさらに有する、半導体装置。 - 請求項11において、
前記第1部分、前記第2部分、前記第3部分、前記第4部分、および前記第5部分は、前記複数の内部端子と同じ配線層に形成されている、半導体装置。 - 請求項12において、
前記第1配線および前記第2配線がそれぞれ有する前記第3部分および前記第5部分は、前記第1部分に対して交差する方向に延びる交差部分と、前記第1部分、前記第2部分、または前記第4部分と並走するように延びる並走部分と、をさらに有する、半導体装置。 - 請求項13において、
前記第5部分は、前記第3部分よりも前記第1内部端子または前記第2内部端子に近い位置に設けられ、
前記第5部分の並走部分の長さは、前記第3部分の並走部分の長さよりも長い、半導体装置。 - 請求項8において、
前記第1配線および前記第2配線がそれぞれ有する前記第3部分の間には、前記第1配線および前記第2配線と分離した第1導体パターンが形成されている、半導体装置。 - 第1面、前記第1面に形成された複数の内部端子、前記第1面とは反対側の第2面、および前記第2面に形成され、かつ、前記複数の内部端子とそれぞれ電気的に接続された複数の外部端子、および前記複数の内部端子と前記複数の外部端子をそれぞれ繋ぐ複数の配線、を有する配線基板と、
複数のパッドを有し、前記配線基板の前記第1面上に搭載された半導体チップと、
前記複数のパッドと前記複数の内部端子を、それぞれ電気的に接続する複数の導電性部材と、
を含み、
前記複数のパッドは、第1パッドと、前記第1パッドの隣に位置する第2パッドと、を有し、
前記複数の内部端子は、前記複数の導電性部材のうちの第1導電性部材を介して前記第1パッドと電気的に接続される第1内部端子と、前記複数の導電性部材のうちの第2導電性部材を介して前記第2パッドと電気的に接続され、かつ、前記第1内部端子の隣に位置する第2内部端子と、を有し、
前記複数の配線は、差動信号を伝送する差動対を構成し、前記第1内部端子に繋がる第1配線と、前記第2内部端子に繋がる第2配線と、を有し、
平面視において、前記第1配線および前記第2配線のそれぞれは、
第1の離間距離で互いに並走する第1部分と、
前記第1部分と同じ配線層に設けられ、互いの離間距離が前記第1の離間距離よりも大きくなる方向に迂回して設けられた第2部分と、
を有し、
前記第1配線および前記第2配線のそれぞれは、前記第2部分において、互いに離れる方向に向かって蛇行している、半導体装置。
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