JP4241302B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4241302B2 JP4241302B2 JP2003340741A JP2003340741A JP4241302B2 JP 4241302 B2 JP4241302 B2 JP 4241302B2 JP 2003340741 A JP2003340741 A JP 2003340741A JP 2003340741 A JP2003340741 A JP 2003340741A JP 4241302 B2 JP4241302 B2 JP 4241302B2
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- semiconductor device
- semiconductor
- manufacturing
- electrode pads
- wiring
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Description
(1)半導体装置の製造方法であって、
半導体ウエハの主面に、回路および複数の第1の電極パッドを有する複数の製品形成領域を形成する工程と、
前記各製品形成領域に、前記第1の電極パッドよりも配列ピッチが広い複数の第2の電極パッドを再配置する工程と、
前記半導体ウエハの複数の製品形成領域を個片化して、第1の面側に、前記回路、前記複数の第1の電極パッド、前記複数の第2の電極パッドを有する複数の半導体装置を形成する工程と、
前記複数の製品形成領域を個片化する工程の後、前記半導体装置の第1の面に付着する異物を洗浄にて除去する工程とを有する。
(2)前記手段(1)において、
前記洗浄工程は、前記半導体装置の第1の面に複数の粉砕状ドライアイスを吹き付けて行う。
(3)前記手段(2)において、
前記粉砕状ドライアイスは、0.1mm乃至0.3mmの粒径サイズからなる。
(4)前記手段(1)において、
更に、前記複数の製品形成領域を個片化する工程の前、前記各製品形成領域の第2の電極パッド上にバンプを形成する工程を有する。
(5)前記手段(1)において、
更に、前記半導体装置をソケットに装着してバーンインを行う工程を有する。
(6)前記手段(5)において、
前記複数の製品形成領域を個片化する工程は、クリーンルームで行い、
前記バーンイン工程は、非クリーンルームで行う。
(7)前記手段(1)において、
更に、前記半導体装置をソケットに装着して特性評価試験を行う工程を有する。
(8)前記手段(7)において、
前記複数の製品形成領域を個片化する工程は、クリーンルームで行い、
前記特性選別試験は、非クリーンルームで行う。
(9)半導体装置の製造方法において、
分離領域で区画された複数の製品形成領域を有し、前記複数の製品形成領域の夫々は、互いに反対側に位置する第1の面および第2の面と、前記第2の面に配置された複数の電極パッドとを有する多数個取り基板を準備する工程と、
前記複数の製品形成領域の夫々の第1の面に半導体チップを実装する工程と、
前記複数の製品形成領域に実装された前記複数の半導体チップを一括して樹脂封止する樹脂封止体を形成する工程と、
前記樹脂封止体および前記多数個取り基板を複数の個片に分割して、前記製品形成領域からなる配線基板と、前記配線基板の第1の面に実装された前記半導体チップと、前記半導体チップを樹脂封止した樹脂封止体とを有する複数の半導体装置を形成する工程と、
前記配線基板の第1の面と反対側の第2の面に付着する異物を洗浄にて除去する工程とを有する。
(10)前記手段(9)において、
前記洗浄工程は、前記半導体装置の第1の面に複数の粉砕状ドライアイスを吹き付けて行う。
(11)前記手段(10)において、
前記粉砕状ドライアイスは、0.1mm乃至0.3mmの粒径サイズからなる。
(12)前記手段(9)において、
更に、前記複数の製品形成領域を個片化する工程の前、前記各製品形成領域の第2の面の電極パッド上にバンプを形成する工程を有する。
(13)前記手段(9)において、
更に、前記半導体装置をソケットに装着してバーンインを行う工程を有する。
(14)前記手段(9)において、
更に、前記半導体装置をソケットに装着して特性評価試験を行う工程を有する。
本実施形態1では、ウエハ・レベルCSP型半導体装置に本発明を適用した例について説明する。
図2は、本実施形態1の半導体装置の内部構造を示す要部模式的断面図であり、
図3は、本実施形態1の半導体装置の実装面側の配線パターンを示す要部模式的平面図であり、
図4は、本実施形態1の半導体装置の製造工程を示すフローチャートであり、
図5は、本実施形態1の半導体装置の製造に使用される半導体ウエハの模式的平面図であり、
図6乃至図13は、本実施形態1の半導体装置の製造工程を示す模式的平面図であり、
図14は、半導体装置の実装面に異物が付着した状態を示す模式的平面図であり、
図15は、本実施形態1の半導体装置の製造に使用される自動異物洗浄装置の概略構成を示す図であり、
図16は、ドライアイス洗浄を説明するための模式図であり、
図17は、エアブロー洗浄を説明するための模式図であり、
図18は、ブラスト洗浄を説明するための模式図であり、
図19は、ウエット洗浄を説明するための模式図である。
(実施形態2)
本実施形態2では、チップ・レベルCSP型半導体装置に本発明を適用した例について説明する。
図21は、本実施形態2の半導体装置の実装面側の構造を示す模式的平面図であり、
図22は、本実施形態2の半導体装置の実装面側の配線パターンを示す要部模式的平面図であり、
図23は、本実施形態2の半導体装置の製造に使用される多数個取り基板の模式的平面図であり、
図24は、図23の多数個取り基板の要部模式的断面図であり、
図25は、本実施形態2の半導体装置の製造工程を示すフローチャートであり、
図26乃至図30は、本実施形態2の半導体装置の製造工程を示す要部模式的断面図である。
10…半導体ウエハ、11…分離領域(スクライブ領域)、12…製品形成領域(デバイス形成領域)、
20…自動異物洗浄装置、21…液化炭素、22…ペレタイザ、23…ペレット状ドライアイス、24…粉砕機、25…粉砕状ドライアイス、26…洗浄装置、26a…ノズル、27…集塵ユニット、28…異物、29a,29b…トレイ、
30…半導体装置、31…半導体チップ、32…配線基板(インターポーザ)、32a,32b…電極パッド、32c,32d…保護膜、32h…スルーホール配線のランド部、33…接着材、34…ボンディングワイヤ、35…樹脂封止体、36…半田バンプ、
40…多数個取り基板、41…モールド領域、42…分離領域、43…製品形成領域(デバイス形成領域)、44…チップ搭載領域
Claims (7)
- (a)半導体ウエハの主面に、回路および複数の第1の電極パッドを有する製品形成領域を複数形成する工程と、
(b)前記製品形成領域のそれぞれに、前記第1の電極パッドよりも配列ピッチが広い複数の第2の電極パッドを、再配線を介して再配置する工程と、
(c)前記複数の第2の電極パッドに複数のバンプ電極をそれぞれ形成する工程と、
(d)前記複数の製品形成領域のうち、互いに隣り合う製品形成領域の間をダイシングすることで、複数の半導体装置を取得する工程と、
(e)前記複数の半導体装置をそれぞれテストする工程と、
(f)前記複数の半導体装置のそれぞれに複数の粉砕状ドライアイスを吹き付けて洗浄する工程とを有することを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記バンプ電極は、Pbフリー材で形成されていることを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記粉砕状ドライアイスは、0.1mm乃至0.3mmの粒径サイズからなることを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(e)工程では、前記半導体装置をソケットに装着し、前記ソケット内に設けられた複数のコンタクトピンに前記半導体装置の前記バンプ電極を圧接することによって行うことを特徴とする半導体装置の製造方法。 - 請求項4に記載の半導体装置の製造方法において、
前記(e)工程は、バーンイン工程であることを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(d)工程の前にプローブ検査を行うことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(f)工程の後、
(g)前記半導体装置の最終外観検査を行う工程と、
(h)前記半導体装置を梱包する工程と、
(i)前記半導体装置を出荷する工程と、
を有することを特徴とする半導体装置の製造方法。
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JP2003340741A JP4241302B2 (ja) | 2003-09-30 | 2003-09-30 | 半導体装置の製造方法 |
TW093127206A TWI357098B (en) | 2003-09-30 | 2004-09-08 | A method of manufacturing a semiconductor device |
KR1020040076828A KR101085244B1 (ko) | 2003-09-30 | 2004-09-24 | 반도체 장치의 제조 방법 |
CNA2004100805473A CN1607637A (zh) | 2003-09-30 | 2004-09-28 | 制造半导体器件的方法 |
US10/953,955 US7534657B2 (en) | 2003-09-30 | 2004-09-30 | Method of manufacturing a semiconductor device |
US12/466,046 US7985625B2 (en) | 2003-09-30 | 2009-05-14 | Method of manufacturing a semiconductor device |
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JP4519571B2 (ja) * | 2004-08-26 | 2010-08-04 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその検査方法と検査装置並びに半導体装置の製造方法 |
JP2007123413A (ja) * | 2005-10-26 | 2007-05-17 | Elpida Memory Inc | 半導体装置の製造方法 |
JP4719009B2 (ja) * | 2006-01-13 | 2011-07-06 | ルネサスエレクトロニクス株式会社 | 基板および半導体装置 |
DE102006008050A1 (de) * | 2006-02-21 | 2007-08-23 | Imi Intelligent Medical Implants Ag | Vorrichtung mit flexiblem Mehrschichtsystem zur Kontaktierung oder Elektrostimulation von lebenden Gewebezellen oder Nerven |
JP5304232B2 (ja) * | 2008-02-01 | 2013-10-02 | セイコーエプソン株式会社 | 電気光学装置の製造方法 |
US8318540B2 (en) * | 2008-05-19 | 2012-11-27 | Infineon Technologies Ag | Method of manufacturing a semiconductor structure |
JP5001903B2 (ja) * | 2008-05-28 | 2012-08-15 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
TWI372453B (en) * | 2008-09-01 | 2012-09-11 | Advanced Semiconductor Eng | Copper bonding wire, wire bonding structure and method for processing and bonding a wire |
US8110931B2 (en) * | 2008-07-11 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Wafer and semiconductor package |
JP5126370B2 (ja) * | 2008-12-16 | 2013-01-23 | 株式会社村田製作所 | 回路モジュール |
JP5175803B2 (ja) * | 2009-07-01 | 2013-04-03 | 新光電気工業株式会社 | 半導体装置の製造方法 |
MY152434A (en) * | 2009-08-18 | 2014-09-30 | Multitest Elektronische Syst | System for post-processing of electronic components |
JP6437012B2 (ja) * | 2014-11-27 | 2018-12-12 | 国立研究開発法人産業技術総合研究所 | 表面実装型パッケージおよびその製造方法 |
KR102341732B1 (ko) | 2015-01-30 | 2021-12-23 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
JP6705727B2 (ja) * | 2016-09-26 | 2020-06-03 | ファスフォードテクノロジ株式会社 | フリップチップボンダおよび半導体装置の製造方法 |
JP2019186464A (ja) * | 2018-04-16 | 2019-10-24 | 株式会社ブイ・テクノロジー | 配線修正装置および配線修正方法 |
WO2020073901A1 (en) * | 2018-10-11 | 2020-04-16 | Changxin Memory Technologies, Inc. | Semiconductor structure, memory device, semiconductor device and method of manufacturing the same |
US11723154B1 (en) * | 2020-02-17 | 2023-08-08 | Nicholas J. Chiolino | Multiwire plate-enclosed ball-isolated single-substrate silicon-carbide-die package |
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US6111317A (en) * | 1996-01-18 | 2000-08-29 | Kabushiki Kaisha Toshiba | Flip-chip connection type semiconductor integrated circuit device |
KR100267155B1 (ko) * | 1996-09-13 | 2000-10-16 | 아끼구사 나오유끼 | 반도체 장치의 제조 방법 및 제조 장치 |
US6039059A (en) * | 1996-09-30 | 2000-03-21 | Verteq, Inc. | Wafer cleaning system |
JP3481444B2 (ja) * | 1998-01-14 | 2003-12-22 | シャープ株式会社 | 半導体装置及びその製造方法 |
TW478089B (en) * | 1999-10-29 | 2002-03-01 | Hitachi Ltd | Semiconductor device and the manufacturing method thereof |
JP3878430B2 (ja) | 2001-04-06 | 2007-02-07 | 株式会社ルネサステクノロジ | 半導体装置 |
JP4790157B2 (ja) * | 2001-06-07 | 2011-10-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7169691B2 (en) * | 2004-01-29 | 2007-01-30 | Micron Technology, Inc. | Method of fabricating wafer-level packaging with sidewall passivation and related apparatus |
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JP2005109156A (ja) | 2005-04-21 |
KR101085244B1 (ko) | 2011-11-22 |
KR20050031944A (ko) | 2005-04-06 |
TWI357098B (en) | 2012-01-21 |
US20090221104A1 (en) | 2009-09-03 |
US20050085009A1 (en) | 2005-04-21 |
US7534657B2 (en) | 2009-05-19 |
TW200524017A (en) | 2005-07-16 |
US7985625B2 (en) | 2011-07-26 |
CN1607637A (zh) | 2005-04-20 |
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