US20050121805A1 - Semiconductor device and a method of manufacturing the same - Google Patents
Semiconductor device and a method of manufacturing the same Download PDFInfo
- Publication number
- US20050121805A1 US20050121805A1 US11/035,999 US3599905A US2005121805A1 US 20050121805 A1 US20050121805 A1 US 20050121805A1 US 3599905 A US3599905 A US 3599905A US 2005121805 A1 US2005121805 A1 US 2005121805A1
- Authority
- US
- United States
- Prior art keywords
- semiconductor chip
- bonding
- electrode pads
- wires
- bonding pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Definitions
- the present invention relates to a semiconductor device and a production technology for the same and, specifically, to a semiconductor device having a face-up bonding structure and a technology which is effectively applied to a production technology for the same.
- BGA All Grid Array
- BGA type semiconductor devices having different structures have been developed and commercialized.
- the structures of the BGA type semiconductor devices are roughly divided into a face-up bonding structure (wire bonding structure) and a face-down bonding structure.
- a face-up bonding structure electrode pads arranged on the main surface (circuit formation surface) of the semiconductor chip and electrode pads (connecting portions which are parts of wirings) arranged on the main surface of the interposer are electrically connected by bonding wires.
- electrode pads arranged on the main surface of the semiconductor chip and electrode pads arranged on the main surface of the interposer are electrically connected by solder bumps interposed between the electrode pads.
- the BGA type semiconductor device having a face-up bonding structure is disclosed by Japanese Unexamined Patent Publication No. 2001-144214, for example.
- the BGA type semiconductor device having a face-down bonding structure is disclosed by Japanese Unexamined Patent Publication No. Hei 6(1994)-34983, for example.
- the plane sizes of the semiconductor chip and the interposer must be reduced.
- the pitch of the electrode pads arranged on the main surface of the semiconductor chip must be reduced.
- the pitch of the electrode pads arranged on the main surface of the interposer must be reduced.
- the interval between adjacent bonding wires is also narrowed.
- a short circuit easily occurs between adjacent bonding wires due to “the flowing of the wires” that the bonding wires are deformed by a flow of a resin at the time of forming a resin sealing body by a transfer molding method. Therefore, in order to downsize the BGA type semiconductor device having a face-up bonding structure, a short circuit between adjacent bonding wires must be suppressed.
- the present invention relates to the following.
- FIG. 1 is a plan view showing the internal structure of a semiconductor device according to Embodiment 1 of the present invention.
- FIG. 2 is a sectional view along line A-A of FIG. 1 ;
- FIG. 3 is a partially enlarged plan view of FIG. 1 ;
- FIGS. 4 (A) to 4 (C) are diagrams showing the internal structure of the semiconductor device of Embodiment 1, in which FIG. 4 (A) is a sectional view along line B-B of FIG. 3 , FIG. 4 (B) is a sectional view along line C-C of FIG. 3 , and FIG. 4 (C) is a sectional view obtained by combining FIG. 4 (A) with FIG. 4 (B);
- FIG. 5 is a partially enlarged plan view of FIG. 3 ;
- FIG. 6 is a plan view showing the schematic constitution of a multiple panel used for the production of the semiconductor device of Embodiment 1;
- FIG. 7 is a plan view showing that a chip bonding step is carried out in the production of the semiconductor device of Embodiment 1;
- FIG. 8 is a plan view showing that a first wire bonding step is carried out in the production of the semiconductor device of Embodiment 1;
- FIG. 9 is a partially enlarged plan view of FIG. 8 ;
- FIG. 10 is a plan view showing that a second wire bonding step is carried out in the production of the semiconductor device of Embodiment 1;
- FIG. 11 is a partially enlarged plan view of FIG. 10 ;
- FIG. 12 is a sectional view showing that a multiple panel is positioned in a mold in the molding step of the production of the semiconductor device of Embodiment 1;
- FIG. 13 is a plan view showing that a resin flows in the cavity of the mold in the molding step of the production of the semiconductor device of Embodiment 1;
- FIG. 14 is a plan view showing that the molding step is carried out in the production of the semiconductor device of Embodiment 1;
- FIG. 15 is a plan view showing that a cutting step is carried out in the production of the semiconductor device of Embodiment 1;
- FIG. 16 is a plan view of a semiconductor wafer of Embodiment 1;
- FIG. 17 is a partially enlarged plan view of FIG. 16 ;
- FIG. 18 is a partially enlarged plan view of FIG. 17 ;
- FIG. 19 is a diagram for explaining a characteristic inspection step in the production of the semiconductor device of Embodiment 1;
- FIG. 20 is a diagram showing the positions of connecting portions when the electrode pads of the semiconductor chip and the one end portions of the bonding wires are connected to each other in a zigzag manner;
- FIG. 21 is a diagram showing the positions of connecting portions when the electrode pads of the semiconductor chip and the one end portions of the bonding wires are connected to each other linearly;
- FIG. 22 is a plan view of the key section of a semiconductor device according to Embodiment 2 of the present invention.
- FIG. 23 is a plan view of the key section of the semiconductor chip of FIG. 22 ;
- FIG. 24 is a partial plan view showing the internal structure of a semiconductor device according to Embodiment 3 of the present invention.
- FIG. 25 is a sectional view of the key section corresponding to FIG. 24 .
- Embodiment 1 a BGA type semiconductor device having a face-up bonding structure to which the present invention is applied will be described hereinbelow.
- FIG. 1 is a plan view showing the internal structure of a BGA type semiconductor device having a face-up bonding structure according to Embodiment 1 of the present invention
- FIG. 2 is a sectional view along line A-A of FIG. 1
- FIG. 3 is a partially enlarged plan view of FIG. 1
- FIGS. 4 (A) to 4 (C) are diagrams showing the internal structure of the semiconductor device according to Embodiment 1 ( FIG. 4 (A) is a sectional view along line B-B of FIG. 3
- FIG. 4 (B) is a sectional view along line C-C of FIG. 3
- FIG. 4 (C) is a sectional view obtained by combining FIG. 4 (A) with FIG. 4 (B))
- FIG. 5 is a partially enlarged view of FIG. 3 .
- the BGA type semiconductor device 1 has a package structure that a semiconductor chip 2 is mounted on the main surface 4 ⁇ out of the main surface 4 ⁇ and the rear surface 4 y located on the opposite sides of an interposer 4 (opposite main surface 4 ⁇ and rear surface 4 y ) and a plurality of ball-like solder bumps 10 are arranged as external connection terminals on the rear surface 4 y of the interposer 4 .
- the semiconductor chip 2 has a square plane which is perpendicular to its thickness direction, for example, a 5.0 mm ⁇ 5.0 mm plane in this embodiment.
- the semiconductor chip 2 is mainly composed of a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, a multi-layered wiring laminate consisting of a plurality of insulating layers and a plurality of wiring layers formed on the main surface of the semiconductor substrate, and a surface protective film (final protective film) formed on the multi-layered wiring laminate, though it is not limited to this structure.
- the insulating layers are each formed of a silicon oxide film, for example.
- the wiring layers are each formed of a metal film such as an aluminum (Al), aluminum alloy, copper (Cu) or copper alloy film.
- the surface protective film is formed of a multi-layer laminate film consisting of an inorganic insulating film such as silicon oxide film or silicon nitride film and an organic insulating film.
- the semiconductor chip 2 has a main surface (circuit formation surface) 2 ⁇ and a rear surface 2 y which are located on opposite sides, and an integrated circuit, for example, a control circuit is formed on the main surface 2 ⁇ of the semiconductor chip 2 .
- This control circuit is mainly composed of transistor elements formed on the main surface of the semiconductor substrate and wirings formed on the multi-layered wiring laminate.
- the semiconductor chip 2 is fixed to the main surface 4 ⁇ of the interposer 4 by an adhesive 7 interposed between the rear surface 2 y thereof and the main surface 4 ⁇ of the interposer 4 .
- Electrodes pads 3 are arranged on the main surface of the semiconductor chip 2 .
- the electrode pads 3 of a first group are arranged along the first side 2 ⁇ 22 of the semiconductor chip 2
- the electrode pads 3 of a second group are arranged along the second side 2 ⁇ 2 of the semiconductor chip 2
- the electrode pads 3 of a third group are arranged along the third side 2 ⁇ 3 of the semiconductor chip 3
- the electrode pads 3 of a fourth group are arranged along the fourth side 2 ⁇ 4 of the semiconductor chip 2 .
- the electrode pads 3 of all the groups are formed on the uppermost wiring layer out of the multi-layered wiring laminate of the semiconductor chip 2 and exposed from bonding openings formed in the surface protective film of the semiconductor chip 2 corresponding to the respective electrode pads 3 .
- the interposer 4 has a square plane which is perpendicular to its thickness direction, for example, a 13.0 mm ⁇ 13.0 mm plane in this embodiment.
- the interposer 4 is mainly composed of a core material, a protective film formed to cover the main surface of the core material and a protective film formed to cover the rear surface (surface opposite to the main surface of the core material) opposite to the main surface of the core material, though it is not limited to this structure.
- the core material has a multi-layered wiring structure comprising wirings in the main surface, rear surface and interior thereof.
- Each insulating layer of the core material is formed of a highly elastic resin substrate made from glass fibers impregnated with an epoxy-based or polyimide-based resin.
- Each wiring layer of the core material is formed of a metal film essentially composed of Cu, for example.
- the protective film on the main surface of the core material is formed to protect mainly wirings formed in the uppermost wiring layer of the core material and the protective film on the rear surface of the core material is formed to protect mainly wirings formed in the lowermost wiring layer of the core material.
- As the protective films on the main surface and the rear surface of the core material are used an insulating film made from a two-liquid alkali developing solder resist ink or thermosetting one-liquid solder resist ink.
- Electrodes pads 5 are arranged around the semiconductor chip 2 on the main surface 4 ⁇ of the interposer 4 .
- the electrode pads 5 of a first group are arranged along the first side 2 ⁇ of the semiconductor chip 2
- the electrode pads 5 of a second group are arranged along the second side 2 ⁇ 2 of the semiconductor chip 2
- the electrode pads 5 of a third group are arranged along the third side 2 ⁇ 3 of the semiconductor chip 2
- the electrode pads 5 of a fourth group are arranged along the fourth side 2 ⁇ 4 of the semiconductor chip 2 .
- the electrode pads 5 of all the groups are formed with parts of the plural wirings formed in the uppermost wiring layer of the core material and exposed from openings formed in the protective film on the main surface of the core material corresponding to the respective electrode pads 5 .
- a plurality of electrode pads 6 are formed on the rear surface 4 y of the interposer 4 .
- the plural electrode pads 6 are formed with part of the plural wirings formed in the lowermost wiring layer of the core material and exposed from openings formed in the protective film on the rear surface of the core material corresponding to the respective electrode pads 6 .
- the electrode pads 3 of the first group of the semiconductor chip 2 and the electrode pads 5 of the first group of the interposer 4 are electrically connected to each other by bonding wires 8 of a first group, respectively.
- the electrode pads 3 of the second group of the semiconductor chip 2 and the electrode pads 5 of the second group of the interposer 4 are electrically connected to each other by bonding wires 8 of a second group, respectively.
- the electrode pads 3 of the third group of the semiconductor chip 2 and the electrode pads 5 of the third group of the interposer 4 are electrically connected to each other by bonding wires 8 of a third group, respectively.
- the electrode pads 3 of the fourth group of the semiconductor chip 2 and the electrode pads 5 of the fourth group of the interposer 4 are electrically connected to each other by bonding wires 8 of a fourth group, respectively.
- the bonding wires 8 are gold (Au) wires, for example.
- the bonding wires 8 are connected by a nail head bonding (ball bonding) method making use of ultrasonic vibration for thermal contact bonding.
- the bonding wires 8 of all the groups are connected by the nail head bonding method in which the electrode pads 3 of the semiconductor chip 2 are used as first bonding points and the electrode pads 5 of the interposer 4 are used as second bonding points.
- the semiconductor chip 2 and the plural bonding wires 8 of all the groups are sealed up with a resin sealing body 9 formed on the main surface 4 ⁇ of the interposer 4 .
- the resin sealing body 9 is formed from an epoxy-based thermosetting insulating resin containing a phenolic curing agent, silicone rubber and a large number of fillers (such as silica) to reduce stress.
- a transfer molding method which is suitable for mass-production is used to form the resin sealing body 9 .
- the plural solder bumps 10 are fixed and electrically and mechanically connected to the respective electrode pads 6 formed on the rear surface 4 y of the interposer 4 .
- the solder bumps 10 are Pb-free solder bumps which contain substantially no Pb, for example, Sn-1[wt %]Ag-0.5[wt %]Cu solder bumps.
- the electrode pads of the first group of the semiconductor chip 2 have a rectangular plane form that their two long opposite sides extend in a direction away from the first side 2 ⁇ of the semiconductor chip 2 and their two short opposite sides extend along the first side 2 ⁇ 1 of the semiconductor chip 2 .
- the electrode pads 3 of the second group, the electrode pads 3 of the third group and the electrode pads 3 of the fourth group of the semiconductor chip 2 have a rectangular plane form that their two long opposite sides extend in a direction away from the respective sides (second side 2 ⁇ 2, third side 2 ⁇ 3, fourth side 2 ⁇ 4) of the semiconductor chip 2 and their two short opposite sides extend along the respective sides (second side 2 ⁇ 2, third side 2 ⁇ 3, fourth side 2 ⁇ 4) of the semiconductor chip 2 .
- the bonding wires 8 of the first group include first bonding wires 8 a having one end portions 8 a 1 connected to the first electrode pads 3 a out of the electrode pads 3 of the first group of the semiconductor chip 2 and the other end portions 8 a 2 opposite to the one end portions 8 a 1 and connected to the first electrode pads 5 a out of the electrode pads 5 of the first group of the interposer 4 as shown in FIG. 3 and FIG.
- the loop height 14 a (see FIG. 4 (A)) of the first bonding wires 8 a is lower than the loop height 14 b of the second bonding wires 8 b.
- the one end portion 8 b 1 of the second bonding wire 8 b is connected at a position farther from the first side 2 ⁇ of the semiconductor chip than the one end portion 8 a 1 of the first bonding wire 8 a
- the other end portion 8 b 2 of the second bonding wire 8 b is connected at a position farther from the first side 2 ⁇ of the semiconductor chip 2 than the other end portion 8 a 2 of the first bonding wire 8 a.
- a short circuit between adjacent bonding wires can be suppressed by changing the loop height of one of them.
- an overlapped portion between the bonding wires in the arrangement direction of the bonding wires is formed on one end sides and the other end sides of the bonding wires in this case, a short circuit between the intermediate portions of the bonding wires can be suppressed but it is difficult to suppress a short circuit on one end sides and the other end sides.
- a short circuit on one end sides and the other end sides of the bonding wires can be suppressed.
- the plane sizes of the semiconductor chip and the interposer must be reduced.
- the pitches of the electrode pads arranged on the main surfaces of the semiconductor chip and the interposer must be reduced.
- a bonding wire having a small diameter must be used. Since the bonding wire having a small diameter has low mechanical strength, it is easily deformed on one end side and the other end side thereof.
- the pitches of the electrode pads of the semiconductor chip and the interposer are reduced, the interval between adjacent bonding wires is narrowed, whereby a short circuit easily occurs on one end sides and the other end sides of the bonding wires.
- the BGA type semiconductor device 1 can be downsized.
- the electrode pads 3 of the first group of the semiconductor chip 2 consist of the first electrode pads 3 a and the second electrode pads 3 b arranged alternately and parallel to each other linearly as shown in FIG. 3
- the electrode pads 5 of the first group of the interposer 4 consist of the first electrode pads 5 a and the second electrode pads 5 b arranged in a zigzag manner as shown in FIG. 3 .
- the distance 11 b between the first side 2 ⁇ 1 of the semiconductor chip 2 and the second electrode pad 5 b is larger than the distance 11 a between the first side 2 ⁇ of the semiconductor chip 2 and the first electrode pad 5 a
- the distance 12 b between the first side 2 ⁇ of the semiconductor chip 2 and the one end portion 8 b 1 of the second bonding wire 8 b is larger than the distance 12 a between the first side 2 ⁇ of the semiconductor chip 2 and the one end portion 8 a 1 of the first bonding wire 8 a
- the distance 13 b between the one end portion 8 b 1 and the other end portion 8 b 2 of the second bonding wire 8 b is larger than the distance 13 a between the one end portion 8 a 1 and the other end portion 8 a 2 of the first bonding wire 8 a.
- the width 3 w of the electrode pads 3 of the first group of the semiconductor chip 2 is smaller than the width 5 w of the electrode pads 5 of the first group of the interposer 4
- the pitch 3 p of the electrode pads 3 of the first group of the semiconductor chip 2 is smaller than the pitch 5 p of the electrode pads 3 of the first group of the interposer 4 .
- the width 3 w of the electrode pads 3 is, for example, about 60 ⁇ m
- the pitch 3 p of the electrode pads 3 is, for example, about 65 ⁇ m
- the width 5 w of the electrode pads 5 is, for example, about 100 ⁇ m
- the pitch 5 p of the electrode pads 5 is, for example, about 200 ⁇ m.
- the pads 3 of the first group of the semiconductor chip 2 have the contact mark 26 of a probe needle on the bonding surface connected to the bonding wires 8 , and the contact mark 26 is farther from the first side 2 ⁇ of the semiconductor chip 2 than the one end portion 8 a 1 of the first bonding wire 8 a and closer to the first side 2 ⁇ of the semiconductor chip than the one end portion 8 b 1 of the second bonding wire 8 b.
- the second to fourth groups of wires have the same constitution as the first group of wires
- the second to fourth groups of pads of the semiconductor chip 2 have the same constitution as the first group of pads of the semiconductor chip
- the second to fourth groups of pads of the interposer 4 have the same constitution as the first group of pads of the interposer 4 .
- the BGA type semiconductor device 1 which will be described hereinafter is produced by sealing up semiconductor chips arranged in the respective device areas of a multiple panel (multi-chip substrate) having a plurality of device areas (product forming areas) on the main surface with a single resin sealing body (batch resin sealing body) in a lump and separating the plural device areas of the multiple panel from one another together with this resin sealing body.
- FIG. 6 is a plan view showing the schematic constitution of the multiple panel used for the production of the BGA type semiconductor device 1 .
- the multiple panel 15 has a square plane form which is perpendicular to its thickness direction, for example, a rectangular plane in this embodiment.
- a molding area (not shown) is formed in the main surface (chip mounting surface) of the multiple panel 15 , a plurality of device areas 16 are formed in this molding area, and a chip mounting area 17 is formed in each of the device areas 16 .
- the semiconductor chip 2 is mounted in each chip mounting area 17 , and the resin sealing body for sealing up the plural semiconductor chips 2 mounted in the respective chip mounting areas 17 in a lump is formed in the molding area.
- the device areas 16 are defined by dividing areas 18 for specifying the boundaries thereof.
- the structure and plane form of the device areas 16 are the same as those of the interposer 4 shown in FIG. 1 and FIG. 2 .
- the production of the BGA type semiconductor device 1 will be described with reference to FIG. 7 to FIG. 15 .
- FIG. 7 is a plan view showing that a die bonding step is carried out
- FIG. 8 is a plan view showing that a first wire bonding step is carried out
- FIG. 9 is a partially enlarged plan view of FIG. 8
- FIG. 10 is a plan view showing that a second wire bonding step is carried out
- FIG. 11 is a partially enlarged plan view of FIG. 10
- FIG. 12 is a sectional view showing that a multiple panel is positioned in a mold in the molding step
- FIG. 13 is a plan view showing that a resin flows in the inside of the cavity of the mold in the molding step
- FIG. 14 is a plan view after the molding step is carried out
- FIG. 15 is a plan view showing that a cutting step is carried out.
- the semiconductor chips 2 and the multiple panel 15 are first prepared.
- an adhesive 7 such as an epoxy-based thermosetting resin is applied to the main surface of the multiple panel 15 , the semiconductor chip 2 is mounted on each chip mounting area 17 by the adhesive 7 , and then the adhesive 7 is cured thermally to fix the semiconductor chip 2 in each chip mounting area 17 as shown in FIG. 7 .
- the plural first electrode pads 3 a of the semiconductor chip 2 are electrically connected to the plural first electrode pads 5 a in the device forming areas 16 (interposer 4 ) by the plural first bonding wires 8 a , respectively.
- the connection of the first bonding wires 8 a is carried out by the nail head bonding method with the first electrode pads 3 a of the semiconductor chip 2 as first bonding points and the first electrode pads 5 a of the interposer 4 as second bonding points.
- the plural second electrode pads 3 b of the semiconductor chip 2 are electrically connected to the plural second electrode pads 5 b in the device forming areas 16 (interposer 4 ) by the plural second bonding wires 8 b , respectively.
- the connection of the second bonding wires 8 b is carried out by the nail head bonding method with the second electrode pads 3 b of the semiconductor chip 2 as first bonding points and the second electrode pads 5 b of the interposer 4 as second bonding points.
- connection between the second electrode pads 3 b of the semiconductor chip 2 and the one end portions 8 b 1 of the second bonding wires 8 b is carried out at positions farther from the respective sides of the semiconductor chip 2 than connection between the first electrode pads 3 a of the semiconductor chip 2 and the one end portions 8 a 1 of the first bonding wires 8 a
- connection between the second electrode pads 5 b in the device forming areas (interposer 4 ) 16 and the other end portions 8 b 2 of the second bonding wires 8 b is carried out at positions farther from the respective sides of the semiconductor chip 2 than connection between the first electrode pads 5 a in the device forming areas 16 and the other end portions 8 a 2 of the first bonding wires 8 a
- the second bonding wires 8 b have a larger loop height than the first bonding wires 8 a.
- the one end portions 8 b 1 of the second bonding wires 8 b are connected at positions farther from the first side 2 ⁇ of the semiconductor chip 2 than the one end portions 8 a 1 of the first bonding wires 8 a
- the other end portions 8 b 2 of the second bonding wires 8 b are connected at positions farther from the first side 2 ⁇ of the semiconductor chip 2 than the other end portions 8 a 2 of the first bonding wires 8 a . Therefore, the first bonding wires 8 a and the second bonding wires 8 b do not overlap with each other in the arrangement direction of the bonding wires 8 .
- connection of the second bonding wires 8 b which have a larger loop height than the first bonding wires 8 a is carried out after the connection of the first bonding wires 8 a .
- the second bonding wires 8 b which have a larger loop height than the first bonding wires 8 a are connected, thereby improving productivity because the set-up for wire bonding becomes easier than when the first and second bonding wires ( 8 a , 8 b ) are connected alternately.
- the second bonding wires 8 b are longer than the first bonding wires 8 a.
- the multiple panel 15 is positioned between the upper mold 30 a and the lower mold 30 b of a mold 30 .
- the mold 30 is not limited to this but it comprises a cavity 31 , a plurality of resin injection gates 32 , a plurality of subrunners, a plurality of main runners, a plurality of culls, a connection runner, a plurality of air vents, a plurality of pots and a panel storage area.
- the cavity 31 , the plural resin injection gates 32 , the plural subrunners, the plural main runners, the plural culls, connection runner and the plural air vents are formed in the upper mold 30 a , and the plural pots and the panel storage area are formed in the lower mold 30 b .
- the cavity 31 is formed in the depth direction from the mating face of the upper mold 30 a and the panel storage area is formed in the depth direction from the mating face of the lower mold 30 b.
- the plane forms of the cavity 31 and the panel storage area correspond to the plane form of the multiple panel 15 . Since the plane form of the multiple panel 15 is rectangular in this embodiment, the plane forms of the cavity 31 and the panel storage area are rectangular. The plane size of the cavity 31 is almost the same as the plane size of the molding area, and the plane size of the panel storage area is almost the same as the plane size of the multiple panel 15 .
- the multiple panel 15 is stored in the panel storage area of the lower mold 30 b and positioned in the mold 30 . When the multiple panel 15 is positioned in the mold 30 , the cavity 31 is existent above the main surface of the multiple panel 15 .
- an epoxy-based thermosetting resin for example, is injected into the cavity 31 from the pots of the mold 30 through the culls, main runners, subrunners and resin injection gates 32 to seal up the plural semiconductor chips 2 mounted on the main surface of the multiple panel 15 in a lump.
- the resin sealing body 33 which has sealed up the plural semiconductor chips 2 in a lump is formed only on the main surface of the multiple panel 15 by this step.
- the resin 33 a injected into the inside of the cavity 31 flows from the above long side toward the other long side of the cavity 31 . Therefore, the macroscopic flow direction 34 of the resin 33 a in the inside of the cavity 31 becomes a direction from one long side toward the other long side of the cavity 31 .
- one end portion 8 b 1 of the second bonding wire 8 b out of adjacent bonding wires is connected at a position farther from the first side 2 ⁇ of the semiconductor chip 2 than the one end portion 8 a 1 of the first bonding wire 8 a
- the other end portion 8 b 2 of the second bonding wire 8 b is connected at a position farther from the first side 2 ⁇ of the semiconductor chip 2 than the other end portion 8 a 2 of the first bonding wire 8 a
- a short circuit between the adjacent bonding wires can be suppressed.
- the ball-like solder bumps 10 are then formed on the main surfaces of the plural electrode pads 6 arranged on the rear surface of the multiple panel 15 .
- the solder bumps 10 are formed, for example, by supplying ball-like solder materials by a ball supplying method and heating them.
- the resin sealing body 33 for sealing up the plural semiconductor chips 2 in a lump is affixed to a dicing sheet 26 and then the plural device areas 16 of the multiple panel 15 are separated from one another together with the resin sealing body 33 as shown in FIG. 15 .
- This separation is carried out by a dicing machine.
- the semiconductor device 1 shown in FIG. 1 and FIG. 2 is almost completed by this step.
- FIG. 16 is a plan view of a semiconductor wafer
- FIG. 17 is a partially enlarged plan view of FIG. 16
- FIG. 18 is a partially enlarged plan view of FIG. 17
- FIG. 19 is a diagram for explaining a characteristics inspection step.
- the semiconductor wafer 20 made from monocrystal silicon is prepared, and the main surface of the semiconductor wafer 20 is subjected to a wafer pretreatment step for forming a semiconductor device such as a field effect transistor, a wiring layer and an insulating film in order to form a plurality of chip forming areas 21 having a control circuit as an integrated circuit in a matrix form as shown in FIG. 16 .
- the plural chip forming areas 21 are defined by dividing areas 22 for specifying the boundaries thereof and spaced apart from one another.
- the plural chip forming areas 22 are produced by forming a semiconductor device, multi-layer wiring laminate, electrode pads 3 , surface protective film and openings on the main surface of the semiconductor wafer 20 .
- probe inspection is carried out by using a probe card.
- the probe inspection is carried out by first aligning the semiconductor wafer 20 with the probe card and coming the end portion 25 a of the probe needle 25 of the probe card into contact with one of the plural electrode pads 3 in the chip forming area 21 of the semiconductor wafer 20 . Then, the electric properties of the circuit in the chip forming area 21 are measured with a tester electrically connected to the probe needle 25 of the probe card. This step is carried out for each chip forming area 21 . Thereby, whether the chip forming area 21 is accepted or not and the grade of electric properties such as operation frequency of the chip forming area 21 are judged.
- a scratch that is, a contact mark 26 is formed on the connection surface of the electrode pad 3 by the contact of the probe needle 25 . Since this contact mark 26 deteriorates bonding between the electrode pad 3 and the one end portion of the bonding wire 8 , it is necessary to prevent the contact mark 26 from being formed in the area where one end portion of the bonding wire 8 is connected as much as possible.
- the electrode pads 3 have a rectangular plane form that their two long opposite sides extend in a direction away from the respective sides of the semiconductor chip 2 and their short opposite sides extend along the respective sides of the semiconductor chip 2 . Therefore, the contact marks 26 can be formed at positions farther from the sides of the semiconductor chip 2 than the one end portions of the first bonding wires 8 a and closer to the sides of the semiconductor chip 2 than the one end portions of the second bonding wires 8 b by setting the length of the long sides of the electrode pad 3 to twice or more the length of the long sides of the electrode pads 3 in the connection areas between the electrode pad 3 and one end portions of the bonding wires 8 , thereby making it possible to prevent the contact marks 26 from being formed in the areas where one end portions of the bonding wires 8 are connected.
- a probe test can be carried out by using the existing probe card.
- the dividing areas 22 of the semiconductor wafer 20 are diced with the dicing machine to divide the semiconductor wafer 20 into chip forming areas 21 . Thereby, semiconductor chips 2 are formed.
- FIG. 20 is a diagram showing the positions of the connecting portions when the electrode pads 3 of the semiconductor chip 2 and the one end portions of the bonding wires 8 are connected to each other in a zigzag manner.
- FIG. 21 is a diagram showing the positions of the connecting portions when the electrode pads 3 of the semiconductor chip 2 and the one end portions of the bonding wires 8 are connected to each other linearly.
- the distance 8 p between the one end portion 8 a 1 of the first bonding wire 8 a connected to the first electrode pad 3 a and the one end portion 8 b 1 of the second bonding wire 8 b connected to the second electrode pad 3 b adjacent to the first electrode pad 3 a is wider when the electrode pads 3 of the semiconductor chip 2 are connected to the one end portions of the bonding wires 8 in a zigzag manner than when the electrode pads 3 of the semiconductor chip 2 are connected to the one end portions of the bonding wires 8 linearly.
- the pitches of the electrode pads are the same, the end portion 28 of a capillary is brought into contact with the one end portions of the adjacent bonding wires 3 in FIG. 21 whereas the end portion 28 of the capillary does not contact the one end portions of the adjacent bonding wires in FIG. 22 .
- the distance 8 p can be increased without widening the pitch of the electrode pads 3 , the pitch 3 p of the electrode pads 3 can be narrowed by the increase in the distance 3 p . As a result, the plane size of the semiconductor chip 2 can be reduced, thereby making it possible to downsize the BGA type semiconductor device 1 .
- FIG. 22 is a plan view of the key section of a BGA type semiconductor device according to Embodiment 2 of the present invention
- FIG. 23 is a plan view of the key section of the semiconductor chip of FIG. 22 .
- the BGA type semiconductor device 1 a of this Embodiment 2 is basically the same as the above Embodiment in constitution but differs from the above Embodiment in the following.
- a plurality of electrode pads 3 are arranged on the main surface of the semiconductor chip 2 along each side of the semiconductor chip 2 and consist of first electrode pads 3 a and second electrode pads 3 b adjacent to the first electrode pads 3 a and farther from the respective sides of the semiconductor chip 2 than the first electrode pads 3 a , all of which are arranged alternately in a zigzag manner.
- the plane form of the electrode pads 3 is, for example, square.
- the end portions 25 a of the probe needles 25 must be arranged in a zigzag manner, thereby making it difficult to use existing probe cards.
- FIG. 24 is a plan view of the key section of a BGA type semiconductor device according to Embodiment 3 of the present invention
- FIG. 25 is a sectional view of the key section of the semiconductor device of FIG. 24 .
- the BGA type semiconductor device 1 b of this Embodiment 3 is the same as the above Embodiment 1 in constitution but differs from the above Embodiment 1 in that the semiconductor chip sealed up with the resin sealing body 9 has a laminate structure.
- a second semiconductor chip 2 b is formed on a first semiconductor chip 2 a by an adhesive layer 7 , and the electrode pads 3 a of the first semiconductor chip 2 a and the electrode pads 3 b of the second semiconductor chip 2 b are arranged in a zigzag manner like Embodiments 1 and 2.
- the above second semiconductor chip 2 b is made as thin as 0.1 mm or less, for example, to reduce the thickness of the resin sealing body 9 as much as possible.
- the semiconductor chip is made thin, the electrode pads of the upper and lower semiconductor chips become close to each other. However, when the electrode pads are arranged in the same manner as in Embodiments 1 and 2, contact between wires can be prevented.
- a short circuit between adjacent bonding wires can be suppressed.
- the size of a semiconductor device can be reduced.
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Abstract
A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.
Description
- The present invention relates to a semiconductor device and a production technology for the same and, specifically, to a semiconductor device having a face-up bonding structure and a technology which is effectively applied to a production technology for the same.
- There is known a semiconductor device called “BGA (Ball Grid Array) type semiconductor device”. This BGA type semiconductor device is packaged such that a semiconductor chip is mounted on a main surface of a wiring substrate called “interposer” and a plurality of ball-like solder bumps are arranged as external connection terminals on the rear surface opposite to the main surface of the wiring substrate.
- BGA type semiconductor devices having different structures have been developed and commercialized. The structures of the BGA type semiconductor devices are roughly divided into a face-up bonding structure (wire bonding structure) and a face-down bonding structure. In the face-up bonding structure, electrode pads arranged on the main surface (circuit formation surface) of the semiconductor chip and electrode pads (connecting portions which are parts of wirings) arranged on the main surface of the interposer are electrically connected by bonding wires. In the face-down bonding structure, electrode pads arranged on the main surface of the semiconductor chip and electrode pads arranged on the main surface of the interposer are electrically connected by solder bumps interposed between the electrode pads.
- The BGA type semiconductor device having a face-up bonding structure is disclosed by Japanese Unexamined Patent Publication No. 2001-144214, for example. The BGA type semiconductor device having a face-down bonding structure is disclosed by Japanese Unexamined Patent Publication No. Hei 6(1994)-34983, for example.
- Along with a recent tendency toward the downsizing of electronic devices such as portable telephones and portable personal computers, demand for small-sized BGA type semiconductor devices to be incorporated into these electronic devices is growing. To cope with this demand, the inventors of the present invention has made studies into the downsizing of a BGA type semiconductor device having a face-up bonding structure which can be produced with existing production equipment at a low cost and has found the following problems.
- To downsize the BGA type semiconductor device, the plane sizes of the semiconductor chip and the interposer must be reduced. To reduce the plane size of the semiconductor chip, the pitch of the electrode pads arranged on the main surface of the semiconductor chip must be reduced. To reduce the plane size of the interposer, the pitch of the electrode pads arranged on the main surface of the interposer must be reduced.
- When the pitches of the electrode pads of the semiconductor chip and the interposer are reduced, the interval between adjacent bonding wires is also narrowed. When the interval between adjacent bonding wires is narrowed, a short circuit easily occurs between adjacent bonding wires due to “the flowing of the wires” that the bonding wires are deformed by a flow of a resin at the time of forming a resin sealing body by a transfer molding method. Therefore, in order to downsize the BGA type semiconductor device having a face-up bonding structure, a short circuit between adjacent bonding wires must be suppressed.
- To suppress a short circuit between adjacent bonding wires, it is conceivable that the loop heights of adjacent bonding wires should be changed. This is effective in suppressing a short circuit between intermediate portions of bonding wires but it is difficult to suppress a short circuit on one end sides (electrode pad side of the semiconductor chip) of the bonding wires and the other end sides (the electrode pad side of the interposer substrate) of the bonding wires.
- It is an object of the present invention to provide a technology capable of suppressing a short circuit between adjacent bonding wires.
- It is another object of the present invention to provide a technology capable of downsizing a semiconductor device by suppressing a short circuit between adjacent bonding wires.
- The above and other objects and new features of the present invention will become apparent from the following description and the accompanying drawings.
- The present invention relates to the following.
- (1) A semiconductor device comprises a semiconductor chip, a wiring substrate mounting the semiconductor chip on the main surface, a plurality of electrode pads arranged on the main surface of the semiconductor chip along one side of the semiconductor chip, a plurality of connecting portions arranged on the main surface of the wiring substrate along one side of the semiconductor chip, a plurality of wires for electrically connecting the plural electrode pads of the semiconductor chip to the plural connecting portions of the wiring substrate, respectively, and a resin sealing body for sealing the semiconductor chip and the plural wires,
- wherein the plural wires include first wires having one end portions connected to first electrode pads out of the plural electrode pads and the other end portions opposite to the one end portions and connected to first connecting portions out of the plural connecting portions and second wires having one end portions connected to second electrode pads adjacent to the first electrode pads out of the plural electrode pads and the other end portions opposite to the above one end portions and connected to second connecting portions adjacent to the first connecting portions, the loop height of the second wires being larger than the first wires, and
- wherein the one end portions of the second wires are connected at positions farther from one side of the semiconductor chip than the one end portions of the first wires and the other end portions of the second wires are connected at positions farther from one side of the semiconductor chip than the other end portions of the first wires.
- (2) A process for producing a semiconductor device comprises:
- an assembly parts preparing step of preparing a semiconductor chip having a plurality of electrode pads arranged on the main surface along one side of the main surface and a wiring substrate having a chip mounting area for mounting the semiconductor chip and a plurality of connecting portions arranged along one side of the semiconductor chip outside the chip mounting area;
- a die bonding step of mounting the semiconductor chip on the chip mounting area of the wiring substrate;
- a wire bonding step of electrically connecting the plural electrode pads of the semiconductor chip to the plural connecting portions of the wiring substrate by a plurality of wires, respectively; and
- a molding step of sealing the semiconductor chip and the plural wires with a resin,
- wherein the plural wires include first wires having one end portions connected to first electrode pads out of the plural electrode pads and the other end portions opposite to the one end portions and connected to first connecting portions out of the plural connecting portions and second wires having one end portions connected to second electrode pads adjacent to the first electrode pads out of the plural electrode pads and the other end portions opposite to the above one end portions and connected to second connecting portions adjacent to the first connecting portions out of the plural connecting portions, the loop height of the second wires being larger than the first wires,
- wherein the one end portions of the second wires are connected at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and
- wherein the other end portions of the second wires are connected at positions farther from one side of the semiconductor chip than the other end portions of the first wires.
-
FIG. 1 is a plan view showing the internal structure of a semiconductor device according toEmbodiment 1 of the present invention; -
FIG. 2 is a sectional view along line A-A ofFIG. 1 ; -
FIG. 3 is a partially enlarged plan view ofFIG. 1 ; - FIGS. 4(A) to 4(C) are diagrams showing the internal structure of the semiconductor device of
Embodiment 1, in whichFIG. 4 (A) is a sectional view along line B-B ofFIG. 3 ,FIG. 4 (B) is a sectional view along line C-C ofFIG. 3 , andFIG. 4 (C) is a sectional view obtained by combiningFIG. 4 (A) withFIG. 4 (B); -
FIG. 5 is a partially enlarged plan view ofFIG. 3 ; -
FIG. 6 is a plan view showing the schematic constitution of a multiple panel used for the production of the semiconductor device ofEmbodiment 1; -
FIG. 7 is a plan view showing that a chip bonding step is carried out in the production of the semiconductor device ofEmbodiment 1; -
FIG. 8 is a plan view showing that a first wire bonding step is carried out in the production of the semiconductor device ofEmbodiment 1; -
FIG. 9 is a partially enlarged plan view ofFIG. 8 ; -
FIG. 10 is a plan view showing that a second wire bonding step is carried out in the production of the semiconductor device ofEmbodiment 1; -
FIG. 11 is a partially enlarged plan view ofFIG. 10 ; -
FIG. 12 is a sectional view showing that a multiple panel is positioned in a mold in the molding step of the production of the semiconductor device ofEmbodiment 1; -
FIG. 13 is a plan view showing that a resin flows in the cavity of the mold in the molding step of the production of the semiconductor device ofEmbodiment 1; -
FIG. 14 is a plan view showing that the molding step is carried out in the production of the semiconductor device ofEmbodiment 1; -
FIG. 15 is a plan view showing that a cutting step is carried out in the production of the semiconductor device ofEmbodiment 1; -
FIG. 16 is a plan view of a semiconductor wafer ofEmbodiment 1; -
FIG. 17 is a partially enlarged plan view ofFIG. 16 ; -
FIG. 18 is a partially enlarged plan view ofFIG. 17 ; -
FIG. 19 is a diagram for explaining a characteristic inspection step in the production of the semiconductor device ofEmbodiment 1; -
FIG. 20 is a diagram showing the positions of connecting portions when the electrode pads of the semiconductor chip and the one end portions of the bonding wires are connected to each other in a zigzag manner; -
FIG. 21 is a diagram showing the positions of connecting portions when the electrode pads of the semiconductor chip and the one end portions of the bonding wires are connected to each other linearly; -
FIG. 22 is a plan view of the key section of a semiconductor device according toEmbodiment 2 of the present invention; -
FIG. 23 is a plan view of the key section of the semiconductor chip ofFIG. 22 ; -
FIG. 24 is a partial plan view showing the internal structure of a semiconductor device according toEmbodiment 3 of the present invention; and -
FIG. 25 is a sectional view of the key section corresponding toFIG. 24 . - Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In all the drawings for explaining the embodiments of the present invention, elements denoted by the same symbol have the same function and a repeated description of the elements is omitted.
- In
Embodiment 1, a BGA type semiconductor device having a face-up bonding structure to which the present invention is applied will be described hereinbelow. -
FIG. 1 is a plan view showing the internal structure of a BGA type semiconductor device having a face-up bonding structure according toEmbodiment 1 of the present invention,FIG. 2 is a sectional view along line A-A ofFIG. 1 ,FIG. 3 is a partially enlarged plan view ofFIG. 1 , FIGS. 4(A) to 4(C) are diagrams showing the internal structure of the semiconductor device according to Embodiment 1 (FIG. 4 (A) is a sectional view along line B-B ofFIG. 3 ,FIG. 4 (B) is a sectional view along line C-C ofFIG. 3 andFIG. 4 (C) is a sectional view obtained by combiningFIG. 4 (A) withFIG. 4 (B)), andFIG. 5 is a partially enlarged view ofFIG. 3 . - As shown in
FIG. 1 andFIG. 2 , the BGAtype semiconductor device 1 according toEmbodiment 1 has a package structure that asemiconductor chip 2 is mounted on themain surface 4× out of themain surface 4× and therear surface 4 y located on the opposite sides of an interposer 4 (oppositemain surface 4× andrear surface 4 y) and a plurality of ball-like solder bumps 10 are arranged as external connection terminals on therear surface 4 y of theinterposer 4. - The
semiconductor chip 2 has a square plane which is perpendicular to its thickness direction, for example, a 5.0 mm×5.0 mm plane in this embodiment. Thesemiconductor chip 2 is mainly composed of a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, a multi-layered wiring laminate consisting of a plurality of insulating layers and a plurality of wiring layers formed on the main surface of the semiconductor substrate, and a surface protective film (final protective film) formed on the multi-layered wiring laminate, though it is not limited to this structure. The insulating layers are each formed of a silicon oxide film, for example. The wiring layers are each formed of a metal film such as an aluminum (Al), aluminum alloy, copper (Cu) or copper alloy film. The surface protective film is formed of a multi-layer laminate film consisting of an inorganic insulating film such as silicon oxide film or silicon nitride film and an organic insulating film. - The
semiconductor chip 2 has a main surface (circuit formation surface) 2× and arear surface 2 y which are located on opposite sides, and an integrated circuit, for example, a control circuit is formed on themain surface 2× of thesemiconductor chip 2. This control circuit is mainly composed of transistor elements formed on the main surface of the semiconductor substrate and wirings formed on the multi-layered wiring laminate. Thesemiconductor chip 2 is fixed to themain surface 4× of theinterposer 4 by an adhesive 7 interposed between therear surface 2 y thereof and themain surface 4× of theinterposer 4. - Four groups of
electrode pads 3 are arranged on the main surface of thesemiconductor chip 2. Theelectrode pads 3 of a first group are arranged along thefirst side 2×22 of thesemiconductor chip 2, theelectrode pads 3 of a second group are arranged along thesecond side 2×2 of thesemiconductor chip 2, theelectrode pads 3 of a third group are arranged along thethird side 2×3 of thesemiconductor chip 3, and theelectrode pads 3 of a fourth group are arranged along thefourth side 2×4 of thesemiconductor chip 2. Theelectrode pads 3 of all the groups are formed on the uppermost wiring layer out of the multi-layered wiring laminate of thesemiconductor chip 2 and exposed from bonding openings formed in the surface protective film of thesemiconductor chip 2 corresponding to therespective electrode pads 3. - The
interposer 4 has a square plane which is perpendicular to its thickness direction, for example, a 13.0 mm×13.0 mm plane in this embodiment. Theinterposer 4 is mainly composed of a core material, a protective film formed to cover the main surface of the core material and a protective film formed to cover the rear surface (surface opposite to the main surface of the core material) opposite to the main surface of the core material, though it is not limited to this structure. The core material has a multi-layered wiring structure comprising wirings in the main surface, rear surface and interior thereof. Each insulating layer of the core material is formed of a highly elastic resin substrate made from glass fibers impregnated with an epoxy-based or polyimide-based resin. Each wiring layer of the core material is formed of a metal film essentially composed of Cu, for example. The protective film on the main surface of the core material is formed to protect mainly wirings formed in the uppermost wiring layer of the core material and the protective film on the rear surface of the core material is formed to protect mainly wirings formed in the lowermost wiring layer of the core material. As the protective films on the main surface and the rear surface of the core material are used an insulating film made from a two-liquid alkali developing solder resist ink or thermosetting one-liquid solder resist ink. - Four groups of electrode pads 5 (wire connecting portions) are arranged around the
semiconductor chip 2 on themain surface 4× of theinterposer 4. Theelectrode pads 5 of a first group are arranged along thefirst side 2× of thesemiconductor chip 2, theelectrode pads 5 of a second group are arranged along thesecond side 2×2 of thesemiconductor chip 2, theelectrode pads 5 of a third group are arranged along thethird side 2×3 of thesemiconductor chip 2, and theelectrode pads 5 of a fourth group are arranged along thefourth side 2×4 of thesemiconductor chip 2. Theelectrode pads 5 of all the groups are formed with parts of the plural wirings formed in the uppermost wiring layer of the core material and exposed from openings formed in the protective film on the main surface of the core material corresponding to therespective electrode pads 5. - A plurality of
electrode pads 6 are formed on therear surface 4 y of theinterposer 4. Theplural electrode pads 6 are formed with part of the plural wirings formed in the lowermost wiring layer of the core material and exposed from openings formed in the protective film on the rear surface of the core material corresponding to therespective electrode pads 6. - The
electrode pads 3 of the first group of thesemiconductor chip 2 and theelectrode pads 5 of the first group of theinterposer 4 are electrically connected to each other bybonding wires 8 of a first group, respectively. Theelectrode pads 3 of the second group of thesemiconductor chip 2 and theelectrode pads 5 of the second group of theinterposer 4 are electrically connected to each other bybonding wires 8 of a second group, respectively. Theelectrode pads 3 of the third group of thesemiconductor chip 2 and theelectrode pads 5 of the third group of theinterposer 4 are electrically connected to each other bybonding wires 8 of a third group, respectively. Theelectrode pads 3 of the fourth group of thesemiconductor chip 2 and theelectrode pads 5 of the fourth group of theinterposer 4 are electrically connected to each other bybonding wires 8 of a fourth group, respectively. Thebonding wires 8 are gold (Au) wires, for example. Thebonding wires 8 are connected by a nail head bonding (ball bonding) method making use of ultrasonic vibration for thermal contact bonding. - The
bonding wires 8 of all the groups are connected by the nail head bonding method in which theelectrode pads 3 of thesemiconductor chip 2 are used as first bonding points and theelectrode pads 5 of theinterposer 4 are used as second bonding points. - The
semiconductor chip 2 and theplural bonding wires 8 of all the groups are sealed up with aresin sealing body 9 formed on themain surface 4× of theinterposer 4. Theresin sealing body 9 is formed from an epoxy-based thermosetting insulating resin containing a phenolic curing agent, silicone rubber and a large number of fillers (such as silica) to reduce stress. A transfer molding method which is suitable for mass-production is used to form theresin sealing body 9. - The plural solder bumps 10 are fixed and electrically and mechanically connected to the
respective electrode pads 6 formed on therear surface 4 y of theinterposer 4. The solder bumps 10 are Pb-free solder bumps which contain substantially no Pb, for example, Sn-1[wt %]Ag-0.5[wt %]Cu solder bumps. - The electrode pads of the first group of the
semiconductor chip 2 have a rectangular plane form that their two long opposite sides extend in a direction away from thefirst side 2× of thesemiconductor chip 2 and their two short opposite sides extend along thefirst side 2×1 of thesemiconductor chip 2. Theelectrode pads 3 of the second group, theelectrode pads 3 of the third group and theelectrode pads 3 of the fourth group of thesemiconductor chip 2 have a rectangular plane form that their two long opposite sides extend in a direction away from the respective sides (second side 2×2,third side 2×3,fourth side 2×4) of thesemiconductor chip 2 and their two short opposite sides extend along the respective sides (second side 2×2,third side 2×3,fourth side 2×4) of thesemiconductor chip 2. - The
bonding wires 8 of the first group includefirst bonding wires 8 a having oneend portions 8 a 1 connected to thefirst electrode pads 3 a out of theelectrode pads 3 of the first group of thesemiconductor chip 2 and theother end portions 8 a 2 opposite to the oneend portions 8 a 1 and connected to thefirst electrode pads 5 a out of theelectrode pads 5 of the first group of theinterposer 4 as shown inFIG. 3 andFIG. 4 (A) andsecond bonding wires 8 b having oneend portions 8b 1 connected to thesecond electrode pads 3 b adjacent to thefirst electrode pads 3 a out of theelectrode pads 3 of the first group of thesemiconductor chip 2 and theother end portions 8b 2 opposite to the oneend portions 8 b 1 and connected to thesecond electrode pads 5 b adjacent to thefirst electrode pads 5 a out of theelectrode pads 5 of the first group of theinterposer 4 as shown inFIG. 3 andFIG. 4 (B). Theloop height 14 a (seeFIG. 4 (A)) of thefirst bonding wires 8 a is lower than theloop height 14 b of thesecond bonding wires 8 b. - As shown in
FIG. 4 (A) andFIG. 4 (B), the oneend portion 8b 1 of thesecond bonding wire 8 b is connected at a position farther from thefirst side 2× of the semiconductor chip than the oneend portion 8 a 1 of thefirst bonding wire 8 a, and theother end portion 8b 2 of thesecond bonding wire 8 b is connected at a position farther from thefirst side 2× of thesemiconductor chip 2 than theother end portion 8 a 2 of thefirst bonding wire 8 a. - Due to this constitution, as shown in
FIG. 4 (C), there is no overlapped portion between thefirst bonding wire 8 a and thesecond bonding wire 8 b in the arrangement direction of thebonding wires 8, thereby making it possible to suppress a short circuit between adjacent bonding wires even if thebonding wires 8 are deformed by a flow of the resin when the resin sealing body is to be formed by the transfer molding method. - A short circuit between adjacent bonding wires can be suppressed by changing the loop height of one of them. However, as an overlapped portion between the bonding wires in the arrangement direction of the bonding wires is formed on one end sides and the other end sides of the bonding wires in this case, a short circuit between the intermediate portions of the bonding wires can be suppressed but it is difficult to suppress a short circuit on one end sides and the other end sides. In contrast to this, as there is no overlapped portion between the bonding wires in the arrangement direction of the bonding wires on one end sides and the other end sides thereof in this embodiment, a short circuit on one end sides and the other end sides of the bonding wires can be suppressed.
- For the downsizing of the BGA
type semiconductor device 1, the plane sizes of the semiconductor chip and the interposer must be reduced. To reduce the plane sizes of the semiconductor chip and the interposer, the pitches of the electrode pads arranged on the main surfaces of the semiconductor chip and the interposer must be reduced. When the pitch of the electrode pads on the semiconductor chip is reduced, a bonding wire having a small diameter must be used. Since the bonding wire having a small diameter has low mechanical strength, it is easily deformed on one end side and the other end side thereof. When the pitches of the electrode pads of the semiconductor chip and the interposer are reduced, the interval between adjacent bonding wires is narrowed, whereby a short circuit easily occurs on one end sides and the other end sides of the bonding wires. Therefore, to downsize the BGAtype semiconductor device 1, a short circuit on one side ends and the other side ends of the bonding wires must be suppressed. Since a short circuit can be suppressed on one end sides and the other end sides of the bonding wires in this embodiment, the BGAtype semiconductor device 1 can be downsized. - The
electrode pads 3 of the first group of thesemiconductor chip 2 consist of thefirst electrode pads 3 a and thesecond electrode pads 3 b arranged alternately and parallel to each other linearly as shown inFIG. 3 , and theelectrode pads 5 of the first group of theinterposer 4 consist of thefirst electrode pads 5 a and thesecond electrode pads 5 b arranged in a zigzag manner as shown inFIG. 3 . - As shown in
FIG. 4 (A) andFIG. 4 (B), thedistance 11 b between thefirst side 2×1 of thesemiconductor chip 2 and thesecond electrode pad 5 b is larger than thedistance 11 a between thefirst side 2× of thesemiconductor chip 2 and thefirst electrode pad 5 a, thedistance 12 b between thefirst side 2× of thesemiconductor chip 2 and the oneend portion 8b 1 of thesecond bonding wire 8 b is larger than thedistance 12 a between thefirst side 2× of thesemiconductor chip 2 and the oneend portion 8 a 1 of thefirst bonding wire 8 a, and thedistance 13 b between the oneend portion 8 b 1 and theother end portion 8b 2 of thesecond bonding wire 8 b is larger than thedistance 13 a between the oneend portion 8 a 1 and theother end portion 8 a 2 of thefirst bonding wire 8 a. - As shown in
FIG. 5 , thewidth 3 w of theelectrode pads 3 of the first group of thesemiconductor chip 2 is smaller than thewidth 5 w of theelectrode pads 5 of the first group of theinterposer 4, and thepitch 3 p of theelectrode pads 3 of the first group of thesemiconductor chip 2 is smaller than thepitch 5 p of theelectrode pads 3 of the first group of theinterposer 4. In this embodiment, thewidth 3 w of theelectrode pads 3 is, for example, about 60 μm, thepitch 3 p of theelectrode pads 3 is, for example, about 65 μm, thewidth 5 w of theelectrode pads 5 is, for example, about 100 μm, and thepitch 5 p of theelectrode pads 5 is, for example, about 200 μm. Thepads 3 of the first group of thesemiconductor chip 2 have thecontact mark 26 of a probe needle on the bonding surface connected to thebonding wires 8, and thecontact mark 26 is farther from thefirst side 2× of thesemiconductor chip 2 than the oneend portion 8 a 1 of thefirst bonding wire 8 a and closer to thefirst side 2× of the semiconductor chip than the oneend portion 8b 1 of thesecond bonding wire 8 b. - The second to fourth groups of wires have the same constitution as the first group of wires, the second to fourth groups of pads of the
semiconductor chip 2 have the same constitution as the first group of pads of the semiconductor chip, and the second to fourth groups of pads of theinterposer 4 have the same constitution as the first group of pads of theinterposer 4. - The plane sizes of the
resin sealing body 9 and theinterposer 4 are almost the same, and the side surfaces of theresin sealing body 9 are flush with the side surfaces of theinterposer 4. In the production of the BGAtype semiconductor device 1 of this embodiment, a batch molding system is employed. Therefore, the BGAtype semiconductor device 1 which will be described hereinafter is produced by sealing up semiconductor chips arranged in the respective device areas of a multiple panel (multi-chip substrate) having a plurality of device areas (product forming areas) on the main surface with a single resin sealing body (batch resin sealing body) in a lump and separating the plural device areas of the multiple panel from one another together with this resin sealing body. -
FIG. 6 is a plan view showing the schematic constitution of the multiple panel used for the production of the BGAtype semiconductor device 1. - As shown in
FIG. 6 , themultiple panel 15 has a square plane form which is perpendicular to its thickness direction, for example, a rectangular plane in this embodiment. A molding area (not shown) is formed in the main surface (chip mounting surface) of themultiple panel 15, a plurality ofdevice areas 16 are formed in this molding area, and achip mounting area 17 is formed in each of thedevice areas 16. Thesemiconductor chip 2 is mounted in eachchip mounting area 17, and the resin sealing body for sealing up theplural semiconductor chips 2 mounted in the respectivechip mounting areas 17 in a lump is formed in the molding area. - The
device areas 16 are defined by dividingareas 18 for specifying the boundaries thereof. The structure and plane form of thedevice areas 16 are the same as those of theinterposer 4 shown inFIG. 1 andFIG. 2 . - The production of the BGA
type semiconductor device 1 will be described with reference toFIG. 7 toFIG. 15 . -
FIG. 7 is a plan view showing that a die bonding step is carried out,FIG. 8 is a plan view showing that a first wire bonding step is carried out,FIG. 9 is a partially enlarged plan view ofFIG. 8 ,FIG. 10 is a plan view showing that a second wire bonding step is carried out,FIG. 11 is a partially enlarged plan view ofFIG. 10 ,FIG. 12 is a sectional view showing that a multiple panel is positioned in a mold in the molding step,FIG. 13 is a plan view showing that a resin flows in the inside of the cavity of the mold in the molding step,FIG. 14 is a plan view after the molding step is carried out, andFIG. 15 is a plan view showing that a cutting step is carried out. - The semiconductor chips 2 and the
multiple panel 15 are first prepared. - Next, an adhesive 7 such as an epoxy-based thermosetting resin is applied to the main surface of the
multiple panel 15, thesemiconductor chip 2 is mounted on eachchip mounting area 17 by the adhesive 7, and then the adhesive 7 is cured thermally to fix thesemiconductor chip 2 in eachchip mounting area 17 as shown inFIG. 7 . - As shown in
FIG. 8 andFIG. 9 , the pluralfirst electrode pads 3 a of thesemiconductor chip 2 are electrically connected to the pluralfirst electrode pads 5 a in the device forming areas 16 (interposer 4) by the pluralfirst bonding wires 8 a, respectively. The connection of thefirst bonding wires 8 a is carried out by the nail head bonding method with thefirst electrode pads 3 a of thesemiconductor chip 2 as first bonding points and thefirst electrode pads 5 a of theinterposer 4 as second bonding points. - Thereafter, as shown in
FIG. 10 andFIG. 11 , the pluralsecond electrode pads 3 b of thesemiconductor chip 2 are electrically connected to the pluralsecond electrode pads 5 b in the device forming areas 16 (interposer 4) by the pluralsecond bonding wires 8 b, respectively. The connection of thesecond bonding wires 8 b is carried out by the nail head bonding method with thesecond electrode pads 3 b of thesemiconductor chip 2 as first bonding points and thesecond electrode pads 5 b of theinterposer 4 as second bonding points. Connection between thesecond electrode pads 3 b of thesemiconductor chip 2 and the oneend portions 8b 1 of thesecond bonding wires 8 b is carried out at positions farther from the respective sides of thesemiconductor chip 2 than connection between thefirst electrode pads 3 a of thesemiconductor chip 2 and the oneend portions 8 a 1 of thefirst bonding wires 8 a, and connection between thesecond electrode pads 5 b in the device forming areas (interposer 4) 16 and theother end portions 8b 2 of thesecond bonding wires 8 b is carried out at positions farther from the respective sides of thesemiconductor chip 2 than connection between thefirst electrode pads 5 a in thedevice forming areas 16 and theother end portions 8 a 2 of thefirst bonding wires 8 a. Thesecond bonding wires 8 b have a larger loop height than thefirst bonding wires 8 a. - In this step, the one
end portions 8b 1 of thesecond bonding wires 8 b are connected at positions farther from thefirst side 2× of thesemiconductor chip 2 than the oneend portions 8 a 1 of thefirst bonding wires 8 a, and theother end portions 8b 2 of thesecond bonding wires 8 b are connected at positions farther from thefirst side 2× of thesemiconductor chip 2 than theother end portions 8 a 2 of thefirst bonding wires 8 a. Therefore, thefirst bonding wires 8 a and thesecond bonding wires 8 b do not overlap with each other in the arrangement direction of thebonding wires 8. - The connection of the
second bonding wires 8 b which have a larger loop height than thefirst bonding wires 8 a is carried out after the connection of thefirst bonding wires 8 a. Thus, after the connection of thefirst bonding wires 8 a, thesecond bonding wires 8 b which have a larger loop height than thefirst bonding wires 8 a are connected, thereby improving productivity because the set-up for wire bonding becomes easier than when the first and second bonding wires (8 a, 8 b) are connected alternately. - The
second bonding wires 8 b are longer than thefirst bonding wires 8 a. - As shown in
FIG. 12 , themultiple panel 15 is positioned between theupper mold 30 a and thelower mold 30 b of amold 30. - The
mold 30 is not limited to this but it comprises acavity 31, a plurality ofresin injection gates 32, a plurality of subrunners, a plurality of main runners, a plurality of culls, a connection runner, a plurality of air vents, a plurality of pots and a panel storage area. Thecavity 31, the pluralresin injection gates 32, the plural subrunners, the plural main runners, the plural culls, connection runner and the plural air vents are formed in theupper mold 30 a, and the plural pots and the panel storage area are formed in thelower mold 30 b. Thecavity 31 is formed in the depth direction from the mating face of theupper mold 30 a and the panel storage area is formed in the depth direction from the mating face of thelower mold 30 b. - The plane forms of the
cavity 31 and the panel storage area correspond to the plane form of themultiple panel 15. Since the plane form of themultiple panel 15 is rectangular in this embodiment, the plane forms of thecavity 31 and the panel storage area are rectangular. The plane size of thecavity 31 is almost the same as the plane size of the molding area, and the plane size of the panel storage area is almost the same as the plane size of themultiple panel 15. Themultiple panel 15 is stored in the panel storage area of thelower mold 30 b and positioned in themold 30. When themultiple panel 15 is positioned in themold 30, thecavity 31 is existent above the main surface of themultiple panel 15. - Subsequently, an epoxy-based thermosetting resin, for example, is injected into the
cavity 31 from the pots of themold 30 through the culls, main runners, subrunners andresin injection gates 32 to seal up theplural semiconductor chips 2 mounted on the main surface of themultiple panel 15 in a lump. As shown inFIG. 14 , theresin sealing body 33 which has sealed up theplural semiconductor chips 2 in a lump is formed only on the main surface of themultiple panel 15 by this step. - Since a plurality of
resin injection gates 32 are formed along one of the long sides of thecavity 31 so that the resin is uniformly filled into the entire inside of thecavity 31, as shown inFIG. 13 , theresin 33 a injected into the inside of thecavity 31 flows from the above long side toward the other long side of thecavity 31. Therefore, themacroscopic flow direction 34 of theresin 33 a in the inside of thecavity 31 becomes a direction from one long side toward the other long side of thecavity 31. - In this step, groups of the
bonding wires 8 arranged in themacroscopic flow direction 34 of theresin 33 a (in other words, wires extending in a direction perpendicular to themacroscopic flow direction 34 of theresin 33 a) are easily deformed. However, since oneend portion 8b 1 of thesecond bonding wire 8 b out of adjacent bonding wires is connected at a position farther from thefirst side 2× of thesemiconductor chip 2 than the oneend portion 8 a 1 of thefirst bonding wire 8 a, and theother end portion 8b 2 of thesecond bonding wire 8 b is connected at a position farther from thefirst side 2× of thesemiconductor chip 2 than theother end portion 8 a 2 of thefirst bonding wire 8 a, a short circuit between the adjacent bonding wires can be suppressed. - The ball-like solder bumps 10 are then formed on the main surfaces of the
plural electrode pads 6 arranged on the rear surface of themultiple panel 15. The solder bumps 10 are formed, for example, by supplying ball-like solder materials by a ball supplying method and heating them. - Thereafter, the
resin sealing body 33 for sealing up theplural semiconductor chips 2 in a lump is affixed to adicing sheet 26 and then theplural device areas 16 of themultiple panel 15 are separated from one another together with theresin sealing body 33 as shown inFIG. 15 . This separation is carried out by a dicing machine. Thesemiconductor device 1 shown inFIG. 1 andFIG. 2 is almost completed by this step. - The production of the
semiconductor chip 2 will be described hereinbelow with reference to FIGS. 16 to 19. -
FIG. 16 is a plan view of a semiconductor wafer,FIG. 17 is a partially enlarged plan view ofFIG. 16 ,FIG. 18 is a partially enlarged plan view ofFIG. 17 andFIG. 19 is a diagram for explaining a characteristics inspection step. - The
semiconductor wafer 20 made from monocrystal silicon is prepared, and the main surface of thesemiconductor wafer 20 is subjected to a wafer pretreatment step for forming a semiconductor device such as a field effect transistor, a wiring layer and an insulating film in order to form a plurality ofchip forming areas 21 having a control circuit as an integrated circuit in a matrix form as shown inFIG. 16 . The pluralchip forming areas 21 are defined by dividingareas 22 for specifying the boundaries thereof and spaced apart from one another. The pluralchip forming areas 22 are produced by forming a semiconductor device, multi-layer wiring laminate,electrode pads 3, surface protective film and openings on the main surface of thesemiconductor wafer 20. - Thereafter, probe inspection is carried out by using a probe card. The probe inspection is carried out by first aligning the
semiconductor wafer 20 with the probe card and coming theend portion 25 a of theprobe needle 25 of the probe card into contact with one of theplural electrode pads 3 in thechip forming area 21 of thesemiconductor wafer 20. Then, the electric properties of the circuit in thechip forming area 21 are measured with a tester electrically connected to theprobe needle 25 of the probe card. This step is carried out for eachchip forming area 21. Thereby, whether thechip forming area 21 is accepted or not and the grade of electric properties such as operation frequency of thechip forming area 21 are judged. - In this step, as shown in
FIG. 17 andFIG. 18 , a scratch, that is, acontact mark 26 is formed on the connection surface of theelectrode pad 3 by the contact of theprobe needle 25. Since thiscontact mark 26 deteriorates bonding between theelectrode pad 3 and the one end portion of thebonding wire 8, it is necessary to prevent thecontact mark 26 from being formed in the area where one end portion of thebonding wire 8 is connected as much as possible. - In this embodiment, the
electrode pads 3 have a rectangular plane form that their two long opposite sides extend in a direction away from the respective sides of thesemiconductor chip 2 and their short opposite sides extend along the respective sides of thesemiconductor chip 2. Therefore, the contact marks 26 can be formed at positions farther from the sides of thesemiconductor chip 2 than the one end portions of thefirst bonding wires 8 a and closer to the sides of thesemiconductor chip 2 than the one end portions of thesecond bonding wires 8 b by setting the length of the long sides of theelectrode pad 3 to twice or more the length of the long sides of theelectrode pads 3 in the connection areas between theelectrode pad 3 and one end portions of thebonding wires 8, thereby making it possible to prevent the contact marks 26 from being formed in the areas where one end portions of thebonding wires 8 are connected. Also, as it is possible to prevent the contact marks 26 from being formed in the areas where one end portions of thebonding wires 8 are connected without arranging thedistal end portions 25 a of the probe needles 25 in a zigzag form, a probe test can be carried out by using the existing probe card. - Then, the dividing
areas 22 of thesemiconductor wafer 20 are diced with the dicing machine to divide thesemiconductor wafer 20 intochip forming areas 21. Thereby,semiconductor chips 2 are formed. -
FIG. 20 is a diagram showing the positions of the connecting portions when theelectrode pads 3 of thesemiconductor chip 2 and the one end portions of thebonding wires 8 are connected to each other in a zigzag manner. -
FIG. 21 is a diagram showing the positions of the connecting portions when theelectrode pads 3 of thesemiconductor chip 2 and the one end portions of thebonding wires 8 are connected to each other linearly. - As shown in
FIG. 20 andFIG. 21 , thedistance 8 p between the oneend portion 8 a 1 of thefirst bonding wire 8 a connected to thefirst electrode pad 3 a and the oneend portion 8b 1 of thesecond bonding wire 8 b connected to thesecond electrode pad 3 b adjacent to thefirst electrode pad 3 a is wider when theelectrode pads 3 of thesemiconductor chip 2 are connected to the one end portions of thebonding wires 8 in a zigzag manner than when theelectrode pads 3 of thesemiconductor chip 2 are connected to the one end portions of thebonding wires 8 linearly. When the pitches of the electrode pads are the same, theend portion 28 of a capillary is brought into contact with the one end portions of theadjacent bonding wires 3 inFIG. 21 whereas theend portion 28 of the capillary does not contact the one end portions of the adjacent bonding wires inFIG. 22 . - Therefore, the deformation of the wires caused by the interference of the capillary at the time of wire bonding can be suppressed without widening the interval between
adjacent electrode pads 3. - Since the
distance 8 p can be increased without widening the pitch of theelectrode pads 3, thepitch 3 p of theelectrode pads 3 can be narrowed by the increase in thedistance 3 p. As a result, the plane size of thesemiconductor chip 2 can be reduced, thereby making it possible to downsize the BGAtype semiconductor device 1. -
FIG. 22 is a plan view of the key section of a BGA type semiconductor device according toEmbodiment 2 of the present invention, andFIG. 23 is a plan view of the key section of the semiconductor chip ofFIG. 22 . - As shown in
FIG. 22 andFIG. 23 , the BGAtype semiconductor device 1 a of thisEmbodiment 2 is basically the same as the above Embodiment in constitution but differs from the above Embodiment in the following. - That is, a plurality of
electrode pads 3 are arranged on the main surface of thesemiconductor chip 2 along each side of thesemiconductor chip 2 and consist offirst electrode pads 3 a andsecond electrode pads 3 b adjacent to thefirst electrode pads 3 a and farther from the respective sides of thesemiconductor chip 2 than thefirst electrode pads 3 a, all of which are arranged alternately in a zigzag manner. The plane form of theelectrode pads 3 is, for example, square. - Even when this
semiconductor chip 2 is used, the same effect as in theabove Embodiment 1 is obtained. - In this embodiment, the
end portions 25 a of the probe needles 25 must be arranged in a zigzag manner, thereby making it difficult to use existing probe cards. -
FIG. 24 is a plan view of the key section of a BGA type semiconductor device according toEmbodiment 3 of the present invention, andFIG. 25 is a sectional view of the key section of the semiconductor device ofFIG. 24 . - As shown in
FIG. 24 andFIG. 25 , the BGAtype semiconductor device 1 b of thisEmbodiment 3 is the same as theabove Embodiment 1 in constitution but differs from theabove Embodiment 1 in that the semiconductor chip sealed up with theresin sealing body 9 has a laminate structure. - A
second semiconductor chip 2 b is formed on afirst semiconductor chip 2 a by anadhesive layer 7, and theelectrode pads 3 a of thefirst semiconductor chip 2 a and theelectrode pads 3 b of thesecond semiconductor chip 2 b are arranged in a zigzag manner likeEmbodiments - The above
second semiconductor chip 2 b is made as thin as 0.1 mm or less, for example, to reduce the thickness of theresin sealing body 9 as much as possible. When the semiconductor chip is made thin, the electrode pads of the upper and lower semiconductor chips become close to each other. However, when the electrode pads are arranged in the same manner as inEmbodiments - Consequently, a semiconductor package which is thin and has high electric reliability can be provided.
- While the invention made by the inventors of the present invention has been described based on the above Embodiments, it is needless to say that the present invention is not limited to the above embodiments and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.
- Effects obtained by a typical one of the inventions disclosed by the present application are briefly described below.
- According to the present invention, a short circuit between adjacent bonding wires can be suppressed.
- According to the present invention, the size of a semiconductor device can be reduced.
Claims (9)
1-29. (canceled)
30. A method of manufacturing semiconductor devices, comprising:
providing a wafer having chip forming areas, each chip forming area having a plurality of rectangular bonding pads arranged along its periphery and each rectangular bonding pad having longitudinally opposite first and second connection ends;
testing a circuit formed in each of said chip forming areas by a probing procedure in which a test probe contacts a substantially central position of each rectangular bonding pad;
dicing said wafer along said chip forming areas to form a plurality of semiconductor chips each having a plurality of said bonding pads and each having a circuit that has been tested by said probing procedure;
mounting said plurality of semiconductor chips on device forming areas of a wiring substrate, each device forming area having a plurality of electrodes in a zig-zag formation; and
electrically connecting said plurality of bonding pads of each of said semiconductor chips with designated electrodes of said plurality of electrodes by bonding wires, the connections to the rectangular bonding pads of each pair of adjacent bonding pads being made to a first connection end of one bonding pad of the pair and to a second connection end of the other bonding pad of the pair.
31. A method according to claim 30 , wherein the rectangular bonding pads of each chip forming area include a set of bonding pads arranged along one side of that chip forming area, and the first end of each bonding pad of the set is closer to the one side of the chip forming area than the second end.
32. A method according to claim 31 , wherein electrodes of the plurality are arranged along said one side of the chip forming area in first and second rows, the first row being closer to said one side of the chip forming area than the second row.
33. A method according to claim 32 , wherein the connecting of the rectangular bonding pads and the electrodes uses a plurality of wires, wires connecting the first row of the electrodes to the bonding pads being shorter than wires connecting the second row of electrodes to the bonding pads.
34. A method according to claim 30 , wherein two long opposite sides of each rectangular bonding pad extend in a direction away from an adjacent side of a chip forming area.
35. A method according to claim 34 , wherein the long sides of each of the bonding pads are longer than the first connection end length and the second connection end length combined.
36. A method according to claim 30 , wherein the bonding pads are arranged with a pitch that is narrower than a pitch of the electrodes.
37. A method according to claim 30 , wherein a probe needle contact mark is formed on a surface of each bonding pad between the first and second connection ends of the bonding pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/035,999 US20050121805A1 (en) | 2002-05-21 | 2005-01-18 | Semiconductor device and a method of manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2002-146321 | 2002-05-21 | ||
JP2002146321A JP2003338519A (en) | 2002-05-21 | 2002-05-21 | Semiconductor device and its manufacturing method |
US10/430,279 US6900551B2 (en) | 2002-05-21 | 2003-05-07 | Semiconductor device with alternate bonding wire arrangement |
US11/035,999 US20050121805A1 (en) | 2002-05-21 | 2005-01-18 | Semiconductor device and a method of manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/430,279 Division US6900551B2 (en) | 2002-05-21 | 2003-05-07 | Semiconductor device with alternate bonding wire arrangement |
Publications (1)
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US20050121805A1 true US20050121805A1 (en) | 2005-06-09 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/430,279 Expired - Lifetime US6900551B2 (en) | 2002-05-21 | 2003-05-07 | Semiconductor device with alternate bonding wire arrangement |
US11/035,999 Abandoned US20050121805A1 (en) | 2002-05-21 | 2005-01-18 | Semiconductor device and a method of manufacturing the same |
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Application Number | Title | Priority Date | Filing Date |
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US10/430,279 Expired - Lifetime US6900551B2 (en) | 2002-05-21 | 2003-05-07 | Semiconductor device with alternate bonding wire arrangement |
Country Status (5)
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US (2) | US6900551B2 (en) |
JP (1) | JP2003338519A (en) |
KR (1) | KR20040014167A (en) |
CN (1) | CN100481414C (en) |
TW (1) | TWI297184B (en) |
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US20180182644A1 (en) * | 2016-12-27 | 2018-06-28 | Renesas Electronics Corporation | Method for manufacturing a semiconductor device |
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---|---|---|---|---|
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Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5932323A (en) * | 1992-03-10 | 1999-08-03 | Texas Instruments Incorporated | Method and apparatus for mounting, inspecting and adjusting probe card needles |
US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
US6025640A (en) * | 1997-07-16 | 2000-02-15 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device |
US6251694B1 (en) * | 1999-05-26 | 2001-06-26 | United Microelectronics Corp. | Method of testing and packaging a semiconductor chip |
US6369407B1 (en) * | 1999-02-09 | 2002-04-09 | Rohm Co., Ltd. | Semiconductor device |
US6429532B1 (en) * | 2000-05-09 | 2002-08-06 | United Microelectronics Corp. | Pad design |
US6534879B2 (en) * | 2000-02-25 | 2003-03-18 | Oki Electric Industry Co., Ltd. | Semiconductor chip and semiconductor device having the chip |
US6539341B1 (en) * | 2000-11-06 | 2003-03-25 | 3Com Corporation | Method and apparatus for log information management and reporting |
US6713881B2 (en) * | 2000-05-29 | 2004-03-30 | Texas Instruments Incorporated | Semiconductor device and method of manufacturing same |
US6734572B2 (en) * | 2002-03-21 | 2004-05-11 | Nanya Technology Corporation | Pad structure for bonding pad and probe pad and manufacturing method thereof |
US6844631B2 (en) * | 2002-03-13 | 2005-01-18 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0770553B2 (en) * | 1988-09-26 | 1995-07-31 | 日本電気株式会社 | Method for manufacturing semiconductor integrated circuit device |
JPH0634983A (en) | 1992-07-17 | 1994-02-10 | Sharp Corp | Sticking device |
JP3000975B2 (en) * | 1997-10-20 | 2000-01-17 | 富士通株式会社 | Semiconductor element mounting structure |
US6157085A (en) * | 1998-04-07 | 2000-12-05 | Citizen Watch Co., Ltd. | Semiconductor device for preventing exfoliation from occurring between a semiconductor chip and a resin substrate |
US6373143B1 (en) * | 1998-09-24 | 2002-04-16 | International Business Machines Corporation | Integrated circuit having wirebond pads suitable for probing |
TW410446B (en) * | 1999-01-21 | 2000-11-01 | Siliconware Precision Industries Co Ltd | BGA semiconductor package |
US6348742B1 (en) * | 1999-01-25 | 2002-02-19 | Clear Logic, Inc. | Sacrificial bond pads for laser configured integrated circuits |
JP3437477B2 (en) * | 1999-02-10 | 2003-08-18 | シャープ株式会社 | Wiring board and semiconductor device |
US6285077B1 (en) * | 1999-08-19 | 2001-09-04 | Lsi Logic Corporation | Multiple layer tape ball grid array package |
JP2001144214A (en) | 1999-11-17 | 2001-05-25 | Canon Inc | Semiconductor device and bonding structure thereof |
US6291898B1 (en) * | 2000-03-27 | 2001-09-18 | Advanced Semiconductor Engineering, Inc. | Ball grid array package |
US6541844B2 (en) * | 2000-07-17 | 2003-04-01 | Rohm Co., Ltd. | Semiconductor device having substrate with die-bonding area and wire-bonding areas |
JP2002043356A (en) * | 2000-07-31 | 2002-02-08 | Nec Corp | Semiconductor wafer, semiconductor device and manufacturing method therefor |
US6538336B1 (en) * | 2000-11-14 | 2003-03-25 | Rambus Inc. | Wirebond assembly for high-speed integrated circuits |
US6417576B1 (en) * | 2001-06-18 | 2002-07-09 | Amkor Technology, Inc. | Method and apparatus for attaching multiple metal components to integrated circuit modules |
SG117395A1 (en) * | 2001-08-29 | 2005-12-29 | Micron Technology Inc | Wire bonded microelectronic device assemblies and methods of manufacturing same |
US6476506B1 (en) * | 2001-09-28 | 2002-11-05 | Motorola, Inc. | Packaged semiconductor with multiple rows of bond pads and method therefor |
TW510034B (en) * | 2001-11-15 | 2002-11-11 | Siliconware Precision Industries Co Ltd | Ball grid array semiconductor package |
US6621140B1 (en) * | 2002-02-25 | 2003-09-16 | Rf Micro Devices, Inc. | Leadframe inductors |
-
2002
- 2002-05-21 JP JP2002146321A patent/JP2003338519A/en active Pending
-
2003
- 2003-05-07 US US10/430,279 patent/US6900551B2/en not_active Expired - Lifetime
- 2003-05-07 TW TW92112447A patent/TWI297184B/en not_active IP Right Cessation
- 2003-05-14 KR KR1020030030463A patent/KR20040014167A/en not_active Application Discontinuation
- 2003-05-20 CN CNB031237061A patent/CN100481414C/en not_active Expired - Fee Related
-
2005
- 2005-01-18 US US11/035,999 patent/US20050121805A1/en not_active Abandoned
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5932323A (en) * | 1992-03-10 | 1999-08-03 | Texas Instruments Incorporated | Method and apparatus for mounting, inspecting and adjusting probe card needles |
US6025640A (en) * | 1997-07-16 | 2000-02-15 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device |
US6008532A (en) * | 1997-10-23 | 1999-12-28 | Lsi Logic Corporation | Integrated circuit package having bond fingers with alternate bonding areas |
US6369407B1 (en) * | 1999-02-09 | 2002-04-09 | Rohm Co., Ltd. | Semiconductor device |
US6251694B1 (en) * | 1999-05-26 | 2001-06-26 | United Microelectronics Corp. | Method of testing and packaging a semiconductor chip |
US6534879B2 (en) * | 2000-02-25 | 2003-03-18 | Oki Electric Industry Co., Ltd. | Semiconductor chip and semiconductor device having the chip |
US6429532B1 (en) * | 2000-05-09 | 2002-08-06 | United Microelectronics Corp. | Pad design |
US6713881B2 (en) * | 2000-05-29 | 2004-03-30 | Texas Instruments Incorporated | Semiconductor device and method of manufacturing same |
US6539341B1 (en) * | 2000-11-06 | 2003-03-25 | 3Com Corporation | Method and apparatus for log information management and reporting |
US6844631B2 (en) * | 2002-03-13 | 2005-01-18 | Freescale Semiconductor, Inc. | Semiconductor device having a bond pad and method therefor |
US6734572B2 (en) * | 2002-03-21 | 2004-05-11 | Nanya Technology Corporation | Pad structure for bonding pad and probe pad and manufacturing method thereof |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100320592A1 (en) * | 2006-12-29 | 2010-12-23 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
US8525306B2 (en) | 2010-07-21 | 2013-09-03 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US8710637B2 (en) | 2010-07-21 | 2014-04-29 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US10777507B2 (en) | 2016-02-23 | 2020-09-15 | Renesas Electronics Corporation | Semiconductor device including a pad and a wiring line arranged for bringing a probe into contact with the pad and method of manufacturing the same |
US10818601B1 (en) | 2016-02-23 | 2020-10-27 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
US20180182644A1 (en) * | 2016-12-27 | 2018-06-28 | Renesas Electronics Corporation | Method for manufacturing a semiconductor device |
US10128130B2 (en) * | 2016-12-27 | 2018-11-13 | Renesas Electronics Corporation | Method for manufacturing a semiconductor device |
US20190306990A1 (en) * | 2017-03-14 | 2019-10-03 | Innolux Corporation | Display device and manufacturing method thereof |
US10820425B2 (en) * | 2017-03-14 | 2020-10-27 | Innolux Corporation | Display device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
KR20040014167A (en) | 2004-02-14 |
TW200405491A (en) | 2004-04-01 |
JP2003338519A (en) | 2003-11-28 |
CN100481414C (en) | 2009-04-22 |
US6900551B2 (en) | 2005-05-31 |
CN1459855A (en) | 2003-12-03 |
US20030218245A1 (en) | 2003-11-27 |
TWI297184B (en) | 2008-05-21 |
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