JP5294351B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP5294351B2
JP5294351B2 JP2011081991A JP2011081991A JP5294351B2 JP 5294351 B2 JP5294351 B2 JP 5294351B2 JP 2011081991 A JP2011081991 A JP 2011081991A JP 2011081991 A JP2011081991 A JP 2011081991A JP 5294351 B2 JP5294351 B2 JP 5294351B2
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Prior art keywords
electrode pads
semiconductor chip
wire
electrode
electrode pad
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Expired - Fee Related
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JP2011081991A
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Japanese (ja)
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JP2011155292A (en
Inventor
安己 堤
孝志 三輪
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact semiconductor device. <P>SOLUTION: A method of manufacturing the semiconductor device includes steps of: electrically connecting a plurality of first electrode pads (a) of a semiconductor chip 5 to a plurality of first connection portions 3b1 of a wiring board 2, respectively, through a plurality of first wires 10b1; electrically connecting second electrode pads (b) to a plurality of second connection portions 3b2 of the wiring board, respectively, through second wires 10b2; and electrically connecting third electrode pads (c) to a plurality of third connection portions 3b3 of the wiring board, respectively, through third wires 10b3. The plurality of first wires 10b1 are connected to first portions of the plurality of first connection portions 3b1, respectively, the third wires 10b3 are connected to second portions of the third connection portions 3b3, and the pluralities of first wires 10b1, second wires 10b2 and third wires 10b3 are extended from the plurality of electrode pads through a center portion of a second side of the semiconductor chip 5 in plan view at an acute angle to a virtual line 5s orthogonal to the second side. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

本発明は、半導体装置及びその製造技術に関し、特に、半導体チップの電極パッドと配線基板の電極パッドとをボンディングワイヤで接続する半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor device in which an electrode pad of a semiconductor chip and an electrode pad of a wiring board are connected by a bonding wire.

半導体装置として、例えばＢＧＡ（Ｂall Ｇrid Ａrray）型と呼称される半導体装置が知られている。このＢＧＡ型半導体装置は、インターポーザと呼ばれる配線基板の主面側に半導体チップを搭載し、配線基板の主面と反対側の裏面側に外部接続用端子としてボール状の半田バンプを複数配置したパッケージ構造になっている。   As a semiconductor device, for example, a semiconductor device called a BGA (Ball Grid Array) type is known. This BGA type semiconductor device is a package in which a semiconductor chip is mounted on the main surface side of a wiring board called an interposer, and a plurality of ball-like solder bumps are arranged as external connection terminals on the back surface side opposite to the main surface of the wiring board. It has a structure.

ＢＧＡ型半導体装置においては、様々な構造のものが開発され、製品化されているが、大別するとフェースアップボンディング構造（ワイヤボンディング構造）とフェースダウンボンディング構造に分類される。フェースアップボンディング構造では、半導体チップの主面（回路形成面）に配置された電極パッドと、配線基板の主面に配置された電極パッド（配線の一部からなる接続部）との電気的な接続をボンディングワイヤで行っている。フェースダウンボンディング構造では、半導体チップの主面に配置された電極パッドと、配線基板の主面に配置された電極パッドとの電気的な接続をこれらの電極パッド間に介在された突起状電極（例えば半田バンプ、スタッドバンプ等）で行っている。   BGA type semiconductor devices having various structures have been developed and commercialized, but are roughly classified into a face-up bonding structure (wire bonding structure) and a face-down bonding structure. In the face-up bonding structure, an electrical connection between an electrode pad arranged on the main surface (circuit forming surface) of the semiconductor chip and an electrode pad (connecting portion made up of a part of the wiring) arranged on the main surface of the wiring board. Connection is made with a bonding wire. In the face-down bonding structure, the electrical connection between the electrode pads arranged on the main surface of the semiconductor chip and the electrode pads arranged on the main surface of the wiring board is a protruding electrode (between these electrode pads ( For example, solder bumps, stud bumps, etc.).

フェースアップボンディング構造のＢＧＡ型半導体装置については、例えば、特開２００１−１４４２１４号公報に開示されている。また、フェースダウンボンディング構造のＢＧＡ型半導体装置については、例えば、特開平６−３４９８３号公報に開示されている。   A BGA type semiconductor device having a face-up bonding structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-144214. A BGA type semiconductor device having a face-down bonding structure is disclosed in, for example, Japanese Patent Application Laid-Open No. 6-34983.

また、特開２００３−３１６１０号公報には、半導体チップの主面にその一辺に沿って配置された複数の電極パッドと、配線基板の主面に前記半導体チップの一辺に沿って２列で配置された複数の電極パッドとを複数のボンディングワイヤで夫々電気的に接続するワイヤボンディングにおいて、先行形成されたワイヤとキャピラリとの干渉を避ける技術が開示されている。   Japanese Patent Application Laid-Open No. 2003-31610 discloses a plurality of electrode pads arranged along one side of a main surface of a semiconductor chip, and two rows arranged along one side of the semiconductor chip on a main surface of a wiring board. In wire bonding in which a plurality of formed electrode pads are electrically connected by a plurality of bonding wires, a technique for avoiding interference between the previously formed wire and the capillary is disclosed.

特開２００１−１４４２１４号公報JP 2001-144214 A 特開平６−３４９８３号公報JP-A-6-34983 特開２００３−３１６１０号公報JP 2003-31610 A

近年、携帯電話、携帯型パーソナルコンピュータ等の電子機器の小型化が進み、これらの電子機器に組み込まれるＢＧＡ型半導体装置においても小型化が要求されている。そこで、本発明者は、既存の製造設備が流用でき、フェースダウン構造に比較すると低コストで製造が可能なフェースアップボンディング構造を有するＢＧＡ型半導体装置の小型化について検討した結果、以下の問題点を見出した。   In recent years, electronic devices such as mobile phones and portable personal computers have been downsized, and BGA type semiconductor devices incorporated in these electronic devices are also required to be downsized. Therefore, the present inventor has examined the downsizing of a BGA type semiconductor device having a face-up bonding structure that can be used at a low cost compared to the face-down structure because the existing manufacturing equipment can be used. I found.

ＢＧＡ型半導体装置の小型化を図るためには、配線基板の平面サイズを小さくする必要がある。配線基板の平面サイズを小さくするためには、配線基板の電極パッドの配列ピッチを狭くし、複数の電極パッドからなるパッド列の長さを短くする必要がある。   In order to reduce the size of the BGA type semiconductor device, it is necessary to reduce the plane size of the wiring board. In order to reduce the planar size of the wiring board, it is necessary to reduce the arrangement pitch of the electrode pads on the wiring board and to shorten the length of the pad row composed of a plurality of electrode pads.

ＢＧＡ型半導体装置においては、半導体チップの主面にその一辺に沿って配置された複数の電極パッド（ボンディングパッド）と、この複数の電極パッドに対応して配線基板の主面に配置された複数の電極パッド（接続部）とを複数のボンディングワイヤで電気的に接続している。従来の配線基板においては、複数の電極パッドを１列で配置することが主であったが、この１列パッド配置では、要求される基板サイズやワイヤ長規格を満足できないことから、２列パッド配置、３列パッド配置といった多列パッド配置が現在主流になっている。   In the BGA type semiconductor device, a plurality of electrode pads (bonding pads) arranged along one side of the main surface of the semiconductor chip and a plurality of electrode pads arranged on the main surface of the wiring board corresponding to the plurality of electrode pads. The electrode pads (connection portions) are electrically connected by a plurality of bonding wires. In the conventional wiring board, a plurality of electrode pads are mainly arranged in one row. However, since this one-row pad arrangement cannot satisfy the required substrate size and wire length standard, the two-row pad is used. Multi-row pad arrangements such as an arrangement and a three-row pad arrangement are currently mainstream.

多列パッド配置は、１列パッド配置と比較して各パッド列の長さが短くなるが、半導体チップに搭載される集積回路の多機能化や高集積化に伴って電極パッド数が増加傾向にあるため、半導体装置の小型化を図るには多列パッド配置においても電極パッドの配列ピッチを狭くし、各パッド列の長さを短くする必要がある。   In the multi-row pad arrangement, the length of each pad line is shorter than that in the single-row pad arrangement, but the number of electrode pads tends to increase as the integrated circuits mounted on the semiconductor chip become more multifunctional and highly integrated. Therefore, in order to reduce the size of the semiconductor device, it is necessary to reduce the arrangement pitch of the electrode pads and shorten the length of each pad row even in the multi-row pad arrangement.

しかしながら、従来の多列パッド配置、例えば２列パッド配置では、半導体チップ側から数えて１列目の電極パッドに繋がる配線（電極パッドから引き出される配線）が２列目の電極パッド間を通って引き回されているため、２列目の電極パッドの配列ピッチを狭くすることが困難である。   However, in the conventional multi-row pad arrangement, for example, the two-row pad arrangement, the wiring connected to the first electrode pad counted from the semiconductor chip side (wiring drawn from the electrode pad) passes between the second electrode pads. Since it is drawn, it is difficult to narrow the arrangement pitch of the electrode pads in the second row.

また、パッド列の長さが長くなると、半導体チップから離れて配線基板の電極パッドを配置する必要があり、これに伴って半導体チップの電極パッドと配線基板の電極パッドとを電気的に接続するボンディングワイヤの長さが長くなる。また、加工精度の違いから配線基板の電極パッドの配列ピッチは半導体チップの電極パッドの配列ピッチよりも広くなっているため、ボンディングワイヤの長さは、半導体チップの辺の中心からその端に向かって徐々に長くなるが、配線基板のパッド列の長さが長くなると、更にボンディングワイヤの長さが長くなる。このため、トランスファモールディング法に基づいて樹脂封止体を形成する時、ボンディングワイヤの形状が樹脂の流れによって変形するワイヤ流れにより、隣り合うボンディングワイヤ同士が短絡するといった不具合が発生し易くなる。この不具合は、半導体装置の製造歩留まり低下の要因となる。   Further, when the length of the pad row is increased, it is necessary to dispose the electrode pads of the wiring board away from the semiconductor chip, and accordingly, the electrode pads of the semiconductor chip and the electrode pads of the wiring board are electrically connected. The length of the bonding wire is increased. Also, because of the difference in processing accuracy, the arrangement pitch of the electrode pads on the wiring board is wider than the arrangement pitch of the electrode pads on the semiconductor chip, so that the length of the bonding wire extends from the center of the side of the semiconductor chip to its end. However, as the length of the pad row of the wiring board increases, the length of the bonding wire further increases. For this reason, when the resin sealing body is formed based on the transfer molding method, a problem that adjacent bonding wires are short-circuited easily occurs due to the wire flow in which the shape of the bonding wire is deformed by the flow of the resin. This defect causes a decrease in the manufacturing yield of the semiconductor device.

また、配線基板の電極パッドの配列ピッチは半導体チップの電極パッドの配列ピッチよりも広くなっているため、ボンディングワイヤは、半導体チップの一辺の中心を横切ってその一辺と直行する仮想線に対して鋭角をなす角度で半導体チップ側から放射状に延在するが、配線基板のパッド列の長さが長くなると、ボンディングワイヤの前記仮想線に対する角度が広くなる。このため、半導体チップの電極パッドにおいて、隣り合う２つの電極パッドのうちの一方の電極パッドにボンディングワイヤを接続し、その後、他方の電極パッドにボンディングワイヤを接続する時、一方の電極パッドに接続されたボンディングワイヤにキャピラリが干渉するといった不具合が発生し易くなる。この不具合は、半導体装置の製造歩留まり低下の要因となる。   In addition, since the arrangement pitch of the electrode pads on the wiring board is wider than the arrangement pitch of the electrode pads on the semiconductor chip, the bonding wire crosses the center of one side of the semiconductor chip with respect to a virtual line perpendicular to the one side. Although extending radially from the semiconductor chip side at an acute angle, the angle of the bonding wire with respect to the virtual line increases as the length of the pad row of the wiring board increases. For this reason, in an electrode pad of a semiconductor chip, when a bonding wire is connected to one of the two adjacent electrode pads and then the bonding wire is connected to the other electrode pad, it is connected to one electrode pad. The problem that the capillary interferes with the bonded bonding wire is likely to occur. This defect causes a decrease in the manufacturing yield of the semiconductor device.

本発明の目的は、半導体装置の小型化を図ることが可能な技術を提供することにある。   An object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.

また、本発明の他の目的は、半導体装置の製造歩留まり向上を図ることが可能な技術を提供することにある。   Another object of the present invention is to provide a technique capable of improving the manufacturing yield of semiconductor devices.

本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。   The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
（１）半導体装置は、
主面に形成され、かつ前記主面の一辺に沿って配置された複数の電極パッドを有する半導体チップと、
主面に前記半導体チップが搭載された配線基板と、
前記配線基板の前記主面に形成され、かつ前記半導体チップの前記一辺に沿って配置された複数の第１の接続部と、
前記配線基板の前記主面に形成され、かつ前記半導体チップの前記一辺から前記複数の第１の接続部よりも離れた位置に前記半導体チップの前記一辺に沿って配置された複数の第２の接続部と、
前記配線基板の前記主面に形成され、かつ前記複数の第１の接続部に夫々繋がる複数の第１の配線と、
前記配線基板の前記主面に形成され、かつ前記複数の第２の接続部に夫々繋がる複数の第２の配線と、
前記複数の電極パッドと、前記複数の第１及び第２の接続部とを夫々接続する複数のボンディングワイヤと、
前記半導体チップ、及び前記複数のボンディングワイヤを封止する樹脂封止体とを有し、
前記複数の第１の配線は、前記複数の第１の接続部の夫々から前記半導体チップの前記一辺に向かって延在し、
前記複数の第２の配線は、前記複数の第２の接続部の夫々から前記半導体チップの前記一辺と反対側に向かって延在している。
（２）前記手段（１）において、
前記複数の第１の配線の一端部は、前記複数の第１の接続部に夫々繋がり、
前記複数の第２の配線の一端部は、前記複数の第２の接続部に夫々繋がっている。
（３）前記手段（１）において、
前記第１の接続部の配列ピッチ、及び前記第２の接続部の配列ピッチは、前記電極パッドの配列ピッチの２倍である。
（４）前記手段（１）において、
前記第１及び第２の接続部、並びに前記電極パッドは、平面が方形状で形成され、
前記第１の接続部の一辺は、対応する前記電極パッドの一辺と向かい合っており、
前記第２の接続部の一辺は、対応する前記電極パッドの一辺と向かい合っている。
（５）前記手段（１）において、
前記第２の接続部は、隣り合う２つの前記第１の接続部の間に配置されている。
（６）前記手段（５）において、
前記第２の接続部は、前記２つの第１の接続部における配列ピッチの中間に配置されている。
（７）前記手段（１）において、
前記配線基板は、表層及び内層の配線層を有する多層配線構造になっている。
（８）前記手段（１）において、
前記配線基板は、表層及び内層の配線層を有する多層配線構造のビルドアップ基板である。
（９）前記手段（１）において、
前記配線基板は、表層及び内層の配線層を有する多層配線構造のセミアディティブ基板である。
（１０）半導体装置の製造において、
（ａ）主面に形成され、かつ前記主面の一辺に沿って第１の電極パッド、第２の電極パッド及び第３の電極パッドがこの順番で繰り返し配置された半導体チップを準備する工程と、
（ｂ）前記半導体チップが搭載されるチップ搭載部と、前記チップ搭載部の外側に前記複数の第１の電極パッドに対応して前記半導体チップの一辺に沿って配置された複数の第１の接続部と、前記半導体チップの一辺から前記複数の第１の接続部よりも離れた位置に前記複数の第２の電極パッドに対応して前記半導体チップの一辺に沿って配置された複数の第２の接続部と、前記半導体チップの一辺から前記複数の第２の接続部よりも離れた位置に前記複数の第３の電極パッドに対応して前記半導体チップの一辺に沿って配置された複数の第３の接続部とを有する配線基板を準備する工程と、
（ｃ）前記複数の第１の接続部が前記半導体チップの一辺に沿う状態で前記配線基板のチップ搭載部に前記半導体チップを搭載する工程と、
（ｄ）前記複数の第１の電極パッドと前記複数の第１の接続部とを複数の第１のボンディングワイヤで夫々電気的に接続する工程と、
（ｅ）前記複数の第２の電極パッドと前記複数の第２の接続部とを前記複数の第１のボンディングワイヤよりもループ高さが高い複数の第２のボンディングワイヤで夫々電気的に接続する工程と、
（ｆ）前記複数の第３の電極パッドと前記複数の第３の接続部とを前記第２のボンディングワイヤよりもループ高さが高い複数の第３のボンディングワイヤで夫々電気的に接続する工程と、
（ｇ）前記半導体チップ、及び前記複数の第１乃至第３のボンディングワイヤを樹脂で封止する工程とを有し、
前記複数の第１乃至第３のボンディングワイヤは、前記半導体チップの一辺の中心を横切って前記半導体チップの一辺と直行する仮想線に対して鋭角をなす角度で延在し、
前記第３のボンディングワイヤと前記第３の電極パッドとの接続は、前記第１のボンディングワイヤと前記第１の電極パッドとの接続よりも前記半導体チップの一辺から離れた位置で行われ、
前記（ｅ）工程、（ｄ）工程、及び（ｆ）工程は、この順番で行われる。
（１１）前記手段（１０）において、
前記第２のボンディングワイヤと前記第２の電極パッドとの接続は、前記第３のボンディングワイヤと前記第３の電極パッドとの接続よりも前記半導体チップの一辺から近い位置で行われる。
（１２）前記手段（１０）において、
前記第２のボンディングワイヤと前記第２の電極パッドとの接続は、前記第１のボンディングワイヤと前記第１の電極パッドとの接続よりも前記半導体チップの一辺から離れた位置で行われる。
（１３）前記手段（１０）において、
前記複数の第１乃至第３の電極パッドは、互いに反対側に位置する２つの長辺が前記半導体チップの一辺から遠ざかる方向に沿って延在する長方形状の平面形状になっている。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) The semiconductor device
A semiconductor chip having a plurality of electrode pads formed on the main surface and disposed along one side of the main surface;
A wiring board on which the semiconductor chip is mounted on the main surface;
A plurality of first connection portions formed on the main surface of the wiring board and disposed along the one side of the semiconductor chip;
A plurality of second portions formed on the main surface of the wiring board and disposed along the one side of the semiconductor chip at positions away from the one side of the semiconductor chip than the plurality of first connection portions. A connection,
A plurality of first wirings formed on the main surface of the wiring board and respectively connected to the plurality of first connection portions;
A plurality of second wirings formed on the main surface of the wiring board and respectively connected to the plurality of second connection portions;
A plurality of bonding wires respectively connecting the plurality of electrode pads and the plurality of first and second connection portions;
A resin sealing body for sealing the semiconductor chip and the plurality of bonding wires;
The plurality of first wirings extend from each of the plurality of first connection portions toward the one side of the semiconductor chip,
The plurality of second wirings extend from each of the plurality of second connection portions toward the side opposite to the one side of the semiconductor chip.
(2) In the means (1),
One end portions of the plurality of first wires are connected to the plurality of first connection portions, respectively.
One end portions of the plurality of second wires are connected to the plurality of second connection portions, respectively.
(3) In said means (1),
The arrangement pitch of the first connection parts and the arrangement pitch of the second connection parts are twice the arrangement pitch of the electrode pads.
(4) In the means (1),
The first and second connection portions and the electrode pad are formed with a rectangular plane.
One side of the first connection portion faces one side of the corresponding electrode pad,
One side of the second connection portion faces one side of the corresponding electrode pad.
(5) In the means (1),
The second connection portion is disposed between two adjacent first connection portions.
(6) In the means (5),
The second connection portion is disposed in the middle of the arrangement pitch of the two first connection portions.
(7) In the means (1),
The wiring board has a multilayer wiring structure having a surface layer and an inner layer.
(8) In the means (1),
The wiring board is a build-up board having a multilayer wiring structure having a surface layer and an inner wiring layer.
(9) In the means (1),
The wiring board is a semi-additive board having a multilayer wiring structure having a surface layer and an inner wiring layer.
(10) In manufacturing a semiconductor device,
(A) preparing a semiconductor chip formed on the main surface and having the first electrode pad, the second electrode pad, and the third electrode pad repeatedly arranged in this order along one side of the main surface; ,
(B) a chip mounting portion on which the semiconductor chip is mounted, and a plurality of first electrodes arranged along one side of the semiconductor chip corresponding to the plurality of first electrode pads outside the chip mounting portion. A plurality of second electrodes arranged along one side of the semiconductor chip corresponding to the plurality of second electrode pads at a position away from one side of the semiconductor chip than the plurality of first connection parts; And a plurality of connecting portions arranged along one side of the semiconductor chip corresponding to the plurality of third electrode pads at positions farther from one side of the semiconductor chip than the plurality of second connecting portions. Preparing a wiring board having a third connection portion of
(C) mounting the semiconductor chip on the chip mounting portion of the wiring board in a state where the plurality of first connection portions are along one side of the semiconductor chip;
(D) electrically connecting the plurality of first electrode pads and the plurality of first connection portions with a plurality of first bonding wires, respectively.
(E) The plurality of second electrode pads and the plurality of second connection portions are electrically connected to each other by a plurality of second bonding wires having a loop height higher than that of the plurality of first bonding wires. And a process of
(F) electrically connecting the plurality of third electrode pads and the plurality of third connection portions with a plurality of third bonding wires each having a loop height higher than that of the second bonding wires. When,
(G) sealing the semiconductor chip and the plurality of first to third bonding wires with a resin;
The plurality of first to third bonding wires extend at an angle that forms an acute angle with respect to a virtual line orthogonal to one side of the semiconductor chip across the center of one side of the semiconductor chip,
The connection between the third bonding wire and the third electrode pad is performed at a position farther from one side of the semiconductor chip than the connection between the first bonding wire and the first electrode pad.
The step (e), the step (d), and the step (f) are performed in this order.
(11) In the means (10),
The connection between the second bonding wire and the second electrode pad is performed at a position closer to one side of the semiconductor chip than the connection between the third bonding wire and the third electrode pad.
(12) In the means (10),
The connection between the second bonding wire and the second electrode pad is performed at a position farther from one side of the semiconductor chip than the connection between the first bonding wire and the first electrode pad.
(13) In the means (10),
The plurality of first to third electrode pads have a rectangular planar shape in which two long sides located on opposite sides extend along a direction away from one side of the semiconductor chip.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

本発明によれば、半導体装置の小型化を図ることができる。
本発明によれば、半導体装置の製造歩留まり向上を図ることができる。 According to the present invention, it is possible to reduce the size of a semiconductor device.
According to the present invention, it is possible to improve the manufacturing yield of semiconductor devices.

本発明の実施例１である半導体装置の内部構造を示す模式的平面図である。1 is a schematic plan view showing an internal structure of a semiconductor device that is Embodiment 1 of the present invention. 図１におけるボンディングワイヤの一部を省略した状態を示す模式的平面図である。FIG. 2 is a schematic plan view showing a state in which a part of the bonding wire in FIG. 1 is omitted. 図１のａ’−ａ’線に沿う模式的断面図である。FIG. 2 is a schematic cross-sectional view taken along the line a′-a ′ in FIG. 1. 図１のｂ’−ｂ’線に沿う模式的断面図である。It is typical sectional drawing which follows the b'-b 'line | wire of FIG. 図１の一部（部分Ａ）を簡略化して示す模式的平面図である。FIG. 2 is a schematic plan view showing a part (part A) of FIG. 1 in a simplified manner. 図５におけるボンディングワイヤを省略して示す模式的平面図である。FIG. 6 is a schematic plan view in which the bonding wires in FIG. 5 are omitted. 図５のｃ’−ｃ’線に沿う模式的断面図である。It is typical sectional drawing which follows the c'-c 'line | wire of FIG. 図５のｄ’−ｄ’線に沿う模式的断面図である。FIG. 6 is a schematic cross-sectional view taken along line d′-d ′ in FIG. 5. 図１の一部（部分Ｂ）を簡略化して示す模式的平面図である。FIG. 2 is a schematic plan view showing a part (part B) of FIG. 1 in a simplified manner. 図９のボンディングワイヤを省略して示す模式的平面図である。FIG. 10 is a schematic plan view in which the bonding wire of FIG. 9 is omitted. 図９のｅ’−ｅ’線に沿う模式的断面図である。FIG. 10 is a schematic cross-sectional view taken along the line e′-e ′ in FIG. 9. 図９のｆ’−ｆ’線に沿う模式的断面図である。FIG. 10 is a schematic cross-sectional view taken along line f′-f ′ in FIG. 9. 図９のｇ’−ｇ’線に沿う模式的断面図である。FIG. 10 is a schematic cross-sectional view taken along the line g′-g ′ of FIG. 9. 本発明の実施例１である半導体装置の製造において、ワイヤボンディング工程を示す模式的平面図である。It is a schematic plan view which shows a wire bonding process in manufacture of the semiconductor device which is Example 1 of this invention. 本発明の実施例１である半導体装置の製造において、ワイヤボンディング工程を示す模式的平面図である。It is a schematic plan view which shows a wire bonding process in manufacture of the semiconductor device which is Example 1 of this invention. 本発明の実施例１である半導体装置の製造において、ワイヤボンディング工程を示す模式的平面図である。It is a schematic plan view which shows a wire bonding process in manufacture of the semiconductor device which is Example 1 of this invention. 本発明の実施例２である半導体装置の概略構成を示す模式的平面図である。It is a typical top view which shows schematic structure of the semiconductor device which is Example 2 of this invention. 図１７のボンディングワイヤを省略して示す模式的平面図である。FIG. 18 is a schematic plan view in which the bonding wire of FIG. 17 is omitted. 本発明の実施例３である半導体装置の概略構成を示す模式的平面図である。It is a typical top view which shows schematic structure of the semiconductor device which is Example 3 of this invention. 図１９のボンディングワイヤを省略して示す模式的平面図である。FIG. 20 is a schematic plan view in which the bonding wire of FIG. 19 is omitted. 本発明の実施例４である半導体装置の概略構成を示す模式的平面図である。It is a typical top view which shows schematic structure of the semiconductor device which is Example 4 of this invention.

以下、図面を参照して本発明の実施例を詳細に説明する。なお、発明の実施例を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments of the invention, those having the same function are given the same reference numerals, and their repeated explanation is omitted.

［実施例１］
本実施例１では、ＢＧＡ型半導体装置として、機能が異なる集積回路が搭載された複数の半導体チップを配線基板に実装して１つのシステムを構築するＳＩＰ（Ｓystem Ｉｎ Ｐackage）型半導体装置に本発明を適用した例について説明する。 [Example 1]
In the first embodiment, as a BGA type semiconductor device, the present invention is an SIP (System In Package) type semiconductor device in which a plurality of semiconductor chips each having an integrated circuit having different functions are mounted on a wiring board to construct one system. An example to which is applied will be described.

図１乃至図１６は、本発明の実施例１である半導体装置に係る図であり、
図１は、半導体装置の内部構造を示す模式的平面図、
図２は、図１におけるボンディングワイヤの一部を省略して示す模式的平面図、
図３は、図１のａ’−ａ’線に沿う模式的断面図、
図４は、図１のｂ’−ｂ’線に沿う模式的断面図、
図５は、図１の一部（部分Ａ）を簡略化して示す模式的平面図、
図６は、図５におけるボンディングワイヤを削除して示す模式的平面図、
図７は、図５のｃ’−ｃ’線に沿う模式的断面図、
図８は、図５のｄ’−ｄ’線に沿う模式的断面図、
図９は、図１の一部（部分Ｂ）を簡略化して示す模式的平面図である。
図１０は、図９のボンディングワイヤを削除して示す模式的平面図、
図１１は、図９のｅ’−ｅ’線に沿う模式的断面図、
図１２は、図９のｆ’−ｆ’線に沿う模式的断面図、
図１３は、図９のｇ’−ｇ’線に沿う模式的断面図、
図１４乃至図１６は、半導体装置の製造において、ワイヤボンディング工程を示す模式的平面図である。 1 to 16 are diagrams related to a semiconductor device which is Embodiment 1 of the present invention.
FIG. 1 is a schematic plan view showing an internal structure of a semiconductor device.
FIG. 2 is a schematic plan view showing a part of the bonding wire in FIG.
3 is a schematic cross-sectional view taken along the line a′-a ′ of FIG.
4 is a schematic cross-sectional view taken along line b′-b ′ of FIG.
FIG. 5 is a schematic plan view showing a part (part A) of FIG.
FIG. 6 is a schematic plan view showing the bonding wire in FIG.
7 is a schematic cross-sectional view taken along the line c′-c ′ in FIG.
8 is a schematic cross-sectional view taken along the line d′-d ′ of FIG.
FIG. 9 is a schematic plan view showing a part (part B) of FIG. 1 in a simplified manner.
FIG. 10 is a schematic plan view showing the bonding wire of FIG.
FIG. 11 is a schematic cross-sectional view along the line e′-e ′ in FIG.
12 is a schematic cross-sectional view taken along line f′-f ′ in FIG.
13 is a schematic cross-sectional view taken along the line g′-g ′ of FIG.
14 to 16 are schematic plan views showing a wire bonding process in manufacturing a semiconductor device.

図１乃至図４に示すように、本実施例１の半導体装置１は、インターポーザとも呼ばれる配線基板２の主面側に、１つの半導体チップ５、並びに２つの半導体チップ（７，８）が実装され、配線基板２の主面と反対側の裏面側に、外部接続用端子として例えばボール状の半田バンプ１２が複数配置されたパッケージ構造になっている。   As shown in FIGS. 1 to 4, in the semiconductor device 1 of the first embodiment, one semiconductor chip 5 and two semiconductor chips (7, 8) are mounted on the main surface side of a wiring board 2, also called an interposer. Thus, a package structure is formed in which a plurality of, for example, ball-shaped solder bumps 12 are arranged as external connection terminals on the back surface side opposite to the main surface of the wiring board 2.

半導体チップ５、並びに半導体チップ（７，８）は、厚さ方向と交差する平面形状が方形状になっている。本実施例１では、半導体チップ５は、例えば５．０ｍｍ×６．７ｍｍの長方形、半導体チップ（７，８）は、例えば１．５３９ｍｍ×６．１３７ｍｍの長方形になっている。半導体チップ５、並びに半導体チップ（７，８）は、これに限定されないが、例えば、主に、半導体基板と、この半導体基板の主面に形成された複数のトランジスタ素子と、前記半導体基板の主面上において絶縁層、配線層の夫々を複数段積み重ねた多層配線層と、この多層配線層を覆うようにして形成された表面保護膜（最終保護膜）とを有する構成になっている。絶縁層は、例えば酸化シリコン膜で形成されている。配線層は、例えばアルミニウム（Ａｌ）、アルミニウム合金、銅（Ｃｕ）、又は銅合金等の金属膜で形成されている。表面保護膜は、例えば、酸化シリコン膜又は窒化シリコン膜等の無機絶縁膜及び有機絶縁膜を積み重ねた多層膜で形成されている。   The semiconductor chip 5 and the semiconductor chips (7, 8) have a square shape that intersects the thickness direction. In the first embodiment, the semiconductor chip 5 has a rectangular shape of, for example, 5.0 mm × 6.7 mm, and the semiconductor chip (7, 8) has a rectangular shape of, for example, 1.539 mm × 6.137 mm. The semiconductor chip 5 and the semiconductor chips (7, 8) are not limited to this, but for example, mainly a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, and a main substrate of the semiconductor substrate. A multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on the surface, and a surface protective film (final protective film) formed so as to cover the multilayer wiring layer are configured. The insulating layer is made of, for example, a silicon oxide film. The wiring layer is formed of a metal film such as aluminum (Al), aluminum alloy, copper (Cu), or copper alloy. The surface protective film is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

半導体チップ５は、互いに反対側に位置する主面（素子形成面，回路形成面）及び裏面を有し、半導体チップ５の主面側には集積回路として例えばデータプロセッサ（ＭＰＵ：Ｍicro Ｐrocessing Ｕnit）が形成されている。   The semiconductor chip 5 has a main surface (element forming surface, circuit forming surface) and a back surface located on opposite sides of each other. On the main surface side of the semiconductor chip 5, for example, a data processor (MPU: Micro Processing Unit) is provided. Is formed.

半導体チップ５の主面には、複数の電極パッド（ボンディングパッド）６ａからなる第１のパッド群、複数の電極パッド（ボンディングパッド）６ｂからなる第２のパッド群、複数の電極パッド（ボンディングパッド）６ｃからなる第３のパッド群、複数の電極パッド（ボンディングパッド）６ｄからなる第４のパッド群が形成されている。第１のパッド群の複数の電極パッド６ａは、半導体チップ５の第１の辺５ａに沿って配置されている。第２のパッド群の複数の電極パッド６ｂは、半導体チップ５の第１の辺５ａとは反対側に位置する第２の辺５ｂに沿って配置されている。第３のパッド群の複数の電極パッド６ｃは、半導体チップ５の第１の辺５ａと交わる第３の辺５ｃに沿って配置されている。第４のパッド群の複数の電極パッド６ｄは、半導体チップ５の第３の辺５ｃとは反対側に位置する第４の辺５ｄに沿って配置されている。各パッド群の複数の電極パッド（６ａ〜６ｄ）は、半導体チップ５の多層配線層のうちの最上層の配線層に形成され、これらの電極パッドに対応して半導体チップ５の表面保護膜に形成されたボンディング開口によって露出されている。   The main surface of the semiconductor chip 5 includes a first pad group composed of a plurality of electrode pads (bonding pads) 6a, a second pad group composed of a plurality of electrode pads (bonding pads) 6b, and a plurality of electrode pads (bonding pads). ) A third pad group composed of 6c and a fourth pad group composed of a plurality of electrode pads (bonding pads) 6d. The plurality of electrode pads 6 a of the first pad group are arranged along the first side 5 a of the semiconductor chip 5. The plurality of electrode pads 6b of the second pad group are arranged along the second side 5b located on the opposite side to the first side 5a of the semiconductor chip 5. The plurality of electrode pads 6 c in the third pad group are arranged along the third side 5 c that intersects the first side 5 a of the semiconductor chip 5. The plurality of electrode pads 6 d of the fourth pad group are arranged along the fourth side 5 d located on the opposite side to the third side 5 c of the semiconductor chip 5. The plurality of electrode pads (6a to 6d) of each pad group are formed on the uppermost wiring layer of the multilayer wiring layers of the semiconductor chip 5, and are formed on the surface protective film of the semiconductor chip 5 corresponding to these electrode pads. It is exposed by the formed bonding opening.

半導体チップ７及び８は、互いに反対側に位置する主面（素子形成面，回路形成面）及び裏面を有し、半導体チップ７及び８の各々の主面側には集積回路として例えばシンクロナス・ディーラム（ＳＤＲＡＭ：Ｓynchronous Ｄynamic Ｒandom Ａccess Ｍemory）が形成されている。半導体チップ７及び８の各々の主面には、各々の第１の辺（７ａ，８ａ）に沿って配置された複数の電極パッド（ボンディングパッド）９が形成されている。   The semiconductor chips 7 and 8 have a main surface (element forming surface, circuit forming surface) and a back surface located on opposite sides, and each main surface side of the semiconductor chips 7 and 8 has, for example, a synchronous circuit as an integrated circuit. A Dyram (SDRAM: Synchronous Dynamic Random Access Memory) is formed. A plurality of electrode pads (bonding pads) 9 arranged along the first sides (7a, 8a) are formed on the main surfaces of the semiconductor chips 7 and 8, respectively.

半導体チップ５は、その裏面が配線基板２の主面と向かい合う状態で配線基板２の主面に接着材を介在して接着固定されている。半導体チップ７は、その裏面が配線基板２の主面と向かい合う状態で配線基板２の主面に接着材を介在して接着固定され、半導体チップ８は、その裏面が半導体チップ７の主面と向かい合う状態で半導体チップ７の主面に接着材を介在して接着固定されている。   The semiconductor chip 5 is bonded and fixed to the main surface of the wiring substrate 2 with an adhesive interposed so that the back surface thereof faces the main surface of the wiring substrate 2. The semiconductor chip 7 is bonded and fixed to the main surface of the wiring substrate 2 with an adhesive interposed in a state where the back surface faces the main surface of the wiring substrate 2, and the back surface of the semiconductor chip 8 is in contact with the main surface of the semiconductor chip 7. In a state of facing each other, the main surface of the semiconductor chip 7 is bonded and fixed with an adhesive interposed.

半導体チップ７及び８は、半導体チップ８の第１の辺８ａの外側に半導体チップ７の電極パッド９が平面的に位置するように位置をずらした状態で多段に積層されている。また、半導体チップ７及び８は、各々の第１の辺（７ａ，８ａ）の伸びる方向が半導体チップ５の第１の辺５ａの伸びる方向と同じ方向を向き、かつ各々の第１の辺（７ａ，８ａ）と反対側の各々の第２の辺（７ｂ，８ｂ）が半導体チップ５の第１の辺５ａ側となるように半導体チップ５から離間して配置されている。   The semiconductor chips 7 and 8 are stacked in multiple stages with the positions shifted so that the electrode pads 9 of the semiconductor chip 7 are planarly positioned outside the first side 8 a of the semiconductor chip 8. Further, in the semiconductor chips 7 and 8, the direction in which each first side (7a, 8a) extends is in the same direction as the direction in which the first side 5a of the semiconductor chip 5 extends, and each first side ( 7a, 8a) and the second side (7b, 8b) on the opposite side to the first side 5a side of the semiconductor chip 5 are arranged apart from the semiconductor chip 5.

配線基板２は、その厚さ方向と交差する平面形状が方形状になっており、本実施例１では例えば９ｍｍ×１１ｍｍの長方形になっている。ここで、配線基板２の平面において、互いに反対側に位置する２つの短辺のうち、一方を第１の辺２ａ、他方を第２の辺２ｂと呼び、互いに反対側に位置する２つの長辺のうち、一方を第３の辺２ｃ、他方を第４の辺２ｄと呼ぶ。   The wiring board 2 has a rectangular planar shape that intersects the thickness direction, and in the first embodiment, the wiring board 2 has a rectangular shape of, for example, 9 mm × 11 mm. Here, in the plane of the wiring board 2, of the two short sides located on the opposite sides, one is called the first side 2 a and the other is the second side 2 b, and the two long sides located on the opposite sides One of the sides is called a third side 2c, and the other is called a fourth side 2d.

半導体チップ５は、その長辺（第１及び第２の辺５ａ，５ｂ）の伸びる方向が配線基板２の短辺（２ａ，２ｂ）の伸びる方向と同じ方向を向く状態で配線基板２の主面に配置されている。   The semiconductor chip 5 has the main side of the wiring substrate 2 in a state where the extending direction of the long side (first and second sides 5a, 5b) faces the same direction as the extending direction of the short side (2a, 2b) of the wiring substrate 2. Arranged on the surface.

配線基板２の主面には、複数の電極パッド（接続部）３ａ１からなるパッド群、複数の電極パッド（接続部）３ａ２からなるパッド群、複数の電極パッド（接続部）３ｂ１からなるパッド群、複数の電極パッド（接続部）３ｂ２からなるパッド群、複数の電極パッド（接続部）３ｂ３からなるパッド群、複数の電極パッド（接続部）３ｃからなるパッド群、複数の電極パッド（接続部）３ｄからなるパッド群、並びに複数の電極パッド（接続部）３ｅからなるパッド群が形成されている。   On the main surface of the wiring board 2, a pad group consisting of a plurality of electrode pads (connection portions) 3a1, a pad group consisting of a plurality of electrode pads (connection portions) 3a2, and a pad group consisting of a plurality of electrode pads (connection portions) 3b1. , A pad group consisting of a plurality of electrode pads (connection parts) 3b2, a pad group consisting of a plurality of electrode pads (connection parts) 3b3, a pad group consisting of a plurality of electrode pads (connection parts) 3c, and a plurality of electrode pads (connection parts) ) A pad group composed of 3d and a pad group composed of a plurality of electrode pads (connection portions) 3e are formed.

複数の電極パッド３ａ１は、半導体チップ５と半導体チップ（７，８）との間において、半導体チップ５の第１の辺５ａの外側に半導体チップ５の第１の辺５ａに沿って配置されている。複数の電極パッド３ａ２は、半導体チップ５と半導体チップ（７，８）との間において、半導体チップ５の第１の辺５ａから複数の電極パッド３ａ１よりも離れた位置に半導体チップ５の第１の辺５ａに沿って配置されている。即ち、半導体チップ５と半導体チップ（７，８）との間には、半導体チップ５の第１の辺５ａに沿って複数の電極パッド（３ａ１，３ａ２）が２列で配置されている。   The plurality of electrode pads 3a1 are arranged along the first side 5a of the semiconductor chip 5 outside the first side 5a of the semiconductor chip 5 between the semiconductor chip 5 and the semiconductor chip (7, 8). Yes. The plurality of electrode pads 3a2 are located between the semiconductor chip 5 and the semiconductor chip (7, 8) at a position farther from the first side 5a of the semiconductor chip 5 than the plurality of electrode pads 3a1. It is arranged along the side 5a. That is, a plurality of electrode pads (3a1, 3a2) are arranged in two rows along the first side 5a of the semiconductor chip 5 between the semiconductor chip 5 and the semiconductor chip (7, 8).

複数の電極パッド３ｂ１は、半導体チップ５の第２の辺５ｂと配線基板２の第２の辺２ｂとの間において、半導体チップ５の第２の辺５ｂの外側に半導体チップ５の第２の辺５ｂに沿って配置されている。複数の電極パッド３ｂ２は、半導体チップ５の第２の辺５ｂと配線基板２の第２の辺２ｂとの間において、半導体チップ５の第２の辺５ｂから複数の電極パッド３ｂ１よりも離れた位置に半導体チップ５の第２の辺５ｂに沿って配置されている。複数の電極パッド３ｂ３は、半導体チップ５の第２の辺５ｂと配線基板２の第２の辺２ｂとの間において、半導体チップ５の第２の辺５ｂから複数の電極パッド３ｂ２よりも離れた位置に半導体チップ５の第２の辺５ｂに沿って配置されている。即ち、半導体チップ５の第２の辺５ｂと配線基板２の第２の辺２ｂとの間には、半導体チップ５の第２の辺５ｂに沿って複数の電極パッド（３ｂ１，３ｂ２，３ｂ３）が３列で配置されている。   The plurality of electrode pads 3b1 are arranged between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring substrate 2 outside the second side 5b of the semiconductor chip 5. Arranged along the side 5b. The plurality of electrode pads 3b2 are located farther from the second side 5b of the semiconductor chip 5 than the plurality of electrode pads 3b1 between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring board 2. The semiconductor chip 5 is disposed at a position along the second side 5b. The plurality of electrode pads 3b3 are located farther from the second side 5b of the semiconductor chip 5 than the plurality of electrode pads 3b2 between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring board 2. The semiconductor chip 5 is disposed at a position along the second side 5b. That is, a plurality of electrode pads (3b1, 3b2, 3b3) are arranged along the second side 5b of the semiconductor chip 5 between the second side 5b of the semiconductor chip 5 and the second side 2b of the wiring board 2. Are arranged in three rows.

複数の電極パッド３ｃは、半導体チップ５の第３の辺５ｃと配線基板２の第３の辺２ｃとの間において、半導体チップ５の第３の辺５ｃの外側に半導体チップ５の第３の辺５ｃに沿って配置されている。即ち、半導体チップ５の第３の辺５ｃと配線基板２の第３の辺２ｃとの間には、半導体チップ５の第３の辺５ｃに沿って複数の電極パッド３ｃが１列で配置されている。   The plurality of electrode pads 3 c are arranged between the third side 5 c of the semiconductor chip 5 and the third side 2 c of the wiring substrate 2, outside the third side 5 c of the semiconductor chip 5. It arrange | positions along the edge | side 5c. That is, a plurality of electrode pads 3 c are arranged in a row along the third side 5 c of the semiconductor chip 5 between the third side 5 c of the semiconductor chip 5 and the third side 2 c of the wiring board 2. ing.

複数の電極パッド３ｄは、半導体チップ５の第４の辺５ｄと配線基板２の第４の辺２ｄとの間において、半導体チップ５の第４の辺５ｄの外側に半導体チップ５の第４の辺５ｄに沿って配置されている。即ち、半導体チップ５の第４の辺５ｄと配線基板２の第４の辺２ｄとの間には、半導体チップ５の第４の辺５ｄに沿って複数の電極パッド３ｄが１列で配置されている。   The plurality of electrode pads 3 d are arranged between the fourth side 5 d of the semiconductor chip 5 and the fourth side 2 d of the wiring substrate 2, outside the fourth side 5 d of the semiconductor chip 5. Arranged along the side 5d. That is, a plurality of electrode pads 3 d are arranged in a row along the fourth side 5 d of the semiconductor chip 5 between the fourth side 5 d of the semiconductor chip 5 and the fourth side 2 d of the wiring substrate 2. ing.

複数の電極パッド３ｅは、半導体チップ（７，８）の第１の辺（７ａ，８ａ）と配線基板２の第１の辺２ａとの間において、半導体チップ（７，８）の第１の辺（７ａ，８ａ）の外側に半導体チップ（７，８）の第１の辺（７ａ，８ａ）に沿って配置されている。即ち、半導体チップ（７，８）の第１の辺（７ａ，８ａ）と配線基板２の第１の辺２ａとの間には、半導体チップ（７，８）の第１の辺（７ａ，８ａ）に沿って複数の電極パッド３ｅが１列で配置されている。   The plurality of electrode pads 3e are arranged between the first side (7a, 8a) of the semiconductor chip (7, 8) and the first side 2a of the wiring substrate 2 so that the first side of the semiconductor chip (7, 8). The semiconductor chip (7, 8) is disposed outside the side (7a, 8a) along the first side (7a, 8a). That is, the first side (7a, 8a) of the semiconductor chip (7, 8) is between the first side (7a, 8a) of the semiconductor chip (7, 8) and the first side 2a of the wiring board 2. A plurality of electrode pads 3e are arranged in a line along 8a).

半導体チップ５の複数の電極パッド６ａは、複数のボンディングワイヤ（１０ａ１，１０ａ２）によって配線基板２の複数の電極パッド（３ａ１，３ａ２）と夫々電気的に接続されている。半導体チップ５の複数の電極パッド６ｂは、複数のボンディングワイヤ（１０ｂ１，１０ｂ２，１０ｂ３）によって配線基板２の複数の電極パッド（３ｂ１，３ｂ２，３ｂ３）と夫々電気的に接続されている。半導体チップ５の複数の電極パッド６ｃは、複数のボンディングワイヤ１０ｃによって配線基板２の複数の電極パッド３ｃと夫々電気的に接続されている。半導体チップ５の複数の電極パッド６ｄは、複数のボンディングワイヤ１０ｄによって配線基板２の複数の電極パッド３ｄと夫々電気的に接続されている。半導体チップ（７，８）の複数の電極パッド９は、複数のボンディングワイヤ１０ｅによって配線基板２の複数の電極パッド３ｅと夫々電気的に接続されている。   The plurality of electrode pads 6a of the semiconductor chip 5 are electrically connected to the plurality of electrode pads (3a1, 3a2) of the wiring board 2 by a plurality of bonding wires (10a1, 10a2), respectively. The plurality of electrode pads 6b of the semiconductor chip 5 are electrically connected to the plurality of electrode pads (3b1, 3b2, 3b3) of the wiring board 2 by a plurality of bonding wires (10b1, 10b2, 10b3), respectively. The plurality of electrode pads 6c of the semiconductor chip 5 are electrically connected to the plurality of electrode pads 3c of the wiring board 2 by a plurality of bonding wires 10c, respectively. The plurality of electrode pads 6d of the semiconductor chip 5 are electrically connected to the plurality of electrode pads 3d of the wiring board 2 by a plurality of bonding wires 10d, respectively. The plurality of electrode pads 9 of the semiconductor chip (7, 8) are electrically connected to the plurality of electrode pads 3e of the wiring board 2 by a plurality of bonding wires 10e, respectively.

ボンディングワイヤとしては、例えば、金（Ａｕ）ワイヤが用いられている。また、ボンディングワイヤの接続方法としては、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング（ボールボンディング）法が用いられている。各ボンディングワイヤの接続は、半導体チップ５の電極パッドを一次接続、配線基板２の電極パッドを二次接続とする正ボンディング法で行われている。   For example, a gold (Au) wire is used as the bonding wire. As a bonding wire connecting method, for example, a nail head bonding (ball bonding) method in which ultrasonic vibration is used in combination with thermocompression bonding is used. The bonding wires are connected by a positive bonding method in which the electrode pads of the semiconductor chip 5 are primary connected and the electrode pads of the wiring board 2 are secondary connected.

半導体チップ５、半導体チップ（７，８）、及び複数のボンディングワイヤ等は、配線基板２の主面上に形成された樹脂封止体１１によって樹脂封止されている。樹脂封止体１１は、低応力化を図る目的として、例えば、フェノール系硬化剤、シリコーンゴム及び多数のフィラー（例えばシリカ）等が添加されたエポキシ系の熱硬化性絶縁樹脂で形成されている。   The semiconductor chip 5, the semiconductor chip (7, 8), and a plurality of bonding wires are sealed with a resin sealing body 11 formed on the main surface of the wiring board 2. For the purpose of reducing the stress, the resin sealing body 11 is formed of, for example, an epoxy thermosetting insulating resin to which a phenolic curing agent, silicone rubber, and a large number of fillers (for example, silica) are added. .

樹脂封止体１１は、厚さ方向と交差する平面形状が方形状になっており、本実施例１では例えば配線基板２と同一の平面サイズになっている。樹脂封止体１１の形成方法としては、例えば大量生産に好適なトランスファモールディング法が用いられている。   The resin sealing body 11 has a square shape that intersects with the thickness direction, and has the same planar size as the wiring board 2 in the first embodiment, for example. As a method for forming the resin sealing body 11, for example, a transfer molding method suitable for mass production is used.

ここで、ＢＧＡ型半導体装置の製造においては、スクライブラインによって区画された複数の製品形成領域（デバイス形成領域，製品取得領域）を有するマルチ配線基板（多数個取り配線基板）を使用し、各製品形成領域に搭載された半導体チップを各製品形成領域毎に樹脂封止する個別方式のトランスファモールディング法や、複数の製品形成領域を有するマルチ配線基板を使用し、各製品形成領域に搭載された半導体チップを１つの樹脂封止体で一括して樹脂封止する一括方式のトランスファモールディング法が採用されている。本実施例１では、例えば一括方式のトランスファモールディング法を採用している。   Here, in the manufacture of the BGA type semiconductor device, a multi-wiring board (multiple-wiring wiring board) having a plurality of product forming areas (device forming areas, product acquiring areas) partitioned by scribe lines is used for each product. Semiconductors mounted in each product formation area using an individual transfer molding method in which the semiconductor chip mounted in the formation area is resin-sealed for each product formation area or a multi-wiring board having multiple product formation areas A batch type transfer molding method in which chips are sealed together with a single resin sealing body is employed. In the first embodiment, for example, a batch type transfer molding method is employed.

一括方式のトランスファモールディング法の場合、樹脂封止体を形成した後、マルチ配線基板及び樹脂封止体は、例えばダイシングによって複数の小片に分割される。従って、本実施例１の樹脂封止体１１と配線基板２は、外形サイズがほぼ同一になっている。   In the case of the collective transfer molding method, after forming the resin sealing body, the multi-wiring substrate and the resin sealing body are divided into a plurality of small pieces by, for example, dicing. Therefore, the resin sealing body 11 and the wiring board 2 of Example 1 have almost the same outer size.

図７に示すように、配線基板２の主面と反対側の裏面には、複数の電極パッド２９ａが配置されている。この複数の電極パッド２９ａには、半田バンプ１２が夫々固着（電気的にかつ機械的に接続）されている。   As shown in FIG. 7, a plurality of electrode pads 29 a are arranged on the back surface opposite to the main surface of the wiring board 2. Solder bumps 12 are fixed (electrically and mechanically connected) to the plurality of electrode pads 29a.

配線基板２は、図７に示すように、表層及び内層の配線層を有する多層配線構造になっており、本実施例１では例えば４層配線構造になっている。配線基板２は、これに限定されないが、コア材２０と、コア材２０の主面に設けられた配線層２１と、配線層２１を覆うようにしてコア材２０の主面上に設けられた絶縁層２３と、絶縁層２３上に設けられた配線層２４と、配線層２４を覆うようにして絶縁層２３上に設けられた絶縁層２５と、コア材２０の主面と反対側の裏面に設けられた配線層２６と、配線層２６を覆うようにしてコア材２０の裏面上に設けられた絶縁層２８と、絶縁層２８上に設けられた配線層２９と、配線層２９を覆うようにして絶縁層２８上に設けられた絶縁層３０とを有する構成になっている。コア材２０は、例えばガラス繊維にエポキシ樹脂、若しくはポリイミド樹脂を含浸させた高弾性樹脂基板からなる。表層の絶縁層２５及び３０は、表層の配線層に形成された配線を保護する目的で設けられており、例えば絶縁性の樹脂膜（ソルダーレジスト膜）で形成されている。   As shown in FIG. 7, the wiring board 2 has a multilayer wiring structure having a surface layer and an inner wiring layer. In the first embodiment, the wiring board 2 has a four-layer wiring structure, for example. Although not limited to this, the wiring board 2 is provided on the main surface of the core material 20 so as to cover the core material 20, the wiring layer 21 provided on the main surface of the core material 20, and the wiring layer 21. Insulating layer 23, wiring layer 24 provided on insulating layer 23, insulating layer 25 provided on insulating layer 23 so as to cover wiring layer 24, and back surface opposite to the main surface of core material 20 A wiring layer 26 provided on the back surface of the core material 20 so as to cover the wiring layer 26, a wiring layer 29 provided on the insulating layer 28, and a wiring layer 29. In this manner, the insulating layer 30 is provided on the insulating layer 28. The core material 20 is made of a highly elastic resin substrate in which, for example, glass fiber is impregnated with epoxy resin or polyimide resin. The surface insulating layers 25 and 30 are provided for the purpose of protecting the wiring formed in the surface wiring layer, and are formed of, for example, an insulating resin film (solder resist film).

配線基板２は、コア材２０に絶縁層及び配線層を１層ずつ形成し、層間を接続して配線層を積み上げることによって多層化するビルドアップ工法で形成されている。また、配線基板は、配線層をセミアディティブ工法で形成している。   The wiring board 2 is formed by a build-up method in which an insulating layer and a wiring layer are formed on the core material 20 one by one, and the layers are stacked by stacking the wiring layers. Moreover, the wiring board forms the wiring layer by the semi-additive construction method.

配線基板２の主面に配置された複数の電極パッド（３ａ１，３ａ２，３ｂ１〜３ｂ３，３ｃ，３ｄ，３ｅ）は、多層配線層の上から数えて第１層目の配線層２４に形成され、配線基板２の裏面に配置された複数の電極パッド２９ａは、多層配線層の上から数えて第４層目の配線層２９に形成されている。   A plurality of electrode pads (3a1, 3a2, 3b1-3b3, 3c, 3d, 3e) arranged on the main surface of the wiring board 2 are formed on the first wiring layer 24 counted from above the multilayer wiring layer. The plurality of electrode pads 29a arranged on the back surface of the wiring board 2 are formed in the fourth wiring layer 29 counted from the top of the multilayer wiring layer.

図５及び図６に示すように、半導体チップ５の複数の電極パッド６ａは、平面形状が長方形で形成され、互いに向かい合う２つの長辺が半導体チップ５の第１の辺５ａから遠ざかる方向に沿って延在するように、換言すれば２つの短辺が半導体チップ５の第１の辺５ａと向かい合うように配置されている。配線基板２の複数の電極パッド３ａ１及び３ａ２は、平面が長方形で形成され、互いに向かい合う２つの長辺が半導体チップの第１の辺５ａから遠ざかる方向に沿って延在するように、換言すれば２つの短辺が半導体チップの第１の辺５ａと向かい合うように配置されている。   As shown in FIGS. 5 and 6, the plurality of electrode pads 6 a of the semiconductor chip 5 are formed in a rectangular planar shape, and two long sides facing each other are along a direction away from the first side 5 a of the semiconductor chip 5. In other words, the two short sides are arranged so as to face the first side 5 a of the semiconductor chip 5. In other words, the plurality of electrode pads 3a1 and 3a2 of the wiring substrate 2 are formed in a rectangular plane, and two long sides facing each other extend along a direction away from the first side 5a of the semiconductor chip. Two short sides are arranged so as to face the first side 5a of the semiconductor chip.

ここで、半導体チップ５の電極パッド６ａにおいて、ボンディングワイヤ１０ａ１を介して配線基板２の１列目の電極パッド３ａ１と電気的に接続される電極パッド６ａを参照符号ａで区別し、ボンディングワイヤ１０ａ２を介して配線基板２の２列目の電極パッド３ａ２と電気的に接続される電極パッド６ｂを参照符号ｂで区別する。また、配線基板２の電極パッドにおいて、半導体チップ５の電極パッド６ａ（ａ）に対応する１列目の電極パッド３ａ１、半導体チップ５の電極パッド６ａ（ｂ）に対応する電極パッド３ａ２を夫々参照符号ａ、ｂで区別する。   Here, in the electrode pad 6a of the semiconductor chip 5, the electrode pad 6a that is electrically connected to the electrode pad 3a1 in the first row of the wiring board 2 via the bonding wire 10a1 is distinguished by the reference symbol a, and the bonding wire 10a2 The electrode pads 6b that are electrically connected to the electrode pads 3a2 in the second row of the wiring board 2 through the wiring board 2 are distinguished by the reference symbol b. Further, in the electrode pads of the wiring substrate 2, refer to the electrode pads 3a1 in the first row corresponding to the electrode pads 6a (a) of the semiconductor chip 5 and the electrode pads 3a2 corresponding to the electrode pads 6a (b) of the semiconductor chip 5, respectively. A distinction is made between symbols a and b.

複数の電極パッド３ａ１及び３ａ２は、半導体チップ５の第１の辺５ａに沿って１つずつ交互に配置した千鳥配列になっている。電極パッド３ａ１の配列ピッチｎ１、及び電極パッド３ａ２の配列ピッチｎ２は、設計上の値が電極パッド６ａの配列ピッチｍ１の２倍になっている。電極パッド３ａ１の一辺（短辺）は、対応する電極パッド６ａの一辺（短辺）と向かい合っており、電極パッド３ａ２の一辺（短辺）は、対応する電極パッド６ａの一辺（短辺）と向かい合っている。電極パッド３ａ２は、隣り合う２つの電極パッド３ａ１の間に配置され、更に電極パッド３ａ１の配列ピッチｎ２の中間に配置されている。即ち、複数の電極パッド３ａ１及び３ａ２は、電極パッド３ａ１と電極パッド３ａ２との配列ピッチｎ１２が半導体チップ５の電極パッド６ａの配列ピッチｍ１に対して同一（設計上の値）となる配列で配置されている。本実施例１において、電極パッド６ａの配列ピッチｍ１は例えば５５［μｍ］程度であり、電極パッド３ａ１の配列ピッチｎ１及び電極パッド３ａ２の配列ピッチｎ２は例えば１１０［μｍ］程度であり、電極パッド３ａ１と電極パッド３ａ２との配列ピッチｎ１２は例えば５５［μｍ］程度である。   The plurality of electrode pads 3 a 1 and 3 a 2 are arranged in a staggered arrangement alternately one by one along the first side 5 a of the semiconductor chip 5. A design value of the arrangement pitch n1 of the electrode pads 3a1 and the arrangement pitch n2 of the electrode pads 3a2 is twice the arrangement pitch m1 of the electrode pads 6a. One side (short side) of the electrode pad 3a1 faces one side (short side) of the corresponding electrode pad 6a, and one side (short side) of the electrode pad 3a2 is one side (short side) of the corresponding electrode pad 6a. Facing each other. The electrode pad 3a2 is disposed between two adjacent electrode pads 3a1, and is further disposed in the middle of the arrangement pitch n2 of the electrode pads 3a1. That is, the plurality of electrode pads 3a1 and 3a2 are arranged in an arrangement in which the arrangement pitch n12 between the electrode pads 3a1 and the electrode pads 3a2 is the same (design value) as the arrangement pitch m1 of the electrode pads 6a of the semiconductor chip 5. Has been. In the first embodiment, the arrangement pitch m1 of the electrode pads 6a is about 55 [μm], for example, and the arrangement pitch n1 of the electrode pads 3a1 and the arrangement pitch n2 of the electrode pads 3a2 are about 110 [μm], for example. The arrangement pitch n12 of 3a1 and electrode pad 3a2 is, for example, about 55 [μm].

なお、電極パッドの配列ピッチに関しては、あくまでも設計値であり、実際の寸法は加工精度のバラツキ等により若干ずれることは言うまでもない。   It should be noted that the arrangement pitch of the electrode pads is a design value to the last, and it goes without saying that actual dimensions are slightly shifted due to variations in processing accuracy.

複数の電極パッド６ａと複数の電極パッド３ａ１とを夫々電気的に接続する複数のボンディングワイヤ１０ａ１、複数の電極パッド６ａと複数の電極パッド３ａ２とを夫々電気的に接続する複数のボンディングワイヤ１０ａ２は、ほぼ並行に延在し、更に半導体チップ５の第１の辺５ａの中間を横切ってその第１の辺５ａと直交する仮想線に対してもほぼ並行に延在している。図７及び図８に示すように、ボンディングワイヤ１０ａ２のループ高さ（ボンディング面からワイヤの最長部までの高さ）ａｈ２は、ボンディングワイヤ１０ａ１のループ高さａｈ１よりも高くなっている。   A plurality of bonding wires 10a1 electrically connecting the plurality of electrode pads 6a and the plurality of electrode pads 3a1 respectively, and a plurality of bonding wires 10a2 electrically connecting the plurality of electrode pads 6a and the plurality of electrode pads 3a2 respectively. Further, it extends substantially in parallel, and also extends substantially parallel to a virtual line that intersects the middle of the first side 5a of the semiconductor chip 5 and is orthogonal to the first side 5a. As shown in FIGS. 7 and 8, the loop height (height from the bonding surface to the longest part of the wire) ah2 of the bonding wire 10a2 is higher than the loop height ah1 of the bonding wire 10a1.

図６乃至図８に示すように、複数の電極パッド３ａ１には、電極パッド３ａ１と同一の配線層に形成された複数の配線４ａが夫々繋がっている。また、複数の電極パッド３ａ２においても、電極パッド３ａ２と同一の配線層に形成された配線４ｂが夫々繋がっている。複数の配線４ａは、各々の一端部が複数の電極パッド３ａ１と夫々一体的に繋がっており、複数の配線４ｂにおいても、各々の一端部が複数の電極パッド３ａ２と夫々一体的に繋がっている。即ち、電極パッド３ａ１は配線４ａの一部で形成され、電極パッド３ａ２は配線４ｂの一部で形成されている。   As shown in FIGS. 6 to 8, a plurality of wirings 4a formed in the same wiring layer as the electrode pad 3a1 are connected to the plurality of electrode pads 3a1. Also, in the plurality of electrode pads 3a2, wirings 4b formed in the same wiring layer as the electrode pads 3a2 are connected to each other. One end of each of the plurality of wirings 4a is integrally connected to the plurality of electrode pads 3a1, and each end of each of the plurality of wirings 4b is integrally connected to each of the plurality of electrode pads 3a2. . That is, the electrode pad 3a1 is formed by a part of the wiring 4a, and the electrode pad 3a2 is formed by a part of the wiring 4b.

複数の配線４ａは、複数の電極パッド３ａ１の夫々から半導体チップ５の第１の辺５ａに向かって延在している（延びている）。一方、複数の配線４ｂは、複数の電極パッドの夫々から半導体チップ５の第１の辺５ａとは反対側に向かって延在している（延びている）。   The plurality of wirings 4 a extend (extend) from each of the plurality of electrode pads 3 a 1 toward the first side 5 a of the semiconductor chip 5. On the other hand, the plurality of wirings 4b extend (extend) from each of the plurality of electrode pads toward the side opposite to the first side 5a of the semiconductor chip 5.

図９及び図１０に示すように、半導体チップ５の複数の電極パッド６ｂは、平面形状が長方形で形成され、互いに向かい合う２つの長辺が半導体チップ５の第２の辺５ｂから遠ざかる方向に沿って延在するように、換言すれば２つの短辺が半導体チップ５の第２の辺５ｂと向かい合うように配置されている。配線基板２の複数の電極パッド３ｂ１〜３ｂ３は、平面が長方形で形成され、互いに向かい合う２つの長辺が半導体チップの第１の辺５ａから遠ざかる方向に対して若干ずれて延在するように、換言すれば２つの短辺が半導体チップ５の第２の辺５ｂに対して若干斜めになるように配置されている。   As shown in FIGS. 9 and 10, the plurality of electrode pads 6 b of the semiconductor chip 5 are formed in a rectangular planar shape, and the two long sides facing each other are along the direction away from the second side 5 b of the semiconductor chip 5. In other words, the two short sides are arranged so as to face the second side 5 b of the semiconductor chip 5. The plurality of electrode pads 3b1 to 3b3 of the wiring board 2 are formed so that the plane is rectangular, and the two long sides facing each other extend slightly deviated from the direction away from the first side 5a of the semiconductor chip. In other words, the two short sides are arranged so as to be slightly inclined with respect to the second side 5 b of the semiconductor chip 5.

３列目の複数の電極パッド３ｂ３、２列目の複数の電極パッド３ｂ２、及び１列目の複数の電極パッド３ｂ１は、半導体チップ５の第２の辺５ｂの中心を横切って第２の辺５ｂと直交する仮想線（中心線）５ｓから数えて同じ段数（順番）に位置する電極パッドにおいて、３列目の電極パッド３ｂ３よりも２列目の電極パッド３ｂ２、２列目の電極パッド３ｂ２よりも１列目の電極パッド３ｂ１の方が仮想線５ｓから離れる状態で配置されている。   The plurality of electrode pads 3b3 in the third row, the plurality of electrode pads 3b2 in the second row, and the plurality of electrode pads 3b1 in the first row cross the center of the second side 5b of the semiconductor chip 5 and the second side The electrode pads 3b2 in the second row and the electrode pads 3b2 in the second row rather than the electrode pads 3b3 in the third row in the electrode pads positioned in the same number of steps (order) counted from the virtual line (center line) 5s orthogonal to 5b The electrode pad 3b1 in the first row is arranged in a state of being separated from the virtual line 5s.

ここで、半導体チップ５の複数の電極パッド６ｂにおいて、ボンディングワイヤ１０ｂ１を介して配線基板２の１列目の電極パッド３ｂ１と電気的に接続される電極パッド６ｂを参照符号ａで区別し、ボンディングワイヤ１０ｂ２を介して配線基板２の２列目の電極パッド３ｂ２と電気的に接続される電極パッド６ｂを参照符号ｂで区別し、ボンディングワイヤ１０ｂ３を介して配線基板２の３列目の電極パッド３ｂ３と電気的に接続される電極パッド６ｂ参照符号ｃで区別する。   Here, in the plurality of electrode pads 6b of the semiconductor chip 5, the electrode pads 6b that are electrically connected to the electrode pads 3b1 in the first row of the wiring board 2 via the bonding wires 10b1 are distinguished by the reference symbol a and bonded. The electrode pad 6b electrically connected to the electrode pad 3b2 in the second row of the wiring board 2 through the wire 10b2 is distinguished by the reference symbol b, and the electrode pad in the third row of the wiring board 2 through the bonding wire 10b3. The electrode pad 6b electrically connected to 3b3 is distinguished by reference symbol c.

また、配線基板２の電極パッドにおいて、半導体チップ５の電極パッド６ｂ（ａ）に対応する１列目の電極パッド３ｂ１、半導体チップ５の電極パッド６ｂ（ｂ）に対応する電極パッド３ｂ２、半導体チップ５の電極パッド６ｂ（ｃ）に対応する電極パッド５ｂ３を夫々参照符号ａ、ｂ、ｃで区別する。   In addition, in the electrode pads of the wiring substrate 2, the electrode pads 3b1 in the first column corresponding to the electrode pads 6b (a) of the semiconductor chip 5, the electrode pads 3b2 corresponding to the electrode pads 6b (b) of the semiconductor chip 5, and the semiconductor chip The electrode pads 5b3 corresponding to the five electrode pads 6b (c) are distinguished by reference symbols a, b and c, respectively.

複数の電極パッド６ｂは、半導体チップ５の第２の辺５ｂに沿って半導体チップ５の第２の辺５ｂの中心からその端部に向かって電極パッドｃ、電極パッドｂ及び電極パッドａがこの順番で繰り返し配置されている。即ち、半導体チップ５の電極パッド６ｂ（ｃ）と配線基板２の３列目の電極パッド３ｂ３とを接続するボンディングワイヤ１０ｂ３、半導体チップ５の電極パッド６ｂ（ｂ）と配線基板２の２列目の電極パッド３ｂ２とを接続するボンディングワイヤ１０ｂ２、及び半導体チップ５の電極パッド６ｂ（ａ）と配線基板２の１列目の電極パッド３ｂ１とを接続するボンディングワイヤ１０ｂ１は、この順番で半導体チップ５の第２の辺５ｂの中心からその端部に向かって繰り返し配置されている。   The plurality of electrode pads 6b include the electrode pad c, the electrode pad b, and the electrode pad a from the center of the second side 5b of the semiconductor chip 5 toward the end portion along the second side 5b of the semiconductor chip 5. It is arranged repeatedly in order. That is, the bonding wire 10b3 that connects the electrode pad 6b (c) of the semiconductor chip 5 and the electrode pad 3b3 of the third row of the wiring substrate 2, and the second row of the electrode pad 6b (b) of the semiconductor chip 5 and the wiring substrate 2 The bonding wire 10b2 that connects the electrode pad 3b2 of the semiconductor chip 5 and the bonding wire 10b1 that connects the electrode pad 6b (a) of the semiconductor chip 5 and the electrode pad 3b1 of the first row of the wiring substrate 2 are in this order. The second side 5b is repeatedly arranged from the center toward the end thereof.

複数のボンディングワイヤ１０ｂ１〜１０ｂ３は、仮想線５ｓに対して鋭角をなす角度で半導体チップ５の第２の辺５ｂの中心を起点にして半導体チップ５側から放射状に延在している。   The plurality of bonding wires 10b1 to 10b3 extend radially from the semiconductor chip 5 side starting from the center of the second side 5b of the semiconductor chip 5 at an acute angle with respect to the virtual line 5s.

図９並びに図１１乃至図１３に示すように、ボンディングワイヤ１０ｂ３と半導体チップ５の電極パッド６ｂ（ｃ）との接続は、ボンディングワイヤ１０ｂ１と半導体チップ５の電極パッド６ｂ（ａ）との接続よりも半導体チップ５の第２の辺５ｂから離れた位置で行われている。ボンディングワイヤ１０ｂ２と半導体チップ５の電極パッド６ｂ（ｂ）との接続は、ボンディングワイヤ１０ｂ１と半導体チップ５の電極パッド６ｂ（ａ）との接続よりも半導体チップ５の第２の辺５ｂから離れた位置で行われている。図１１乃至図１３に示すように、ボンディングワイヤ１０ｂ２のループ高さｂｈ２（図１２参照）は、ボンディングワイヤ１０ｂ１のループ高さｂｈ１（図１１参照）よりも高くなっている。ボンディングワイヤ１０ｂ３のループ高さｂｈ３（図１３参照）は、ボンディングワイヤ１０ｂ２のループ高さｂｈ２（図１２参照）よりも高くなっている。   As shown in FIGS. 9 and 11 to 13, the connection between the bonding wire 10 b 3 and the electrode pad 6 b (c) of the semiconductor chip 5 is based on the connection between the bonding wire 10 b 1 and the electrode pad 6 b (a) of the semiconductor chip 5. Is also performed at a position away from the second side 5 b of the semiconductor chip 5. The connection between the bonding wire 10b2 and the electrode pad 6b (b) of the semiconductor chip 5 is farther from the second side 5b of the semiconductor chip 5 than the connection between the bonding wire 10b1 and the electrode pad 6b (a) of the semiconductor chip 5. Is done in position. As shown in FIGS. 11 to 13, the loop height bh2 (see FIG. 12) of the bonding wire 10b2 is higher than the loop height bh1 (see FIG. 11) of the bonding wire 10b1. The loop height bh3 (see FIG. 13) of the bonding wire 10b3 is higher than the loop height bh2 (see FIG. 12) of the bonding wire 10b2.

次に、半導体装置１の製造について説明する。   Next, the manufacture of the semiconductor device 1 will be described.

まず、半導体チップ５、及び２つの半導体チップ（７，８）を準備すると共に、マルチ配線基板を準備する。   First, the semiconductor chip 5 and the two semiconductor chips (7, 8) are prepared, and a multi-wiring board is prepared.

次に、マルチ配線基板の各製品形成領域のチップ搭載部に半導体チップ５、半導体チップ７及び８を搭載する。半導体チップの搭載は、各製品形成領域におけるパッド列が半導体チップの辺に沿う状態で行う。   Next, the semiconductor chip 5 and the semiconductor chips 7 and 8 are mounted on the chip mounting portion in each product formation region of the multi-wiring substrate. The mounting of the semiconductor chip is performed in a state where the pad row in each product formation region is along the side of the semiconductor chip.

次に、各製品形成領域において、半導体チップの複数の電極パッドと半導体チップの周囲に配置された複数の電極パッドとを複数のボンディングワイヤで夫々電気的に接続する。この工程により、マルチ配線基板の各製品形成領域に、半導体チップ５，半導体チップ７及び８が実装される。   Next, in each product formation region, the plurality of electrode pads of the semiconductor chip and the plurality of electrode pads arranged around the semiconductor chip are electrically connected by a plurality of bonding wires, respectively. By this process, the semiconductor chips 5 and the semiconductor chips 7 and 8 are mounted in each product formation region of the multi-wiring board.

ここで、実装とは、基板に半導体チップが接着固定され、基板の接続用パッドと半導体チップの接続用パッドとが電気的に接続された状態を言う。本実施例１では、半導体チップ２の接着固定は、接着材によって行われており、マルチ配線基板の電極パッドと半導体チップの電極パッドとの電気的な接続は、ボンディングワイヤによって行われている。   Here, the mounting means a state in which the semiconductor chip is bonded and fixed to the substrate, and the connection pad of the substrate and the connection pad of the semiconductor chip are electrically connected. In the first embodiment, the semiconductor chip 2 is bonded and fixed by an adhesive, and the electrical connection between the electrode pad of the multi-wiring substrate and the electrode pad of the semiconductor chip is performed by a bonding wire.

次に、一括方式のトランスファモールディング法を使用して、マルチ配線基板の各製品形成領域３７に実装された半導体チップを一括して樹脂封止する樹脂封止体を形成する。   Next, using a batch transfer molding method, a resin sealing body is formed which collectively seals the semiconductor chips mounted on each product formation region 37 of the multi-wiring board.

次に、マルチ配線基板の主面と反対側の裏面に、各製品形成領域に対応して複数の半田バンプ１２を形成する。半田バンプ１２は、これに限定されないが、例えば、マルチ配線基板の裏面の電極パッド上にフラックス材を塗布し、その後、電極パッド３２上に半田ボールを供給し、その後、半田ボールを溶融して電極パッドとの接合を行うことによって形成される。   Next, a plurality of solder bumps 12 are formed on the back surface opposite to the main surface of the multi-wiring board, corresponding to each product formation region. The solder bump 12 is not limited to this, but, for example, a flux material is applied on the electrode pad on the back surface of the multi-wiring board, and then a solder ball is supplied onto the electrode pad 32, and then the solder ball is melted. It is formed by bonding with an electrode pad.

次に、半田バンプ形成工程において使用したフラックスを洗浄にて除去し、その後、マルチ配線基板の各製品形成領域３７に対応して樹脂封止体の上面に、例えば品名、社名、品種、製造ロット番号等の識別マークを、インクジェットマーキング法、ダイレクト印刷法、レーザマーキング法等を用いて形成する。   Next, the flux used in the solder bump forming process is removed by cleaning, and then, for example, a product name, a company name, a product type, and a production lot are formed on the upper surface of the resin sealing body corresponding to each product formation region 37 of the multi-wiring board. Identification marks such as numbers are formed using an inkjet marking method, a direct printing method, a laser marking method, or the like.

次に、マルチ配線基板及び樹脂封止体を各製品形成領域に対応して複数の小片に分割する。この分割は、例えば、ダイシングシートに樹脂封止体を貼り付けた状態で、マルチ配線基板のスクライブラインに沿ってマルチ配線基板及び樹脂封止体をダイシングブレードでダイシングすることによって行われる。この工程により、図１に示す半導体装置１がほぼ完成する。   Next, the multi-wiring substrate and the resin sealing body are divided into a plurality of small pieces corresponding to each product formation region. This division is performed, for example, by dicing the multi-wiring board and the resin sealing body with a dicing blade along the scribe line of the multi-wiring board in a state where the resin sealing body is attached to the dicing sheet. Through this step, the semiconductor device 1 shown in FIG. 1 is almost completed.

次に、半導体チップ５の主面にその主面の第１の辺５ｂに沿って配置された複数の電極パッド６ｂと、この複数の電極パッド６ｂに対応して配線基板２の主面に３列で配置された複数の電極パッド（３ｂ１，３ｂ２，３ｂ３）とを複数のボンディングワイヤ（１０ｂ１，１０ｂ２，１０ｂ３）で夫々電気的に接続するワイヤボンディングについて説明する。   Next, a plurality of electrode pads 6b arranged on the main surface of the semiconductor chip 5 along the first side 5b of the main surface, and 3 on the main surface of the wiring board 2 corresponding to the plurality of electrode pads 6b. Wire bonding for electrically connecting a plurality of electrode pads (3b1, 3b2, 3b3) arranged in a row with a plurality of bonding wires (10b1, 10b2, 10b3) will be described.

まず、図１４に示すように、配線基板２に配置された１列目の複数の電極パッド３ｂ１（ａ）と、半導体チップ５の複数の電極パッド６ｂのうち、配線基板２の１列目の複数の電極パッド３ｂ１と対応する複数の電極パッド６ｂ（ａ）とを複数のボンディングワイヤ１０ｂ１で夫々電気的に接続する。この工程において、ボンディングワイヤ１０ｂ１と電極パッド６ｂ（ａ）との接続は、電極パッドａの２つの短辺のうち、半導体チップ５の第２の辺５ｂに近い方の短辺に偏った位置（接続点ｋ１）で行う。また、ボンディングワイヤ１０ｂ１は、仮想線５ｓに対して鋭角を成す角度で延在する。   First, as shown in FIG. 14, among the plurality of electrode pads 3b1 (a) in the first row arranged on the wiring board 2 and the plurality of electrode pads 6b in the semiconductor chip 5, the first row in the wiring board 2 is provided. The plurality of electrode pads 3b1 and the corresponding plurality of electrode pads 6b (a) are electrically connected by a plurality of bonding wires 10b1, respectively. In this step, the connection between the bonding wire 10b1 and the electrode pad 6b (a) is biased to the short side of the two short sides of the electrode pad a closer to the second side 5b of the semiconductor chip 5 ( At the connection point k1). The bonding wire 10b1 extends at an angle that forms an acute angle with the virtual line 5s.

次に、図１５に示すように、配線基板２に配置された２列目の複数の電極パッド３ｂ２（ｂ）と、半導体チップ５の複数の電極パッド６ｂのうち、配線基板２の２列目の複数の電極パッド３ｂ２と対応する複数の電極パッド６ｂ（ｂ）とを複数のボンディングワイヤ１０ｂ２で夫々電気的に接続する。ボンディングワイヤ１０ｂ２と電極パッド６ｂ（ｂ）との接続は、電極パッド６ｂ（ｂ）の２つの短辺のうち、半導体チップ５の第２の辺５ｂから離れた方の短辺に偏った位置（接続点ｋ２）で行う。換言すると、ボンディングワイヤ１０ｂ１が接続された電極パッド６ｂ（ａ）の短辺側とは異なる短辺側に偏った位置で、ボンディングワイヤ１０ｂ２の接続を行う。また、ボンディングワイヤ１０ｂ２は、仮想線５ｓに対して鋭角を成す角度で延在する。この工程において、電極パッド６ｂ（ｂ）におけるボンディングワイヤ１０ｂ２の接続位置(接続点ｋ２)と隣り合う電極パッド６ｂ（ａ）におけるボンディングワイヤ１０ｂ１の接続位置（接続点ｋ１）は、それぞれ異なる短辺に偏った位置で接続をしている。換言すると、それぞれの接続点が千鳥配置の関係でそれぞれのボンディングワイヤと接続されているため、電極パッド６ｂ（ｂ）にキャピラリが降りた時、ボンディングワイヤ１０ｂ１とキャピラリとの距離が電極パッド６ｂの配列ピッチよりも大きくなる。このため、ボンディングワイヤ１０ｂ１とキャピラリとの干渉を抑制することができる。   Next, as shown in FIG. 15, among the plurality of electrode pads 3 b 2 (b) arranged in the second row and the plurality of electrode pads 6 b of the semiconductor chip 5, the second row of the wiring substrate 2 is arranged. The plurality of electrode pads 3b2 and the corresponding plurality of electrode pads 6b (b) are electrically connected by a plurality of bonding wires 10b2. The connection between the bonding wire 10b2 and the electrode pad 6b (b) is biased to the short side of the two short sides of the electrode pad 6b (b) that is farther from the second side 5b of the semiconductor chip 5 ( This is done at connection point k2). In other words, the bonding wire 10b2 is connected at a position that is biased toward the short side different from the short side of the electrode pad 6b (a) to which the bonding wire 10b1 is connected. The bonding wire 10b2 extends at an angle that forms an acute angle with the virtual line 5s. In this step, the connection position (connection point k2) of the bonding wire 10b2 in the electrode pad 6b (b) and the connection position (connection point k1) of the bonding wire 10b1 in the adjacent electrode pad 6b (a) are on different short sides. Connections are made at a biased position. In other words, since each connection point is connected to each bonding wire in a staggered relationship, when the capillary descends to the electrode pad 6b (b), the distance between the bonding wire 10b1 and the capillary is equal to that of the electrode pad 6b. It becomes larger than the arrangement pitch. For this reason, interference between the bonding wire 10b1 and the capillary can be suppressed.

次に、図１６に示すように、配線基板２に配置された３列目の複数の電極パッド３ｂ３（ｃ）と、半導体チップ５の複数の電極パッド６ｂのうち、配線基板２の３列目の複数の電極パッド３ｂ３と対応する複数の電極パッド６ｂ（ｃ）とを複数のボンディングワイヤ１０ｂ３で夫々電気的に接続する。ボンディングワイヤ１０ｂ３と電極パッド６ｂ（ｃ）との接続は、電極パッドｃの２つの短辺のうち、半導体チップ５の第２の辺５ｂから離れた方の短辺に偏った位置（接続点ｋ２）で行う。換言すると、電極パッド６ｂ（ｂ）においてボンディングワイヤ１０ｂ２が接続される短辺と同じ側の短辺に偏った位置で行う。また、ボンディングワイヤ１０ｂ２は、仮想線５ｓに対して鋭角を成す角度で延在する。   Next, among the plurality of electrode pads 3b3 (c) in the third row arranged on the wiring board 2 and the plurality of electrode pads 6b in the semiconductor chip 5, as shown in FIG. The plurality of electrode pads 3b3 and the corresponding plurality of electrode pads 6b (c) are electrically connected by a plurality of bonding wires 10b3, respectively. The connection between the bonding wire 10b3 and the electrode pad 6b (c) is a position (connection point k2) that is biased to the short side of the two short sides of the electrode pad c that is farther from the second side 5b of the semiconductor chip 5. ). In other words, it is performed at a position biased to the short side on the same side as the short side to which the bonding wire 10b2 is connected in the electrode pad 6b (b). The bonding wire 10b2 extends at an angle that forms an acute angle with the virtual line 5s.

この工程において、電極パッド６ｂ（ｃ）と隣り合う電極パッド６ｂ（ｂ）に接続されたボンディングワイヤ１０ｂ２は、仮想線５ｓに対して鋭角をなす角度、即ち電極パッド６ｂ（ｃ）に対して外側を向いているため、電極パッド６ｂ（ｃ）にキャピラリが降りた時、ボンディングワイヤ１０ｂ２とキャピラリとの距離が電極パッド６ｂの配列ピッチよりも大きくなる。このため、ボンディングワイヤ１０ｂ１とキャピラリとの干渉を抑制することができる。一方、電極パッド６ｂ（ｃ）と隣り合う電極パッド６ｂ（ａ）に接続されたボンディングワイヤ１０ｂ１は、仮想線５ｓに対して鋭角をなす角度、即ち電極パッド６ｂ（ｃ）に対して内側を向いているが、ボンディングワイヤ１０ｂ３と電極パッド６ｂ（ｃ）との接続は、ボンディングワイヤ１０ｂ１と電極パッド３ｂ１との接続位置よりも半導体チップ５の第２の辺５ｂから離れた位置で行われるため、電極パッド６ｂ（ｃ）にキャピラリが降りた時、ボンディングワイヤ１０ｂ１とキャピラリとの距離が電極パッド６ｂの配列ピッチよりも大きくなる。このため、ボンディングワイヤ１０ｂ１とキャピラリとの干渉を抑制することができる。   In this step, the bonding wire 10b2 connected to the electrode pad 6b (b) adjacent to the electrode pad 6b (c) forms an acute angle with the virtual line 5s, that is, outside the electrode pad 6b (c). Therefore, when the capillary descends to the electrode pad 6b (c), the distance between the bonding wire 10b2 and the capillary becomes larger than the arrangement pitch of the electrode pads 6b. For this reason, interference between the bonding wire 10b1 and the capillary can be suppressed. On the other hand, the bonding wire 10b1 connected to the electrode pad 6b (a) adjacent to the electrode pad 6b (c) has an acute angle with respect to the virtual line 5s, that is, faces inward with respect to the electrode pad 6b (c). However, the connection between the bonding wire 10b3 and the electrode pad 6b (c) is performed at a position farther from the second side 5b of the semiconductor chip 5 than the connection position between the bonding wire 10b1 and the electrode pad 3b1. When the capillary descends to the electrode pad 6b (c), the distance between the bonding wire 10b1 and the capillary becomes larger than the arrangement pitch of the electrode pads 6b. For this reason, interference between the bonding wire 10b1 and the capillary can be suppressed.

ここで、本実施例１のように配線基板２の電極パッドが多列の場合、１列目の電極パッド３ｂ１に接続されるボンディングワイヤ１０ｂ１と、２列目の電極パッド３ｂ２に接続されるボンディングワイヤ１０ｂ２と、３列目の電極パッド３ｂ３に接続されるボンディングワイヤ１０ｂ３とでは、夫々のワイヤ長が異なる。このようにワイヤ長が異なるワイヤボンディングでは、ワイヤだれ（ワイヤループが中間でたれ下がる状態）や、ワイヤのよれ（２点間を接続したワイヤが上方から見て直線ではなく湾曲した状態）によって、半導体チップにボンディングワイヤが接触、又は隣接するワイヤ同士が接触するといったワイヤタッチ不良を抑制するため、ボンディングワイヤのループ高さを変える必要がある。本実施例１では、２列目の電極パッド３ｂ２に接続されるボンディングワイヤ１０ｂ２のループ高さｂｈ２（図１２参照）は、１列目の電極パッド３ｂ１に接続されるボンディングワイヤ１０ｂ１のループ高さｂｈ１（図１１参照）よりも高く、３列目の電極パッド３ｂ３に接続されるボンディングワイヤ１０ｂ３のループ高さｂｈ３（図１３参照）は、２列目の電極パッド３ｂ２に接続されるボンディングワイヤ１０ｂ２のループ高さｂｈ２（図１２参照）よりも高くなっている。   Here, when the electrode pads of the wiring board 2 are in multiple rows as in the first embodiment, the bonding wires 10b1 connected to the first electrode pads 3b1 and the bondings connected to the second electrode pads 3b2 are used. The wire 10b2 and the bonding wire 10b3 connected to the third-row electrode pad 3b3 have different wire lengths. In wire bonding with different wire lengths as described above, depending on the wire droop (the state in which the wire loop hangs down in the middle) and the wire twist (the state in which the wire connecting the two points is curved instead of a straight line when viewed from above), It is necessary to change the loop height of the bonding wire in order to suppress a wire touch failure such that the bonding wire contacts the semiconductor chip or adjacent wires contact each other. In the first embodiment, the loop height bh2 (see FIG. 12) of the bonding wire 10b2 connected to the electrode pad 3b2 in the second row is the loop height of the bonding wire 10b1 connected to the electrode pad 3b1 in the first row. The loop height bh3 (see FIG. 13) of the bonding wire 10b3 connected to the third-row electrode pad 3b3 is higher than bh1 (see FIG. 11) and the bonding wire 10b2 connected to the second-row electrode pad 3b2 Is higher than the loop height bh2 (see FIG. 12).

ボンディングワイヤのループ高さを考慮しなければ、半導体チップ５の第２の辺５ｂの両端からその中央に向かって順次ワイヤボンディングを行うことによって、ボンディングワイヤとキャピラリとの干渉を抑制することができるが、ボンディングワイヤのループ高さを考慮した場合は、半導体チップ５の第２の辺５ｂの端からその中央に向かってワイヤボンディングを行うと、ループ高さが高いボンディングワイヤ１０ｂ３で接続した後に、ループ高さが低いボンディングワイヤ１０ｂ１で接続することになるため、ループ高さが高いボンディングワイヤ１０ｂ３にその後のワイヤボンディングを行うキャピラリが干渉してしまう。   If the loop height of the bonding wire is not taken into consideration, interference between the bonding wire and the capillary can be suppressed by sequentially performing wire bonding from both ends of the second side 5b of the semiconductor chip 5 toward the center thereof. However, when the loop height of the bonding wire is taken into account, when wire bonding is performed from the end of the second side 5b of the semiconductor chip 5 toward the center thereof, after the connection with the bonding wire 10b3 having a high loop height, Since the connection is made with the bonding wire 10b1 having a low loop height, the capillary for performing subsequent wire bonding interferes with the bonding wire 10b3 having a high loop height.

従って、本実施例１のように、１列目の電極パッド３ｂ１のワイヤ接続後に２列目の電極パッド３ｂ２のワイヤ接続、２列目の電極パッド３ｂ２のワイヤ接続後に３列目の電極パッド３ｂ３のワイヤ接続という順番で行う、換言すれば、同じワイヤ長から成るワイヤ接続を全て完了した後、異なるワイヤ長からなるワイヤ接続を行うことが有効である。   Accordingly, as in the first embodiment, after the wire connection of the electrode pad 3b1 in the first row, the wire connection of the electrode pad 3b2 in the second row, and the electrode pad 3b3 in the third row after the wire connection of the electrode pad 3b2 in the second row. It is effective to perform wire connection consisting of different wire lengths after completing all the wire connections consisting of the same wire length.

本実施例１において、図５乃至図８に示すように、半導体チップ５の第１の辺５ａに沿って配線基板２の主面に２列で配置された複数の電極パッド（３ａ１，３ａ２）のうち、１列目に配置された複数の電極パッド３ａ１に繋がる複数の配線４ａは、各々の電極パッド３ａ１から半導体チップ５の第１の辺５ａに向かって延在し、２列目に配置された複数の電極パッド３ａ２に繋がる複数の配線４ｂは、各々の電極パッド３ａ２から半導体チップ５の第１の辺５ａと反対側に向かって延在している。このような構成にすることにより、電極パッド３ａ２の配列ピッチを小さくすることができるので、２列目のパッド列の長さを短くすることができる。また、２列目の電極パッド３ａ２の配列ピッチの縮小に伴い、１列目の電極パッド３ｂ１の配列ピッチも小さくすることができるので、１列目のパッド配列の長さを短くすることができる。これにより、配線基板２の平面サイズを縮小できるため、半導体装置１の小型化を図ることができる。   In the first embodiment, as shown in FIGS. 5 to 8, a plurality of electrode pads (3 a 1, 3 a 2) arranged in two rows on the main surface of the wiring board 2 along the first side 5 a of the semiconductor chip 5. Among them, the plurality of wirings 4a connected to the plurality of electrode pads 3a1 arranged in the first column extend from each electrode pad 3a1 toward the first side 5a of the semiconductor chip 5, and are arranged in the second column. A plurality of wirings 4 b connected to the plurality of electrode pads 3 a 2 extend from the respective electrode pads 3 a 2 toward the side opposite to the first side 5 a of the semiconductor chip 5. With such a configuration, since the arrangement pitch of the electrode pads 3a2 can be reduced, the length of the second pad row can be shortened. Further, as the arrangement pitch of the electrode pads 3a2 in the second row is reduced, the arrangement pitch of the electrode pads 3b1 in the first row can be reduced, so that the length of the pad arrangement in the first row can be shortened. . Thereby, since the planar size of the wiring board 2 can be reduced, the semiconductor device 1 can be reduced in size.

また、１列目の電極パッド３ａ１及び２列目の電極パッド３ａ２を半導体チップ５の第１の辺５ａに近づけることができるため、ボンディングワイヤの長さを短くすることができる。これにより、トランスファモールディング法に基づいて樹脂封止体を形成する時、ボンディングワイヤの形状が樹脂の流れによって変形するワイヤ流れにより、隣り合うボンディングワイヤ同士が短絡するといった不具合の発生を抑制することができるため、半導体装置１の製造歩留まり向上を図ることができる。   Further, since the electrode pad 3a1 in the first row and the electrode pad 3a2 in the second row can be brought close to the first side 5a of the semiconductor chip 5, the length of the bonding wire can be shortened. Thereby, when forming the resin sealing body based on the transfer molding method, it is possible to suppress the occurrence of a problem that adjacent bonding wires are short-circuited by the wire flow in which the shape of the bonding wire is deformed by the flow of the resin. Therefore, the manufacturing yield of the semiconductor device 1 can be improved.

また、配線基板２の電極パッドの配列ピッチは半導体チップ５の電極パッドの配列ピッチよりも広くなっているため、ボンディングワイヤは、半導体チップの一辺の中心を横切ってその一辺と直行する仮想線に対して鋭角をなす角度で半導体チップ側から放射状に延在するが、配線基板のパッド列の長さが長くなると、ボンディングワイヤの前記仮想線に対する角度が小さくなるため、半導体チップの電極パッドにおいて、隣り合う２つの電極パッドのうちの一方の電極パッドにボンディングワイヤを接続し、その後、他方の電極パッドにボンディングワイヤを接続する時、一方の電極パッドに接続されたボンディングワイヤにキャピラリが干渉するといった不具合の発生を抑制することができる。この結果、半導体装置の製造歩留まり向上を図ることができる。   Further, since the arrangement pitch of the electrode pads on the wiring board 2 is wider than the arrangement pitch of the electrode pads on the semiconductor chip 5, the bonding wire crosses the center of one side of the semiconductor chip and forms a virtual line perpendicular to the one side. Although it extends radially from the semiconductor chip side at an acute angle with respect to the electrode pad of the semiconductor chip, the angle of the bonding wire with respect to the virtual line decreases as the length of the pad row of the wiring board increases. When a bonding wire is connected to one of the two adjacent electrode pads and then the bonding wire is connected to the other electrode pad, the capillary interferes with the bonding wire connected to the one electrode pad. The occurrence of defects can be suppressed. As a result, the manufacturing yield of the semiconductor device can be improved.

本実施例１において、図５及び図６に示すように、半導体チップ５の第１の辺５ａに沿って配線基板２の主面に２列で配置された複数の電極パッド（３ａ１，３ａ２）のうち、１列目の複数の電極パッド３ａ１は、対応する複数の電極パッド６ａと向かい合って配置され、２列目の複数の電極パッド３ａ２は、対応する複数の電極パッド６ａと向かい合って配置されている。このような構成にすることにより、更に１列目のパッド列の長さ及び２列目のパッド列の長さを短くすることができるので、半導体装置１の小型化、半導体装置１の歩留まり向上を更に図ることができる。   In the first embodiment, as shown in FIGS. 5 and 6, a plurality of electrode pads (3 a 1, 3 a 2) arranged in two rows on the main surface of the wiring board 2 along the first side 5 a of the semiconductor chip 5. Among them, the plurality of electrode pads 3a1 in the first row are arranged to face the corresponding electrode pads 6a, and the plurality of electrode pads 3a2 in the second row are arranged to face the corresponding electrode pads 6a. ing. With such a configuration, the length of the first row of pads and the length of the second row of pads can be further shortened, so that the semiconductor device 1 can be downsized and the yield of the semiconductor device 1 can be improved. Can be further achieved.

本実施例１の配線基板２は、セミアディティブ工法で形成されている。セミアディティブ工法は、サブトラ工法と比較して加工精度が高く、完成した導体パターン（配線、電極パッド）の上幅と下幅との差がほとんどないため、高密度に配線や電極パッドを形成することできる。従って、更に１列目のパッド列の長さ及び２列目のパッド列の長さを短くすることができるので、半導体装置１の小型化、半導体装置１の歩留まり向上を更に図ることができる。   The wiring board 2 of Example 1 is formed by a semi-additive construction method. The semi-additive method has higher processing accuracy than the sub-traffic method and there is almost no difference between the upper and lower widths of the completed conductor pattern (wiring and electrode pads), so the wiring and electrode pads are formed with high density. I can. Therefore, since the length of the first row of pads and the length of the second row of pads can be further reduced, it is possible to further reduce the size of the semiconductor device 1 and improve the yield of the semiconductor device 1.

配線基板２の電極パッドには、ボンディングワイヤとのボンダビリティ向上を図るため、メッキ層が形成される。このメッキ層は、低コストでのメッキが可能な電界メッキ法が使用されるが、この場合、電極パッドに給電用配線を接続する必要がある。本実施例１の配線基板２は、表層及び内層の配線層を有する多層配線構造になっている。従って、配線基板２の内層の配線層を使って給電用配線を引き回すことができるため、２列目の電極パッド３ａ２間に給電用配線を通すことなく、１列目の電極パッド３ａ１に給電用配線を接続することができる。   A plating layer is formed on the electrode pad of the wiring board 2 in order to improve bondability with the bonding wire. For this plating layer, an electroplating method capable of plating at low cost is used. In this case, it is necessary to connect a power supply wiring to the electrode pad. The wiring board 2 of the first embodiment has a multilayer wiring structure having a surface layer and an inner layer. Accordingly, the power supply wiring can be routed using the inner wiring layer of the wiring board 2, and therefore, the power supply wiring is not supplied to the first electrode pad 3a1 without passing the power supply wiring between the second electrode pads 3a2. Wiring can be connected.

本実施例１の配線基板２は、ビルドアップ工法で形成されている。ビルドアップ工法は、コア材に絶縁層及び配線層を１層ずつ形成し、層間を接続して配線層を積み上げることによって多層化するため、配線の引き回し自由度が高い。従って、ビルドアップ工法で形成された配線基板を使用することにより、狭ピッチの電極パッドを配置することができる。   The wiring board 2 of the first embodiment is formed by a buildup method. In the build-up method, an insulating layer and a wiring layer are formed one by one on the core material, and the layers are stacked by connecting the layers, so that the degree of freedom of wiring is high. Therefore, by using the wiring board formed by the build-up method, it is possible to arrange the electrode pads with a narrow pitch.

半導体チップ５の主面にその主面の第１の辺５ｂに沿って配置された複数の電極パッド６ｂと、この複数の電極パッド６ｂに対応して配線基板２の主面に３列で配置された複数の電極パッド（３ｂ１，３ｂ２，３ｂ３）とを複数のボンディングワイヤ（１０ｂ１，１０ｂ２，１０ｂ３）で夫々電気的に接続するワイヤボンディングにおいて、２列目の複数の電極パッド３ｂ２は、半導体チップ５の第２の辺５ｂの中心を横切って第２の辺５ｂと直交する仮想線（中心線）５ｓから数えて３列目の電極パッド３ｂ３と同じ順位（順番）に位置する電極パッド３ｂ２が仮想線５ｓから離れる状態で配置する。１列目の複数の電極パッド３ｂ１は、仮想線５ｓから数えて２列目の電極パッド３ｂ２と同じ順位（順番）に位置する電極パッド３ｂ１が仮想線５ｓから離れる状態で配置する。
１列目の複数の電極パッド３ｂ１とこれに対応する複数の電極パッド６ｂ（ａ）とを複数のボンディングワイヤ１０ｂ１で夫々電気的に接続する工程、２列目の複数の電極パッド３ｂ２とこれに対応する複数の電極パッド６ｂ（ｂ）とを複数のボンディングワイヤ１０ｂ２で夫々電気的に接続する工程、及び３列目の複数の電極パッド３ｂ３とこれに対応する複数の電極パッド６ｂ（ｃ）とを複数のボンディングワイヤ１０ｂ３で夫々電気的に接続する工程を、この順番で行う。
ボンディングワイヤ１０ｂ３と３列目の電極パッド３ｂ３との接続、並びにボンディングワイヤ１０ｂ２と２列目の電極パッド３ｂ２との接続は、ボンディグワイヤ１０ｂ１と１列目の電極パッド３ｂ１との接続よりも半導体チップ５の第２の辺５ｂから離れた位置で行う。 A plurality of electrode pads 6b arranged on the main surface of the semiconductor chip 5 along the first side 5b of the main surface, and arranged in three rows on the main surface of the wiring board 2 corresponding to the plurality of electrode pads 6b. In the wire bonding in which the plurality of electrode pads (3b1, 3b2, 3b3) are electrically connected to each other by a plurality of bonding wires (10b1, 10b2, 10b3), the plurality of electrode pads 3b2 in the second row are semiconductor chips. The electrode pads 3b2 positioned in the same order (order) as the electrode pads 3b3 in the third column are counted from a virtual line (center line) 5s orthogonal to the second side 5b across the center of the second side 5b. It arrange | positions in the state away from the virtual line 5s. The plurality of electrode pads 3b1 in the first row are arranged in a state in which the electrode pads 3b1 positioned in the same order (order) as the electrode pads 3b2 in the second row as counted from the virtual line 5s are separated from the virtual line 5s.
A step of electrically connecting a plurality of electrode pads 3b1 in the first row and a plurality of electrode pads 6b (a) corresponding thereto with a plurality of bonding wires 10b1, and a plurality of electrode pads 3b2 in the second row and A step of electrically connecting a plurality of corresponding electrode pads 6b (b) with a plurality of bonding wires 10b2, and a plurality of electrode pads 3b3 in the third row and a plurality of electrode pads 6b (c) corresponding thereto Are sequentially connected in this order by a plurality of bonding wires 10b3.
The connection between the bonding wire 10b3 and the third row electrode pad 3b3 and the connection between the bonding wire 10b2 and the second row electrode pad 3b2 are more semiconductor than the connection between the bonding wire 10b1 and the first row electrode pad 3b1. This is performed at a position away from the second side 5b of the chip 5.

このようにしてワイヤボンディングを行うことにより、キャピラリが電極パッドに降りた時、隣接するボンディングワイヤとキャピラリとの距離が電極パッド６ｂの配列ピッチよりも大きくなるため、隣接するボンディングワイヤとキャピラリとの干渉を抑制することができる。これにより、半導体装置１の製造歩留まり向上を図ることができる。   By performing the wire bonding in this way, when the capillary descends to the electrode pad, the distance between the adjacent bonding wire and the capillary becomes larger than the arrangement pitch of the electrode pad 6b. Interference can be suppressed. Thereby, the manufacturing yield of the semiconductor device 1 can be improved.

なお、実施例１では、ボンディングワイヤ１０ｂ２と電極パッド６ｂ（ｂ）との接続を、ボンディングワイヤ１０ｂ１と電極パッド６ｂ（ａ）との接続よりも半導体チップ５の第２の辺５ｂから離れた位置で行う例について説明したが、ボンディングワイヤ１０ｂ２と電極パッド６ｂ（ｂ）との接続は、ボンディングワイヤ１０ｂ１と電極パッド６ｂ（ａ）との接続と同じように半導体チップ５の第２の辺５ｂに近い位置、即ち、ボンディングワイヤ１０ｂ３と電極パッド６ｂ（ｃ）よりも半導体チップ５の第２の辺５ｂと近い位置に配置しても、同様の効果が得られる。   In Example 1, the connection between the bonding wire 10b2 and the electrode pad 6b (b) is located farther from the second side 5b of the semiconductor chip 5 than the connection between the bonding wire 10b1 and the electrode pad 6b (a). However, the connection between the bonding wire 10b2 and the electrode pad 6b (b) is connected to the second side 5b of the semiconductor chip 5 in the same manner as the connection between the bonding wire 10b1 and the electrode pad 6b (a). The same effect can be obtained even if it is arranged at a position closer to the second side 5b of the semiconductor chip 5 than the bonding wire 10b3 and the electrode pad 6b (c).

各ボンディングワイヤ（１０ｂ１，１０ｂ２，１０ｂ３）の接続は、半導体チップ５の第２の辺５ｂの一端側から他端側に向かって連続的に行っても良いし、半導体チップ５の第２の辺５ｂの一端側及び他端側からその第２の辺５ｂの中心に向かって連続的に行っても良いし、半導体チップ５の第２の辺５ｂの中心からその第２の辺５ｂの一端側及び他端側に向かって連続的に行っても良い。   The bonding wires (10b1, 10b2, 10b3) may be connected continuously from one end side to the other end side of the second side 5b of the semiconductor chip 5, or the second side of the semiconductor chip 5 may be connected. It may be performed continuously from one end side and the other end side of 5b toward the center of the second side 5b, or from the center of the second side 5b of the semiconductor chip 5 to one end side of the second side 5b. And you may carry out continuously toward the other end side.

ただし、半導体チップ５の電極パッド６ｂ（ａ）と配線基板２の１列目の電極パッド３ｂ１とをボンディングワイヤ１０ｂ１で接続する第１のワイヤボンディング工程の後、半導体チップ５の電極パッド６ｂ（ｂ）と配線基板２の２列目の電極パッド３ｂ２とをボンディングワイヤ１０ｂ２で接続する第２のワイヤボンディング工程を実施し、第２のワイヤボンディング工程の後、半導体チップ５の電極パッド６ｂ（ｃ）と配線基板２の３列目の電極パッド３ｂ３とをボンディングワイヤ１０ｂ３で接続する第３のワイヤボンディング工程を実施する。   However, after the first wire bonding step in which the electrode pads 6b (a) of the semiconductor chip 5 and the electrode pads 3b1 in the first row of the wiring substrate 2 are connected by the bonding wires 10b1, the electrode pads 6b (b) of the semiconductor chip 5 are connected. ) And the electrode pads 3b2 in the second row of the wiring board 2 are connected by bonding wires 10b2, and after the second wire bonding process, electrode pads 6b (c) of the semiconductor chip 5 are implemented. A third wire bonding step for connecting the electrode pads 3b3 in the third row of the wiring board 2 with the bonding wires 10b3 is performed.

第１のワイヤボンディング工程の後、第３のワイヤボンディング工程を実施すると、第３のワイヤボンディング工程で張られたボンディングワイヤ１０ｂ３に第２のワイヤボンディング工程におけるキャピラリが干渉し易くなるため、第１、第２、第３の順番でワイヤボンディング工程を実施することが重要である。   When the third wire bonding step is performed after the first wire bonding step, the capillary in the second wire bonding step easily interferes with the bonding wire 10b3 stretched in the third wire bonding step. It is important to perform the wire bonding process in the second and third order.

［実施例２］
図１７は、本発明の実施例２である半導体装置の概略構成を示す模式的平面図であり、図１８は、図１７のボンディングワイヤを省略して示す模式的平面図である。 [Example 2]
FIG. 17 is a schematic plan view showing a schematic configuration of a semiconductor device that is Embodiment 2 of the present invention, and FIG. 18 is a schematic plan view in which the bonding wires of FIG. 17 are omitted.

本実施例２は、パッド配列ピッチを小さくする本発明を３列パッド配置に適用した例である。   The second embodiment is an example in which the present invention for reducing the pad arrangement pitch is applied to a three-row pad arrangement.

図１７及び１８に示すように、電極パッド３ａ１（ａ）は対応する電極パッド６ａ（ａ）と向かい合っており、電極パッド３ａ２（ｂ）は対応する電極パッド６ａ（ｂ）と向かい合っており、電極パッド３ａ３（ｃ）は対応する電極パッド６ａ（ｃ）と向かい合っている。   17 and 18, the electrode pad 3a1 (a) faces the corresponding electrode pad 6a (a), and the electrode pad 3a2 (b) faces the corresponding electrode pad 6a (b). The pad 3a3 (c) faces the corresponding electrode pad 6a (c).

電極パッド３ａ１（ａ）の配列ピッチｎ１、電極パッド３ａ２（ｂ）の配列ピッチｎ２、及び電極パッド３ａ３（ｃ）の配列ピッチｎ３は、設計値で半導体チップ５の電極パッド６ａの配列ピッチｍ１の３倍になっている。   The arrangement pitch n1 of the electrode pads 3a1 (a), the arrangement pitch n2 of the electrode pads 3a2 (b), and the arrangement pitch n3 of the electrode pads 3a3 (c) are designed values of the arrangement pitch m1 of the electrode pads 6a of the semiconductor chip 5. It has tripled.

電極パッド３ａ１（ａ）と電極パッド３ａ２（ｂ）との配列ピッチｎ１２、並びに電極パッド３ａ２（ｂ）と電極パッド３ａ３（ｃ）との配列ピッチｎ２３は、設計値で電極パッド６ａの配列ピッチｍ１と同一になっている。   The arrangement pitch n12 between the electrode pad 3a1 (a) and the electrode pad 3a2 (b) and the arrangement pitch n23 between the electrode pad 3a2 (b) and the electrode pad 3a3 (c) are designed values of the arrangement pitch m1 of the electrode pad 6a. Is the same.

本実施例２においても、前述の実施例１と同様の効果が得られる。   Also in the second embodiment, the same effect as in the first embodiment can be obtained.

また、各列の電極パッドの配列ピッチが大きくなるので、電極パッド間に配線を通しても、各パッド列の長さは長く成らない。   Further, since the arrangement pitch of the electrode pads in each row is increased, the length of each pad row is not increased even if the wiring is passed between the electrode pads.

［実施例３］
図１９は、本発明の実施例３である半導体装置の概略構成を示す模式的平面図であり、図２０は、図１９のボンディングワイヤを省略して示す模式的平面図である。 [Example 3]
FIG. 19 is a schematic plan view showing a schematic configuration of a semiconductor device that is Embodiment 3 of the present invention, and FIG. 20 is a schematic plan view in which the bonding wires of FIG. 19 are omitted.

本実施例３は、パッド配列ピッチを小さくする本発明を４列パッド配置に適用した例である。   The third embodiment is an example in which the present invention for reducing the pad arrangement pitch is applied to a four-row pad arrangement.

図１９及び２０に示すように、電極パッド３ａ１〜３ａ４（ａ〜ｄ）は夫々対応する電極パッド６ａ（ａ〜ｄ）と向かい合っている。電極パッド３ａ１（ａ）の配列ピッチｎ１、電極パッド３ａ２（ｂ）の配列ピッチｎ２、電極パッド３ａ３（ｃ）の配列ピッチｎ３、電極パッド３ａ４（ｄ）の配列ピッチｎ４は、電極パッド６ａの配列ピッチｍ１の４倍になっている。   As shown in FIGS. 19 and 20, the electrode pads 3a1 to 3a4 (a to d) face the corresponding electrode pads 6a (a to d), respectively. The arrangement pitch n1 of the electrode pads 3a1 (a), the arrangement pitch n2 of the electrode pads 3a2 (b), the arrangement pitch n3 of the electrode pads 3a3 (c), and the arrangement pitch n4 of the electrode pads 3a4 (d) are the arrangement of the electrode pads 6a. It is four times the pitch m1.

電極パッド３ａ１と電極パッド３ａ２との配列ピッチｎ１２、電極パッド３ａ２と電極パッド３ａ３との配列ピッチｎ２３、並びに電極パッド３ａ３と電極パッド３ａ４との配列ピッチｎ３４は、設計値が電極パッド６ａの配列ピッチｍ１と同一になっている。   The arrangement pitch n12 of the electrode pad 3a1 and the electrode pad 3a2, the arrangement pitch n23 of the electrode pad 3a2 and the electrode pad 3a3, and the arrangement pitch n34 of the electrode pad 3a3 and the electrode pad 3a4 are designed values of the arrangement pitch of the electrode pad 6a. It is the same as m1.

本実施例３においても、前述の実施例１と同様の効果が得られる。   Also in the third embodiment, the same effect as in the first embodiment can be obtained.

また、各列の電極パッドの配列ピッチが大きくなるので、電極パッド間に配線を通しても、各パッド列の長さは長く成らない。   Further, since the arrangement pitch of the electrode pads in each row is increased, the length of each pad row is not increased even if the wiring is passed between the electrode pads.

［実施例４］
図２１は、本発明の実施例４である半導体装置の概略構成を示す模式的平面図である。 [Example 4]
FIG. 21 is a schematic plan view showing a schematic configuration of a semiconductor device that is Embodiment 4 of the present invention.

本実施例４は、キャピラリ干渉を抑制する本発明を４列パッド配置に適用した例である。本実施例４においても、実施例１と同様の効果が得られる。   The fourth embodiment is an example in which the present invention for suppressing capillary interference is applied to a four-row pad arrangement. In the fourth embodiment, the same effect as in the first embodiment can be obtained.

更には、最初にボンディングワイヤで接続された位置と最後にボンディングワイヤで接続される位置が千鳥配置の関係を満たせば、電極パッドの配置は４列以上であっても良い。   Further, the electrode pads may be arranged in four or more rows as long as the first connection position with the bonding wire and the last connection position with the bonding wire satisfy the staggered relationship.

以上、本発明者によってなされた発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

１…半導体装置、
２…配線基板、３ａ１，３ａ２，３ｂ１，３ｂ２，３ｂ３，３ｃ，３ｄ，３ｅ…電極パッド（接続部）、４ａ，４ｂ…配線、
５…半導体チップ、５ａ，５ｂ，５ｃ，５ｄ…第１〜第４の辺、６ａ，６ｂ，６ｃ，６ｄ…電極パッド（ボンディングパッド）、
７，８…半導体チップ、９…電極パッド（ボンディングパッド）、
１０ａ１，１０ａ２，１０ｂ１，１０ｂ２，１０ｂ３，１０ｃ，１０ｄ，１０ｅ…ボンディングワイヤ、１１…樹脂封止体、１２…半田バンプ。 1 ... Semiconductor device,
2 ... wiring board, 3a1, 3a2, 3b1, 3b2, 3b3, 3c, 3d, 3e ... electrode pads (connection portions), 4a, 4b ... wiring,
5 ... Semiconductor chip, 5a, 5b, 5c, 5d ... 1st-4th edge, 6a, 6b, 6c, 6d ... Electrode pad (bonding pad),
7, 8 ... Semiconductor chip, 9 ... Electrode pad (bonding pad),
10 a 1, 10 a 2, 10 b 1, 10 b 2, 10 b 3, 10 c, 10 d, 10 e... Bonding wire, 11.

Claims (4)

以下の工程を含むことを特徴とする半導体装置の製造方法：
（ａ）第１辺を有する上面と、前記上面に形成されたチップ搭載部と、前記第１辺に沿って配置され、かつ平面視において前記第１辺と前記チップ搭載部との間に配置された複数の第１接続部と、前記第１辺に沿って配置され、かつ平面視において前記第１辺と前記複数の第１接続部との間に配置された複数の第２接続部と、前記第１辺に沿って配置され、かつ平面視において前記第１辺と前記複数の第２接続部との間に配置された複数の第３接続部と、前記上面とは反対側の下面と、を備えた配線基板を準備する工程；
（ｂ）第２辺を有する表面と、前記第２辺に沿って一列に前記表面に形成された複数の電極パッドと、前記表面とは反対側の裏面と、を備えた半導体チップを、前記半導体チップの前記第２辺が前記配線基板の前記第１辺と並ぶように、前記チップ搭載部に搭載する工程；
（ｃ）前記複数の電極パッドのうちの複数の第１電極パッドと前記複数の第１接続部を、複数の第１ワイヤを介してそれぞれ電気的に接続する工程；
（ｄ）前記（ｃ）工程の後、前記複数の電極パッドのうちの第２電極パッドと前記複数の第２接続部のうちの一つを、第２ワイヤを介して電気的に接続する工程；
（ｅ）前記（ｄ）工程の後、前記複数の電極パッドのうちの第３電極パッドと前記複数の第３接続部のうちの一つを、第３ワイヤを介して電気的に接続する工程；
ここで、前記複数の第１電極パッドは、前記半導体チップの前記第２辺の第１端部側に位置する外側電極パッドと、前記外側電極パッドよりも前記第１端部から離れた内側電極パッドと、を有しており、
前記第２電極パッドは、平面視において、前記外側電極パッドと前記内側電極パッドの間に配置されており、
前記第３電極パッドは、平面視において、前記第２電極パッドと前記内側電極パッドの間に配置されており、
前記（ｄ）工程では、前記第２ワイヤの一部が前記複数の第１ワイヤのそれぞれの上方に位置するように、第２ワイヤを介して電気的に接続し、
前記（ｅ）工程では、前記第３ワイヤの一部が前記第２ワイヤの上方に位置するように、第３ワイヤを介して電気的に接続し、
前記複数の電極パッドのそれぞれの平面形状は、第１部分と、平面視において前記第１部分よりも前記半導体チップの前記第２辺から遠くに位置する第２部分と、を有する長方形からなり、
前記（ｃ）工程では、前記複数の第１ワイヤのそれぞれを前記複数の第１電極パッドのそれぞれの前記第１部分に接続し、
前記（ｅ）工程では、前記第３ワイヤを前記第３電極パッドの前記第２部分に接続し、
前記複数の第１、第２および第３ワイヤは、平面視において、前記半導体チップの前記第２辺の中心部を経由し、かつ前記第２辺と直交する仮想線に対して鋭角をなす角度で、かつ前記仮想線から離れる方向に、前記複数の第１、第２および第３電極パッドからそれぞれ延在している。 A method for manufacturing a semiconductor device comprising the following steps:
(A) An upper surface having a first side, a chip mounting portion formed on the upper surface, and disposed along the first side, and disposed between the first side and the chip mounting portion in plan view. A plurality of first connection portions, and a plurality of second connection portions disposed along the first side and disposed between the first side and the plurality of first connection portions in a plan view. A plurality of third connection portions arranged along the first side and arranged between the first side and the plurality of second connection portions in plan view, and a lower surface opposite to the upper surface And a step of preparing a wiring board comprising:
(B) a surface having a second side, and a plurality of electrode pads formed on the surface in a row along the second side, and the back opposite to the surface, the semiconductor chip with the Mounting on the chip mounting portion such that the second side of the semiconductor chip is aligned with the first side of the wiring board ;
(C) electrically connecting a plurality of first electrode pads of the plurality of electrode pads and the plurality of first connection portions through a plurality of first wires, respectively;
(D) After the step (c), a step of electrically connecting a second electrode pad of the plurality of electrode pads and one of the plurality of second connection portions via a second wire. ;
(E) After the step (d), electrically connecting a third electrode pad of the plurality of electrode pads and one of the plurality of third connection portions via a third wire. ;
Here, the plurality of first electrode pads include an outer electrode pad positioned on the first end side of the second side of the semiconductor chip, and an inner electrode farther from the first end than the outer electrode pad. has a pad, the,
The second electrode pad is disposed between the outer electrode pad and the inner electrode pad in plan view,
The third electrode pad is disposed between the second electrode pad and the inner electrode pad in a plan view;
In the step (d), the second wire is electrically connected via the second wire so that a part of the second wire is positioned above each of the plurality of first wires,
In the step (e), the third wire is electrically connected via the third wire so that a part of the third wire is located above the second wire,
Each planar shape of the plurality of electrode pads is a rectangle having a first portion and a second portion located farther from the second side of the semiconductor chip than the first portion in plan view,
In the step (c), each of the plurality of first wires is connected to the first portion of each of the plurality of first electrode pads ,
In the step (e), the third wire is connected to the second portion of the third electrode pad ,
The plurality of first, second, and third wires form an acute angle with a virtual line that passes through the center of the second side of the semiconductor chip and is orthogonal to the second side in plan view. in, and in a direction away from the imaginary line, the plurality of first, extending respectively from the second and third electrode pads. 請求項１に記載の半導体装置の製造方法において、前記（ｃ）乃至（ｅ）工程は、キャピラリを用いて行われることを特徴とする半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the steps (c) to (e) are performed using a capillary. 請求項２に記載の半導体装置の製造方法において、前記（ｅ）工程の後、前記半導体チップ、前記複数の第１ワイヤ、前記第２ワイヤおよび前記第３ワイヤを、樹脂で封止することを特徴とする半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein after the step (e), the semiconductor chip, the plurality of first wires, the second wires, and the third wires are sealed with a resin. A method of manufacturing a semiconductor device. 請求項３に記載の半導体装置の製造方法において、前記半導体チップ、前記複数の第１ワイヤ、前記第２ワイヤおよび前記第３ワイヤを前記樹脂で封止した後、複数の外部接続用端子を前記配線基板の前記下面に形成することを特徴とする半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 3, wherein after sealing the semiconductor chip, the plurality of first wires, the second wire, and the third wire with the resin, a plurality of external connection terminals are connected to the semiconductor device. A method of manufacturing a semiconductor device, comprising forming the wiring substrate on the lower surface.
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