JP3848333B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP3848333B2 JP3848333B2 JP2004108784A JP2004108784A JP3848333B2 JP 3848333 B2 JP3848333 B2 JP 3848333B2 JP 2004108784 A JP2004108784 A JP 2004108784A JP 2004108784 A JP2004108784 A JP 2004108784A JP 3848333 B2 JP3848333 B2 JP 3848333B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- multilayer wiring
- substrate
- sealing member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
110、120、610、910 チップ
150、160、 170 金属細線
140 リード
420、620、920 はんだボール
Claims (7)
- 封止部材と、
前記封止部材の内部に位置し、第1面と該第1面に対向する第2面を有する基板と、
前記封止部材の内部に位置し、前記基板の前記第1面上に設けられる第1のチップと、
前記封止部材の内部に位置し、前記基板の前記第2面上に設けられる第2のチップと、
前記封止部材の内部に位置するインナーリードと該封止部材の外部に位置するアウターリードとにより構成され、前記第1及び第2のチップと電気的に接続されるリードとを有し、
前記インナーリードは、前記基板の前記第2面上に設けられる第1の水平部と、前記アウターリードと接続する第2の水平部と、該第1及び第2の水平部を結び該第2の水平部に向かって上昇する傾斜部とを有し、
前記封止部材は、前記第1のチップ上に形成される第1の封止部材と、該第1の封止部材と同じ厚みを有し前記第2のチップ上に形成される第2の封止部材とにより構成されることを特徴とする半導体装置。 - 前記第1のチップと前記基板の前記第1面に形成された第1のボンディングパッドとを電気的に接続する第1の金属細線と、
前記インナーリードと前記基板の前記第1面に形成された第2のボンディングパッドとを電気的に接続する第2の金属細線とを有することを特徴とする請求項1記載の半導体装置。 - 前記インナーリードと前記第2のチップとを電気的に接続する第3の金属細線とを有することを特徴とする請求項2記載の半導体装置。
- 突起部を介して、前記基板の前記第2面上に前記インナーリードを設けることを特徴とする請求項1記載の半導体装置。
- 突起部を介して、前記基板の前記第1面上に前記第1のチップを設けることを特徴とする請求項1記載の半導体装置。
- 突起部を介して、前記基板の前記第2面上に前記第2のチップを設けることを特徴とする請求項1記載の半導体装置。
- 前記基板は多層配線基板であることを特徴とする請求項3−6のいずれか一つに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004108784A JP3848333B2 (ja) | 2004-04-01 | 2004-04-01 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004108784A JP3848333B2 (ja) | 2004-04-01 | 2004-04-01 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002103967A Division JP3576146B2 (ja) | 2002-04-05 | 2002-04-05 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004221615A JP2004221615A (ja) | 2004-08-05 |
JP3848333B2 true JP3848333B2 (ja) | 2006-11-22 |
Family
ID=32906311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004108784A Expired - Fee Related JP3848333B2 (ja) | 2004-04-01 | 2004-04-01 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3848333B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5132070B2 (ja) * | 2006-03-31 | 2013-01-30 | オンセミコンダクター・トレーディング・リミテッド | 回路装置およびその製造方法 |
JP5359176B2 (ja) * | 2008-10-16 | 2013-12-04 | 株式会社デンソー | モールドパッケージおよびその製造方法 |
-
2004
- 2004-04-01 JP JP2004108784A patent/JP3848333B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2004221615A (ja) | 2004-08-05 |
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