JP2010040955A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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Abstract
【解決手段】上段の第2半導体チップ2の端部と下段の第1半導体チップ1の端部との距離が第1半導体チップ1の端部と配線基板7のボンディングリード7cとの距離よりも長くなるように、第2半導体チップ2が第1半導体チップ1上に搭載され、かつ第2半導体チップ2と接続する複数の第2ワイヤ3bが逆ボンディング方式により形成されていることで、第1半導体チップ1の外側で第2ワイヤ3bを急峻に立ち上がらせて接続することができるため、第1半導体チップ1の端部と第2ワイヤ3bの間にクリアランスを大きく設けることができ、下段側の第1半導体チップ1と第2ワイヤ3bのショートを防止できる。
【選択図】図3
Description
図1は本発明の実施の形態1の半導体装置の構造の一例を封止体を透過して示す平面図、図2は図1のA−A線に沿って切断した構造の一例を示す断面図、図3は図1のB−B線に沿って切断した構造の一例を示す断面図である。
図30は本発明の実施の形態2の半導体装置の構造の一例を封止体を透過して示す平面図、図31は図30のA−A線に沿って切断した構造の一例を示す断面図、図32は図30のB−B線に沿って切断した構造の一例を示す断面図である。また、図33は図30に示す半導体装置の製造方法の第1ワイヤボンドにおける下段チップのワイヤボンディング状態の一例を示す平面図、図34は図33のA−A線に沿って切断した構造の一例を示す断面図、図35は図33のB−B線に沿って切断した構造の一例を示す断面図である。
1a 第1主面
1b 裏面
1c 第1パッド(第1電極パッド)
1d 中心
2 第2半導体チップ
2a 第2主面
2b 裏面
2c 第2パッド(第2電極パッド)
2d 中心
3 ワイヤ
3a 第1ワイヤ
3b 第2ワイヤ
3c 金バンプ
3d 折り曲げ点
4 封止体
5 半田ボール(外部端子)
6 接着剤
7 配線基板(基板)
7a 表面(主面)
7b 裏面
7c ボンディングリード
7d ソルダレジスト膜
7e 開口部
7f モールドエリア
7g チップ搭載領域
8 マルチチップモジュール(半導体装置)
9 モールド金型
9a 上型
9b キャビティ
9c ゲート
9d 下型
9e 金型面
9f ポット
9g ランナ
10 モールドレジン(樹脂)
11 充填方向
12 マルチチップモジュール(半導体装置)
13 半導体チップ
13a 主面
13b パッド
14 ワイヤリング方向
15 半導体装置
16 突起電極
17 アンダーフィル樹脂
Claims (11)
- 複数の第1ボンディングリード及び複数の第2ボンディングリードが形成された表面、及び前記表面と反対側の裏面を有する基板と、
複数の第1パッドが形成された第1主面、及び前記第1主面とは反対側の第1裏面を有し、前記基板の複数のボンディングリードの内側に位置するように、前記基板の前記表面上に搭載された第1半導体チップと、
複数の第2パッドが形成され、前記第1半導体チップの外形寸法よりも小さい第2主面、及び前記第2主面とは反対側の第2裏面を有し、前記第1半導体チップの前記複数の第1パッドの内側に位置し、前記第2裏面が前記第1半導体チップと対向するように、前記第1半導体チップ上に搭載された第2半導体チップと、
前記第1半導体チップの前記複数の第1パッドと前記基板の前記複数の第1ボンディングリードとをそれぞれ電気的に接続する複数の第1接続手段と、
前記第2半導体チップの前記複数の第2パッドと前記基板の前記複数の第2ボンディングリードとをそれぞれ電気的に接続する複数の第2接続手段と、
前記第1半導体チップ、前記第2半導体チップ及び前記複数の第2接続手段を封止する封止体と、
前記基板の前記裏面に設けられた複数の外部端子と、
を含み、
前記第2半導体チップは、前記第2半導体チップの端部と前記第1半導体チップの端部との距離が前記第1半導体チップの端部と前記基板の前記ボンディングリードとの距離よりも長くなるように、前記第1半導体チップの前記第1主面上に搭載され、
前記第2接続手段は、ワイヤであり、
前記第2ボンディングリード上における前記ワイヤと前記基板の前記表面との成す角度は、前記第2半導体チップの前記第2パッド上における前記ワイヤと前記第2半導体チップの前記第2主面との成す角度より大きいことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記基板の前記表面の平面形状は、一対の第1辺と、前記第1辺と交差する一対の第2辺を有する四角形であり、
前記複数の第2ボンディングリードは、前記基板の前記第1辺に沿って形成され、
前記第2半導体チップの前記第2主面の平面形状は、前記基板の前記第1辺と並ぶ一対の第3辺と、前記第3辺と交差する一対の第4辺を有する四角形であり、
前記複数の第2パッドは、前記第2半導体チップの前記第3辺に沿って形成されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記複数の第2ボンディングリードは、さらに前記第2辺に沿って形成され、
前記複数の第2パッドは、さらに前記第4辺に沿って形成され、
前記基板の前記第2辺に沿って形成された前記第2ボンディングリード上における前記ワイヤと前記基板の前記表面との成す角度は、前記第2半導体チップの前記第4辺に沿って形成された前記第2パッド上における前記ワイヤと前記第2半導体チップの前記第2主面との成す角度より小さいことを特徴とする半導体装置。 - 請求項3記載の半導体装置において、前記第1半導体チップの前記第1主面の平面形状は、前記基板の前記第1辺と並ぶ一対の第5辺と、前記第5辺と交差する一対の第6辺を有する四角形であり、
前記第1半導体チップの前記第5辺と前記基板の前記第1辺に沿って形成された前記第2ボンディングリードとの距離(M1)は、前記第1半導体チップの前記第6辺と前記基板の前記第2辺に沿って形成された前記第2ボンディングリードとの距離(M2)よりも短いことを特徴とする半導体装置。 - 請求項4記載の半導体装置において、前記第2半導体チップの厚さは、前記第1半導体チップの厚さよりも厚いことを特徴とする半導体装置。
- (a)複数の第1ボンディングリード及び複数の第2ボンディングリードが形成された表面、及び前記表面と反対側の裏面を有する基板を準備する工程;
(b)複数の第1パッドが形成された第1主面、及び前記第1主面とは反対側の第1裏面を有する第1半導体チップを、前記基板の複数のボンディングリードの内側に位置するように、前記基板の前記表面上に搭載する工程;
(c)複数の第2パッドが形成され、前記第1半導体チップの外形寸法よりも小さい第2主面、及び前記第2主面とは反対側の第2裏面を有する第2半導体チップを、前記第1半導体チップの前記複数の第1パッドの内側に位置し、前記第2裏面が前記第1半導体チップと対向するように、前記第1半導体チップ上に搭載する工程;
(d)前記第1半導体チップの前記複数の第1パッドと前記基板の前記複数の第1ボンディングリードとを、複数の第1接続手段を介してそれぞれ電気的に接続する工程;
(e)前記第2半導体チップの前記複数の第2パッドと前記基板の前記複数の第2ボンディングリードとを、複数の第2接続手段を介してそれぞれ電気的に接続する工程;
(f)前記第1半導体チップ、前記第2半導体チップ及び前記複数の第2接続手段を樹脂で封止する工程;
(g)前記基板の前記裏面に複数の外部端子を形成する工程;
を含み、
前記第2半導体チップは、前記第2半導体チップの端部と前記第1半導体チップの端部との距離が前記第1半導体チップの端部と前記基板の前記ボンディングリードとの距離よりも長くなるように、前記第1半導体チップの前記第1主面上に搭載され、
前記第2接続手段は、ワイヤであり、
前記(e)工程では、前記基板の前記第2ボンディングリードに前記ワイヤの一端部を接続した後、前記ワイヤの一端部とは反対側の他端部を前記第2半導体チップの前記第2パッドに接続することを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、前記基板の前記表面の平面形状は、一対の第1辺と、前記第1辺と交差する一対の第2辺を有する四角形であり、
前記複数の第2ボンディングリードは、前記基板の前記第1辺に沿って形成され、
前記第2半導体チップの前記第2主面の平面形状は、前記基板の前記第1辺と並ぶ一対の第3辺と、前記第3辺と交差する一対の第4辺を有する四角形であり、
前記複数の第2パッドは、前記第2半導体チップの前記第3辺に沿って形成されていることを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、前記(f)工程では、前記基板の前記第1辺側から前記樹脂を供給することを特徴とする半導体装置の製造方法。
- 請求項8記載の半導体装置の製造方法において、
前記複数の第2ボンディングリードは、さらに前記第2辺に沿って形成され、
前記複数の第2パッドは、さらに前記第4辺に沿って形成され、
前記基板の前記第2辺に沿って形成された前記第2ボンディングリードと前記第2半導体チップの前記第4辺に沿って形成された前記第2パッドとを電気的に接続する前記ワイヤは、前記第2半導体チップの前記第2パッドに前記ワイヤの一端部を接続した後、前記ワイヤの前記一端部とは反対側の前記他端部を前記基板の前記第2ボンディングリードに接続することを特徴とする半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、前記第1半導体チップの前記第1主面の平面形状は、前記基板の前記第1辺と並ぶ一対の第5辺と、前記第5辺と交差する一対の第6辺を有する四角形であり、
前記第1半導体チップの前記第5辺と前記基板の前記第1辺に沿って形成された前記第2ボンディングリードとの距離(M1)は、前記第1半導体チップの前記第6辺と前記基板の前記第2辺に沿って形成された前記第2ボンディングリードとの距離(M2)よりも短いことを特徴とする半導体装置の製造方法。 - 請求項10記載の半導体装置の製造方法において、前記第2半導体チップの厚さは前記第1半導体チップの厚さより厚いことを特徴とする半導体装置の製造方法。
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH0525602A (ja) * | 1991-07-17 | 1993-02-02 | Nippon Steel Corp | メツキ密着性に優れたアルミニウムメツキオーステナイト系ステンレス鋼板の製造法 |
JP2013125765A (ja) * | 2011-12-13 | 2013-06-24 | Elpida Memory Inc | 半導体装置 |
CN109003947A (zh) * | 2018-07-23 | 2018-12-14 | 苏州锝耀电子有限公司 | 大功率层叠式芯片结构 |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000307057A (ja) * | 1999-02-17 | 2000-11-02 | Sharp Corp | 半導体装置、およびその製造方法 |
JP2007184385A (ja) * | 2006-01-06 | 2007-07-19 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2008078367A (ja) * | 2006-09-21 | 2008-04-03 | Renesas Technology Corp | 半導体装置 |
JP2008159786A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | 半導体装置及び接着配線部材の製造方法 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000307057A (ja) * | 1999-02-17 | 2000-11-02 | Sharp Corp | 半導体装置、およびその製造方法 |
JP2007184385A (ja) * | 2006-01-06 | 2007-07-19 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP2008078367A (ja) * | 2006-09-21 | 2008-04-03 | Renesas Technology Corp | 半導体装置 |
JP2008159786A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | 半導体装置及び接着配線部材の製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0525602A (ja) * | 1991-07-17 | 1993-02-02 | Nippon Steel Corp | メツキ密着性に優れたアルミニウムメツキオーステナイト系ステンレス鋼板の製造法 |
JP2013125765A (ja) * | 2011-12-13 | 2013-06-24 | Elpida Memory Inc | 半導体装置 |
US9449951B2 (en) | 2011-12-13 | 2016-09-20 | Ps4 Luxco S.A.R.L. | Semiconductor device |
CN109003947A (zh) * | 2018-07-23 | 2018-12-14 | 苏州锝耀电子有限公司 | 大功率层叠式芯片结构 |
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