CN101593736B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN101593736B
CN101593736B CN2009102029677A CN200910202967A CN101593736B CN 101593736 B CN101593736 B CN 101593736B CN 2009102029677 A CN2009102029677 A CN 2009102029677A CN 200910202967 A CN200910202967 A CN 200910202967A CN 101593736 B CN101593736 B CN 101593736B
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wiring
insulating layer
layer
semiconductor device
semiconductor chip
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CN101593736A (zh
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冈田三香子
石川智和
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NEC Electronics Corp
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Renesas Electronics Corp
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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JP5001903B2 (ja) 2012-08-15
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TWI458057B (zh) 2014-10-21

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