JP4918695B2 - メモリデバイス用分離トレンチ - Google Patents
メモリデバイス用分離トレンチ Download PDFInfo
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- JP4918695B2 JP4918695B2 JP2007519287A JP2007519287A JP4918695B2 JP 4918695 B2 JP4918695 B2 JP 4918695B2 JP 2007519287 A JP2007519287 A JP 2007519287A JP 2007519287 A JP2007519287 A JP 2007519287A JP 4918695 B2 JP4918695 B2 JP 4918695B2
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- 238000002955 isolation Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 42
- 238000007667 floating Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 78
- 238000000137 annealing Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 claims 1
- 230000005641 tunneling Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Description
104…メモリアレイ 106…アドレスデコーダ
108…行アクセス回路 110…列アクセス回路
112…制御回路 114…I/O回路
116…アドレスバッファ回路 120…マイクロプロセッサ
122…制御リンク 124…データリンク
126…アドレスリンク 200…基板
202…第1誘電体層 204、260…導電層
206…マスク層 210…トレンチ
212…第3誘電体層 220…第4誘電体層
230…第5誘電体層 232…第1の誘電体充填層
240…第6誘電体層 242…第2の誘電体充填層
250…ゲート間誘電体層
Claims (19)
- 基板内を延在するトレンチの一部に、第1誘電体の層と前記第1誘電体の層上に形成された第2誘電体の層とを備える第1の誘電体充填層を、その上側表面が、前記基板の上側表面よりも下方に位置するように形成するステップと、
第3誘電体からなる第2の誘電体充填層を、前記第1の誘電体充填層の上側表面に、前記第1の誘電体充填層の上側表面から、その上方に向かって、前記基板の上側表面上に形成された第4誘電体の層と、その上に形成された第1導電層とを貫通する前記トレンチの残余の部分にわたって延在し、且つ前記第4誘電体の層の一部と前記第1導電層の一部とに接するように形成するステップと、
前記第2の誘電体充填層を形成するステップの後、
前記第1導電層上に第5誘電体の層を形成するステップと、
前記第5誘電体の層上に第2導電層を形成するステップと、を備え、
前記第5誘電体の層の上側表面は、前記第2の誘電体充填層の上側表面よりも下方に配置されることを特徴するメモリデバイスの一部を形成する方法。 - 請求項1記載の方法において、第1の誘電体充填層を形成する前記ステップは、前記トレンチの一部を覆い、且つ前記基板上に配置された第6誘電体の層上に、前記第1誘電体の層を形成するステップをさらに備えることを特徴とする方法。
- 請求項2記載の方法において、第2の誘電体充填層を形成する前記ステップは、前記第6誘電体の層上に前記第2の誘電体充填層の一部を形成するステップを備えることを特徴とする方法。
- 請求項1〜3のいずれか1項に記載の方法において、前記第1誘電体は窒化物であり、前記第2誘電体はスピンオン誘電体であり、前記第3誘電体は高密度プラズマによる酸化物であることを特徴とする方法。
- 請求項1〜4のいずれか1項に記載の方法において、第1の誘電体充填層を形成する前記ステップは、前記第2誘電体の層をキュアするステップをさらに備えることを特徴とする方法。
- 請求項5記載の方法において、前記第2誘電体の層をキュアする前記ステップは酸化工程を備えることを特徴とする方法。
- 請求項1〜6のいずれか1項に記載の方法において、前記第4誘電体の層は、トンネル誘電体層であることを特徴とする方法。
- 請求項1〜7のいずれか1項に記載の方法において、前記トレンチは、前記第1導電層上に配置されたハードマスク層をパターニングして、エッチングすることによって形成されることを特徴とする方法。
- 請求項1〜8のいずれか1項に記載の方法において、前記第1の誘電体充填層を形成する前記ステップは、
前記第1誘電体の層上に前記第2誘電体の層を形成して、前記第2誘電体の層で前記トレンチを前記基板の上側表面より上のレベルまで充填するステップと、
前記第2誘電体の層の一部を除去して、前記第2誘電体の層の上側表面を前記基板の上側表面よりも下方に位置させるステップと、
を備えることを特徴とする方法。 - 請求項9記載の方法において、前記第1の誘電体充填層を形成する前記ステップは、前記第1誘電体の層の一部を前記第2誘電体の層の上側表面のレベルまで選択的に除去するステップをさらに備えることを特徴とする方法。
- 請求項9又は10のいずれか1項に記載の方法において、前記第2誘電体の層の一部を除去する前記ステップの前に、前記第2誘電体の層をアニールするステップをさらに備えることを特徴とする方法。
- 請求項1〜7、9〜11のいずれか1項に記載の方法において、前記第5誘電体の層は、ゲート間誘電体層であることを特徴とする方法。
- 請求項12記載の方法において、前記第1導電層は浮遊ゲート層であり、前記第2導電層は制御ゲート層であることを特徴とする方法。
- 第1誘電体の層とその層上に形成された第2誘電体の層とを有し、基板内に延在するトレンチ内に配置され、上側表面が、前記基板の上側表面よりも下方に位置している第1の誘電体充填層と、
前記トレンチ内の前記第1の誘電体充填層の上側表面上に配置され、前記基板の上側表面上に形成された第4誘電体の層と、その層上に形成された第1導電層とを貫通し、前記第4誘電体の層の一部と前記第1導電層の一部とに接する、第3誘電体からなる第2の誘電体充填層と、
前記第1導電層上に形成された第5誘電体の層と、
前記第5誘電体の層上に形成された第2導電層と、
を備える集積回路デバイスであって、
前記第5誘電体の層の上側表面は、前記第2の誘電体充填層の上側表面よりも下方に位置していることを特徴とする集積回路デバイス。 - 請求項14記載の集積回路デバイスにおいて、前記基板と前記第1の誘電体充填層の前記第1誘電体との間に介在し、且つ前記第2の誘電体充填層の一部と前記基板との間に介在する第6誘電体の層をさらに備えることを特徴とする集積回路デバイス。
- 請求項14又は15のいずれか1項に記載の集積回路デバイスにおいて、前記第1誘電体は窒化物であり、前記第2誘電体はアニールされたスピンオン誘電体であることを特徴とする集積回路デバイス。
- 請求項14〜16のいずれか1項に記載の集積回路デバイスにおいて、前記第3誘電体は高密度プラズマによる酸化物であることを特徴とする集積回路デバイス。
- 請求項14〜17のいずれか1項に記載の集積回路デバイスにおいて、前記第4誘電体の層は、トンネル誘電体層であり、前記第1導電層は浮遊ゲート層であり、前記第5誘電体の層は、層間誘電体層であり、且つ前記第2導電層は、制御ゲート層であることを特徴とする集積回路デバイス。
- 請求項14〜18のいずれか1項に記載の集積回路デバイスにおいて、前記集積回路デバイスはメモリデバイスであることを特徴とする集積回路デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/878,805 | 2004-06-28 | ||
US10/878,805 US7332408B2 (en) | 2004-06-28 | 2004-06-28 | Isolation trenches for memory devices |
PCT/US2005/022143 WO2006012163A1 (en) | 2004-06-28 | 2005-06-22 | Isolation trenches for memory devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008504713A JP2008504713A (ja) | 2008-02-14 |
JP4918695B2 true JP4918695B2 (ja) | 2012-04-18 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007519287A Active JP4918695B2 (ja) | 2004-06-28 | 2005-06-22 | メモリデバイス用分離トレンチ |
Country Status (6)
Country | Link |
---|---|
US (5) | US7332408B2 (ja) |
EP (1) | EP1774586B1 (ja) |
JP (1) | JP4918695B2 (ja) |
SG (1) | SG141446A1 (ja) |
TW (1) | TWI316745B (ja) |
WO (1) | WO2006012163A1 (ja) |
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