US20210143275A1 - Finfet stack gate memory and mehod of forming thereof - Google Patents
Finfet stack gate memory and mehod of forming thereof Download PDFInfo
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- US20210143275A1 US20210143275A1 US16/815,151 US202016815151A US2021143275A1 US 20210143275 A1 US20210143275 A1 US 20210143275A1 US 202016815151 A US202016815151 A US 202016815151A US 2021143275 A1 US2021143275 A1 US 2021143275A1
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- 150000004767 nitrides Chemical class 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 241000588731 Hafnia Species 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 description 8
- 229910052906 cristobalite Inorganic materials 0.000 description 8
- 229910052682 stishovite Inorganic materials 0.000 description 8
- 229910052905 tridymite Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000002349 favourable effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present disclosure relates to a stack gate memory and a method of forming thereof. More particularly, the present disclosure relates to a FINFET stack gate memory and a method of forming thereof.
- FIG. 8 is a schematic view of a structure of a stack gate memory 30 of prior art.
- a SiO 2 film 31 is grown on a p-type silicon wafer 32 in a furnace at 1000° C., and a thickness of the SiO 2 film 31 is about 200 ⁇ .
- masks and implants are applied to form a deep N-well, an N-well and a P-well.
- a silicon nitride (Si 3 N 4 ) film 33 is deposited for about 2000 ⁇ , a photo printing active area (AA) pattern is applied for transistors, and a stack of Si 3 N 4 /SiO 2 /silicon is etched in sequence.
- AA photo printing active area
- CG structure forming step a portion of the FG structure is removed in the non-memory cell area of the memory structure, a second polysilicon is disposed on a surface of the ONO layer in the memory cell area and on the surface of the substrate and a surface of the STI oxide in the non-memory cell area of the memory structure to form a CG structure, and the FinFET stack gate memory is formed.
- FIG. 1 is a step flow chart of a method of forming a FinFET stack gate memory according to an embodiment of the present disclosure.
- FIG. 4 is a schematic view of the FG structure forming step according to the embodiment of FIG. 1 .
- FIG. 7 is a schematic view of the CG structure forming step according to the embodiment of FIG. 1 .
- the nitride film 231 is formed on a thin oxide film 211 , and the thin oxide film 211 is disposed on a substrate 210 .
- the substrate 210 can be made of a silicon.
- the memory cell area 230 can be masked-off, and the nitride film 231 can be removed by an etching process in a non-memory cell area 240 .
- the STI oxide 221 can be disposed in the STI structure 220 via a process of chemical vapor deposition (CVD), and the STI oxide is performed via a chemical-mechanical polishing (CMP).
- CVD chemical vapor deposition
- CMP chemical-mechanical polishing
- the tunnel oxide 232 is disposed in the side-wall region formed in the stripping step S 102 , and it is favorable for increasing an effective memory cell channel width.
- the mask is applied for covering the memory cell area 230 , and the ONO layer 234 and the FG structure 233 are removed via the etching process in the non-memory cell area 240 for reserving for a plurality of peripheral devices. Furthermore, source/drain junctions for the memory cell area 230 and the peripheral devices are formed, and contact/metal connections are formed to allow proper electric connections.
- a channel width of a scaling barrier scaling below 120 nm can be maintained, and an effective channel width can be widen. Moreover, it is favorable for avoiding significant current loss and reliability issue, and also maintaining proper cell current. Further, a scaling limitation can be decreased, and a density of the FinFET stack gate memory can be increased.
- the STI structure 220 is disposed on the substrate 210 , and includes the STI oxide 221 .
- the STI oxide 221 is disposed in the STI structure 220 , the STI oxide 221 can be made of silicon oxide, and a thickness of the STI oxide 221 can be 600 ⁇ to 2400 ⁇ .
- the memory cell area 230 includes the nitride film 231 , the tunnel oxide 232 , the FG structure 233 , the ONO layer 234 and the CG structure 235 .
- the nitride film 231 is disposed on a surface of the STI structure 220 and below the surface of the substrate 210 .
- the tunnel oxide 232 is disposed on the substrate 210 , the tunnel oxide 232 can be made of silicon oxide, and a thickness of the tunnel oxide 232 can be 70 ⁇ to 105 ⁇ . It is worth mentioning that the best thickness of the tunnel oxide 232 is 95 ⁇ , but is not limited thereto.
- the FG structure 233 is disposed on the tunnel oxide 232 .
- the non-memory cell area 240 is connected to the memory cell area 230 , and includes the plurality of peripheral devices. Moreover, the memory cell area 230 is isolated from the non-memory cell area 240 , and a short circuit will not be caused.
- the peripheral devices includes a high voltage N-channel (HVN) logic device 241 , a low voltage N-channel (LVN) logic device 242 , a high voltage P-channel (HVP) logic device 243 and a low voltage P-channel (LVP) logic device 244 .
- a triple P-well (its reference numeral is omitted) is located on a deep N-well (its reference numeral is omitted) of the substrate 210 in the memory cell area 230 , and a P-well (its reference numeral is omitted) is located beside an N-well (its reference numeral is omitted) of the substrate 210 in the non-memory cell area 240 .
- an effective memory cell channel width is increased, a further memory cell size scaling can be allowed, and a current of the FinFET stack gate memory can be kept intact.
Abstract
Description
- This application claims priority to U.S. Provisional Application Ser. No. 62/933,588, filed Nov. 11, 2019, which is herein incorporated by reference.
- The present disclosure relates to a stack gate memory and a method of forming thereof. More particularly, the present disclosure relates to a FINFET stack gate memory and a method of forming thereof.
-
FIG. 8 is a schematic view of a structure of astack gate memory 30 of prior art. InFIG. 8 , a SiO2film 31 is grown on a p-type silicon wafer 32 in a furnace at 1000° C., and a thickness of the SiO2film 31 is about 200 Å. Then, masks and implants are applied to form a deep N-well, an N-well and a P-well. A silicon nitride (Si3N4)film 33 is deposited for about 2000 Å, a photo printing active area (AA) pattern is applied for transistors, and a stack of Si3N4/SiO2/silicon is etched in sequence. - However, a channel length of the
stack gate memory 30 of prior art scaling below 120 nm is a limitation, because a short channel effects including a memory cell punch-through and a hot carrier injection will be caused further scaling difficulty, and a significant current loss and a reliability issue will be happened. Moreover, a maximum current of thestack gate memory 30 is limited, because an effective channel width is less than 80 nm. There is a limitation of maximum current less than 20 μ, and it causes a difficulty of a read margin. That is, the read margin is small, and a product reliability is at risk. Therefore, a FINFET stack gate memory scaling below 120 nm with stable reliability needs to be developed. - According to one aspect of the present disclosure, a method of forming a FinFET stack gate memory includes a nitride film forming step, a stripping step, a floating gate (FG) structure forming step, an oxide-nitride-oxide (ONO) layer disposing step, a removing step and a control gate (CG) structure forming step. In the nitride film forming step, a nitride film is formed on a memory cell area of a memory structure with a shallow trench isolation (STI) structure. In the stripping step, a portion of the nitride film is stripped, the other portion of the nitride film which is unstripped is below a surface of a substrate and is remained at a bottom of the STI structure, and a STI oxide is disposed in the STI structure. In the FG structure forming step, a tunnel oxide is disposed on the surface of the substrate and a surface of the other portion of the nitride film, and a first polysilicon is disposed on the tunnel oxide in the memory cell area and on the surface of the substrate in a non-memory cell area of the memory structure to form a FG structure. In the ONO layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed on a surface of the FG structure, the surface of the other portion of the nitride film, and a surface of the other portion of the STI oxide which is unstripped after a portion of the STI oxide is stripped in the memory cell area. In the removing step, a portion of the ONO layer is removed in the non-memory cell area of the memory structure. In the CG structure forming step, a portion of the FG structure is removed in the non-memory cell area of the memory structure, a second polysilicon is disposed on a surface of the ONO layer in the memory cell area and on the surface of the substrate and a surface of the STI oxide in the non-memory cell area of the memory structure to form a CG structure, and the FinFET stack gate memory is formed.
- According to another aspect of the present disclosure, a FinFET stack gate memory includes a substrate, a shallow trench isolation (STI) structure and a memory cell area. A STI structure is disposed on the substrate, and includes a STI oxide. The STI oxide is disposed in the STI structure. The memory cell area includes a nitride film, a tunnel oxide, a floating gate (FG) structure, an oxide-nitride-oxide (ONO) layer and a control gate (CG) structure. The nitride film is disposed on a surface of the STI structure and below the surface of the substrate. The FG structure is disposed on the tunnel oxide. The ONO layer is disposed on the FG structure and the STI oxide, and the STI oxide is located between the ONO layer and the nitride film. The CG structure is disposed on the ONO layer, and the ONO layer is located between the FG structure and the CG structure.
- The present disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:
-
FIG. 1 is a step flow chart of a method of forming a FinFET stack gate memory according to an embodiment of the present disclosure. -
FIG. 2 is a schematic view of the nitride film forming step according to the embodiment ofFIG. 1 . -
FIG. 3 is a schematic view of the stripping step according to the embodiment ofFIG. 1 . -
FIG. 4 is a schematic view of the FG structure forming step according to the embodiment ofFIG. 1 . -
FIG. 5 is a schematic view of the ONO layer disposing step according to the embodiment ofFIG. 1 . -
FIG. 6 is a schematic view of the removing step according to the embodiment ofFIG. 1 . -
FIG. 7 is a schematic view of the CG structure forming step according to the embodiment ofFIG. 1 . -
FIG. 8 is a schematic view of a structure of a stack of Si3N4/SiO2/silicon of prior art. -
FIG. 1 is a step flow chart of a method of forming a FinFETstack gate memory 100 according to an embodiment of the present disclosure. InFIG. 1 , the method of forming the FinFETstack gate memory 100 includes a nitride film forming step S101, a stripping step S102, a floating gate (FG) structure forming step S103, an oxide-nitride-oxide (ONO) layer disposing step S104, a removing step S105 and a control gate (CG) structure forming step S106. -
FIG. 2 is a schematic view of the nitride film forming step S101 according to the embodiment ofFIG. 1 . InFIGS. 1 and 2 , anitride film 231 is formed on amemory cell area 230 of a memory structure (its reference numeral is omitted) with a shallow trench isolation (STI)structure 220, and thenitride film 231 can be made of a silicon nitride, but is not limited thereto. Before the nitride film forming step S101, theSTI structure 220 can be formed via an etching process, and a depth of theSTI structure 220 can be 2000 Å. In detail, thenitride film 231 is formed on athin oxide film 211, and thethin oxide film 211 is disposed on asubstrate 210. Thesubstrate 210 can be made of a silicon. Before the stripping step S102, thememory cell area 230 can be masked-off, and thenitride film 231 can be removed by an etching process in anon-memory cell area 240. -
FIG. 3 is a schematic view of the stripping step S102 according to the embodiment ofFIG. 1 . InFIGS. 1 and 3 , a portion of thenitride film 231 is stripped, the other portion of thenitride film 231 which is unstripped is below a surface of thesubstrate 210 and is remained at a bottom of theSTI structure 220, and aSTI oxide 221 is disposed in theSTI structure 220. Moreover, the portion of thenitride film 231 is stripped to 300 Å to 1400 Å, and a side-wall region is formed by the stripped portion of thenitride film 231 via a plasma etching. It is worth mentioning that every depth of each of the side-wall regions is similar. In detail, theSTI oxide 221 can be disposed in theSTI structure 220 via a process of chemical vapor deposition (CVD), and the STI oxide is performed via a chemical-mechanical polishing (CMP). -
FIG. 4 is a schematic view of the FG structure forming step S103 according to the embodiment ofFIG. 1 . InFIGS. 1 and 4 , atunnel oxide 232 is disposed on the surface of thesubstrate 210 and a surface of the other portion of thenitride film 231, and a first polysilicon is disposed on thetunnel oxide 232 in thememory cell area 230 and on the surface of thesubstrate 210 in thenon-memory cell area 240 of the memory structure to form aFG structure 233. In detail, the first polysilicon is disposed on thetunnel oxide 232 via a plasma process or the process of CVD at 300° C. to 800° C., and theFG structure 233 is performed via the CMP to form a FIN-shaped FG structure. Thetunnel oxide 232 is disposed in the side-wall region formed in the stripping step S102, and it is favorable for increasing an effective memory cell channel width. -
FIG. 5 is a schematic view of the ONO layer disposing step S104 according to the embodiment ofFIG. 1 . InFIGS. 1 and 5 , a portion of theSTI oxide 221 is stripped, and anONO layer 234 is disposed on a surface of theFG structure 233, the surface of the other portion of thenitride film 231, and a surface of the other portion of theSTI oxide 221 which is unstripped after a portion of theSTI oxide 221 is stripped in thememory cell area 230. In detail, a mask is applied for stripping the portion of theSTI oxide 221 in thememory cell area 230, and the portion of theSTI oxide 221 is stripped via a solution containing a hydrofluoric acid. After finishing stripping the portion of theSTI oxide 221, a photoresist (PR) is stripped, and theONO layer 234 is deposited via the process of CVD at 350° C. to 800° C. -
FIG. 6 is a schematic view of the removing step S105 according to the embodiment ofFIG. 1 . InFIGS. 1 and 6 , a portion of theONO layer 234 is removed in thenon-memory cell area 240 of the memory structure. -
FIG. 7 is a schematic view of the CG structure forming step S106 according to the embodiment ofFIG. 1 . InFIGS. 1 and 7 , a portion of theFG structure 233 is removed in thenon-memory cell area 240 of the memory structure, a second polysilicon is disposed on a surface of theONO layer 234 in thememory cell area 230 and on the surface of thesubstrate 210 and a surface of theSTI oxide 221 in thenon-memory cell area 240 of the memory structure to form aCG structure 235, and the FinFETstack gate memory 200 is formed. - In
FIGS. 6 and 7 , the mask is applied for covering thememory cell area 230, and theONO layer 234 and theFG structure 233 are removed via the etching process in thenon-memory cell area 240 for reserving for a plurality of peripheral devices. Furthermore, source/drain junctions for thememory cell area 230 and the peripheral devices are formed, and contact/metal connections are formed to allow proper electric connections. - Via the method of forming the FinFET stack gate memory of the present disclosure, a channel width of a scaling barrier scaling below 120 nm can be maintained, and an effective channel width can be widen. Moreover, it is favorable for avoiding significant current loss and reliability issue, and also maintaining proper cell current. Further, a scaling limitation can be decreased, and a density of the FinFET stack gate memory can be increased.
- In
FIG. 7 , the FinFETstack gate memory 200 of the present disclosure includes thesubstrate 210, theSTI structure 220, thememory cell area 230 and thenon-memory cell area 240. - In detail, the
STI structure 220 is disposed on thesubstrate 210, and includes theSTI oxide 221. TheSTI oxide 221 is disposed in theSTI structure 220, theSTI oxide 221 can be made of silicon oxide, and a thickness of theSTI oxide 221 can be 600 Å to 2400 Å. - The
memory cell area 230 includes thenitride film 231, thetunnel oxide 232, theFG structure 233, theONO layer 234 and theCG structure 235. Thenitride film 231 is disposed on a surface of theSTI structure 220 and below the surface of thesubstrate 210. Thetunnel oxide 232 is disposed on thesubstrate 210, thetunnel oxide 232 can be made of silicon oxide, and a thickness of thetunnel oxide 232 can be 70 Å to 105 Å. It is worth mentioning that the best thickness of thetunnel oxide 232 is 95 Å, but is not limited thereto. TheFG structure 233 is disposed on thetunnel oxide 232. TheONO layer 234 is disposed on theFG structure 233 and theSTI oxide 221, and theSTI oxide 221 is located between theONO layer 234 and thenitride film 231. TheCG structure 235 is disposed on theONO layer 234, and theONO layer 234 is located between theFG structure 233 and theCG structure 235. Furthermore, a thickness of theFG structure 233 is 1000 Å, a thickness of theONO layer 234 is 65/80/65 Å, and a thickness of theCG structure 235 is 2000 Å, but is not limited thereto. - In detail, the
ONO layer 234 can be made of silicon oxide/silicon nitride/silicon oxide. Also, silicon nitride can be replaced with high-k insulator materials like alumina, zirconia, hafnia, titania or strontium titanate. Hence, theONO layer 234 can also be made of silicon oxide/alumina/silicon oxide, silicon oxide/zirconia/silicon oxide, silicon oxide/hafnia/silicon oxide, silicon oxide/titania/silicon oxide or silicon oxide/strontium titanate/silicon oxide, but is not limited thereto. - The
non-memory cell area 240 is connected to thememory cell area 230, and includes the plurality of peripheral devices. Moreover, thememory cell area 230 is isolated from thenon-memory cell area 240, and a short circuit will not be caused. In detail, the peripheral devices includes a high voltage N-channel (HVN)logic device 241, a low voltage N-channel (LVN)logic device 242, a high voltage P-channel (HVP)logic device 243 and a low voltage P-channel (LVP)logic device 244. - Furthermore, a triple P-well (its reference numeral is omitted) is located on a deep N-well (its reference numeral is omitted) of the
substrate 210 in thememory cell area 230, and a P-well (its reference numeral is omitted) is located beside an N-well (its reference numeral is omitted) of thesubstrate 210 in thenon-memory cell area 240. - Via the FinFET stack gate memory of the present disclosure, an effective memory cell channel width is increased, a further memory cell size scaling can be allowed, and a current of the FinFET stack gate memory can be kept intact.
- The foregoing description, for purpose of explanation, has been described with reference to specific embodiments. It is to be noted that Tables show different data of the different embodiments; however, the data of the different embodiments are obtained from experiments. The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical applications, to thereby enable others skilled in the art to best utilize the disclosure and various embodiments with various modifications as are suited to the particular use contemplated. The embodiments depicted above and the appended drawings are exemplary and are not intended to be exhaustive or to limit the scope of the present disclosure to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings.
Claims (15)
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US16/815,151 US20210143275A1 (en) | 2019-11-11 | 2020-03-11 | Finfet stack gate memory and mehod of forming thereof |
CN202010776012.9A CN112786598A (en) | 2019-11-11 | 2020-08-05 | FinFET stacked gate memory and forming method thereof |
TW109126585A TWI742792B (en) | 2019-11-11 | 2020-08-05 | Finfet stack gate memory and method of forming thereof |
TW110125956A TWI794887B (en) | 2019-11-11 | 2020-08-05 | Finfet stack gate memory |
US17/563,214 US11616145B2 (en) | 2019-11-11 | 2021-12-28 | FINFET stack gate memory and method of forming thereof |
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US7332408B2 (en) * | 2004-06-28 | 2008-02-19 | Micron Technology, Inc. | Isolation trenches for memory devices |
JP2006286788A (en) * | 2005-03-31 | 2006-10-19 | Fujitsu Ltd | Semiconductor apparatus and its manufacturing method |
TWI288966B (en) * | 2005-09-05 | 2007-10-21 | Promos Technologies Inc | Memory structure with high coupling ratio and forming method thereof |
KR100660543B1 (en) * | 2005-10-24 | 2006-12-22 | 삼성전자주식회사 | Nand falsh memory device and method of fabricating the same |
JP2008071827A (en) * | 2006-09-12 | 2008-03-27 | Toshiba Corp | Nonvolatile semiconductor memory and method for manufacturing the same |
JP5076426B2 (en) * | 2006-09-29 | 2012-11-21 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US7642616B2 (en) * | 2007-05-17 | 2010-01-05 | Micron Technology, Inc. | Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device |
US8837216B2 (en) * | 2010-12-13 | 2014-09-16 | Sandisk Technologies Inc. | Non-volatile storage system with shared bit lines connected to a single selection device |
US20130285134A1 (en) * | 2012-04-26 | 2013-10-31 | International Business Machines Corporation | Non-volatile memory device formed with etch stop layer in shallow trench isolation region |
KR102002942B1 (en) * | 2013-04-18 | 2019-07-24 | 에스케이하이닉스 주식회사 | Nonvolatile memory device and method of fabricating the same |
US20150115346A1 (en) * | 2013-10-25 | 2015-04-30 | United Microelectronics Corp. | Semiconductor memory device and method for manufacturing the same |
US10755984B2 (en) | 2015-06-24 | 2020-08-25 | Intel Corporation | Replacement channel etch for high quality interface |
US10510544B2 (en) * | 2016-11-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Non-volatile memory semiconductor device and manufacturing method thereof |
US10192746B1 (en) | 2017-07-31 | 2019-01-29 | Globalfoundries Inc. | STI inner spacer to mitigate SDB loading |
US10937879B2 (en) | 2017-11-30 | 2021-03-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
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