JP4424760B2 - 時間多重相互接続を用いたエミュレーション・システム - Google Patents
時間多重相互接続を用いたエミュレーション・システム Download PDFInfo
- Publication number
- JP4424760B2 JP4424760B2 JP50074799A JP50074799A JP4424760B2 JP 4424760 B2 JP4424760 B2 JP 4424760B2 JP 50074799 A JP50074799 A JP 50074799A JP 50074799 A JP50074799 A JP 50074799A JP 4424760 B2 JP4424760 B2 JP 4424760B2
- Authority
- JP
- Japan
- Prior art keywords
- logic
- emulation system
- signal
- chip
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31717—Interconnect testing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S370/00—Multiplex communications
- Y10S370/916—Multiplexer/demultiplexer
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Time-Division Multiplex Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/865,741 | 1997-05-30 | ||
| US08/865,741 US5960191A (en) | 1997-05-30 | 1997-05-30 | Emulation system with time-multiplexed interconnect |
| PCT/US1998/010171 WO1998054664A1 (en) | 1997-05-30 | 1998-05-18 | Emulation system with time-multiplexed interconnect |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002507294A JP2002507294A (ja) | 2002-03-05 |
| JP2002507294A5 JP2002507294A5 (enExample) | 2005-12-08 |
| JP4424760B2 true JP4424760B2 (ja) | 2010-03-03 |
Family
ID=25346124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50074799A Expired - Fee Related JP4424760B2 (ja) | 1997-05-30 | 1998-05-18 | 時間多重相互接続を用いたエミュレーション・システム |
Country Status (10)
| Country | Link |
|---|---|
| US (4) | US5960191A (enExample) |
| EP (1) | EP0983562B1 (enExample) |
| JP (1) | JP4424760B2 (enExample) |
| KR (1) | KR20010013190A (enExample) |
| AT (1) | ATE225058T1 (enExample) |
| CA (1) | CA2291738A1 (enExample) |
| DE (1) | DE69808286T2 (enExample) |
| IL (1) | IL132983A (enExample) |
| TW (1) | TW440796B (enExample) |
| WO (1) | WO1998054664A1 (enExample) |
Families Citing this family (325)
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| US5801955A (en) * | 1996-05-31 | 1998-09-01 | Mentor Graphics Corporation | Method and apparatus for removing timing hazards in a circuit design |
| US5841967A (en) | 1996-10-17 | 1998-11-24 | Quickturn Design Systems, Inc. | Method and apparatus for design verification using emulation and simulation |
| US5960191A (en) * | 1997-05-30 | 1999-09-28 | Quickturn Design Systems, Inc. | Emulation system with time-multiplexed interconnect |
| US6535505B1 (en) * | 1998-09-30 | 2003-03-18 | Cisco Technology, Inc. | Method and apparatus for providing a time-division multiplexing (TDM) interface among a high-speed data stream and multiple processors |
-
1997
- 1997-05-30 US US08/865,741 patent/US5960191A/en not_active Expired - Lifetime
-
1998
- 1998-05-18 DE DE69808286T patent/DE69808286T2/de not_active Expired - Lifetime
- 1998-05-18 AT AT98923498T patent/ATE225058T1/de not_active IP Right Cessation
- 1998-05-18 KR KR19997011175A patent/KR20010013190A/ko not_active Withdrawn
- 1998-05-18 EP EP98923498A patent/EP0983562B1/en not_active Expired - Lifetime
- 1998-05-18 JP JP50074799A patent/JP4424760B2/ja not_active Expired - Fee Related
- 1998-05-18 IL IL13298398A patent/IL132983A/en not_active IP Right Cessation
- 1998-05-18 CA CA002291738A patent/CA2291738A1/en not_active Abandoned
- 1998-05-18 WO PCT/US1998/010171 patent/WO1998054664A1/en not_active Ceased
- 1998-05-29 TW TW087108460A patent/TW440796B/zh not_active IP Right Cessation
-
1999
- 1999-08-13 US US09/374,444 patent/US6377912B1/en not_active Expired - Lifetime
-
2001
- 2001-08-02 US US09/922,113 patent/US6732068B2/en not_active Expired - Lifetime
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2002
- 2002-04-22 US US10/128,178 patent/US7739097B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| IL132983A0 (en) | 2001-03-19 |
| US20030074178A1 (en) | 2003-04-17 |
| EP0983562B1 (en) | 2002-09-25 |
| KR20010013190A (ko) | 2001-02-26 |
| JP2002507294A (ja) | 2002-03-05 |
| US20020161568A1 (en) | 2002-10-31 |
| DE69808286T2 (de) | 2003-07-31 |
| CA2291738A1 (en) | 1998-12-03 |
| DE69808286D1 (de) | 2002-10-31 |
| TW440796B (en) | 2001-06-16 |
| US7739097B2 (en) | 2010-06-15 |
| ATE225058T1 (de) | 2002-10-15 |
| IL132983A (en) | 2002-07-25 |
| WO1998054664A1 (en) | 1998-12-03 |
| EP0983562A1 (en) | 2000-03-08 |
| US6377912B1 (en) | 2002-04-23 |
| US6732068B2 (en) | 2004-05-04 |
| US5960191A (en) | 1999-09-28 |
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