JP2019009435A - 酸化物半導体層を含む薄膜トランジスタ、その製造方法及び表示装置 - Google Patents
酸化物半導体層を含む薄膜トランジスタ、その製造方法及び表示装置 Download PDFInfo
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- JP2019009435A JP2019009435A JP2018114108A JP2018114108A JP2019009435A JP 2019009435 A JP2019009435 A JP 2019009435A JP 2018114108 A JP2018114108 A JP 2018114108A JP 2018114108 A JP2018114108 A JP 2018114108A JP 2019009435 A JP2019009435 A JP 2019009435A
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- oxide semiconductor
- semiconductor layer
- film transistor
- thin film
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Ceramic Engineering (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
Description
図1に示した構造を有する比較例1〜3の薄膜トランジスタを製造した。
酸化物半導体層120の厚さによる薄膜トランジスタの特性を確認するために、図1に示された構造を有する薄膜トランジスタを製造した(比較例4、実施例1および2)。比較例1の薄膜トランジスタと同じ方法で薄膜トランジスタを製造するが、ただし酸化物半導体層120の組成は異なるようにした。以下、他の説明がない限り、薄膜トランジスタは、図1の構造を有し、比較例1の薄膜トランジスタと同じ方法で製造することができる。
蒸着温度および熱処理温度による酸化物半導体層120の特性を確認するためには、インジウム(In)、ガリウム(Ga)、亜鉛(Zn)およびスズ(Sn)が4:1:4:1の比(原子数比率)で混合して行い、30nmの厚さを有する酸化物半導体層120試料を製造した。ここで、酸化物半導体層120を形成するための蒸着温度と蒸着した後の熱処理温度を表3のように調整して、酸化物半導体層120の試料であるS11、S12、S13、S14、S15、およびS16を製造した。
スズ(Sn)の含有量による酸化物半導体層120の特性を確認するために、4:1:4の比(原子数比率)のインジウム(In)、ガリウム(Ga)、亜鉛(Zn)を含み、インジウム(In)に対するスズ(Sn)の割合(Sn/In)が表4のような酸化物半導体層120および薄膜トランジスタを製造した(S21、S22、S23、S24、およびS25)。表4でインジウム(In)に対するスズ(Sn)の割合(Sn/In)を%で表示した。%で示された割合は、次の式1で求めることができる。
[数1]
Sn/In比率(%)=[(Snの原子数)/(Inの原子数)]x100
101:基板
102:対向基板
110:ゲート電極
120:酸化物半導体層
130:ソース電極
140:ドレイン電極
150:ゲート絶縁膜
151:第1ゲート絶縁膜
152:第2ゲート絶縁膜
180:エッチストッパー
190:平坦化層
191:バッファ層
250:バンク層
270:有機発光素子
271、381:第1電極
272:有機層
273、383:第2電極
341、342:カラーフィルタ
350:遮光部
382:液晶層
700、800:表示装置
Claims (18)
- 基板上に配置されたゲート電極、
前記ゲート電極と絶縁され、前記ゲート電極と少なくとも一部重畳する酸化物半導体層、
前記ゲート電極と前記酸化物半導体層間に配置されたゲート絶縁膜、
前記酸化物半導体層と接続されたソース電極、および
前記ソース電極と離隔され前記酸化物半導体層と接続されたドレイン電極を含み、
前記酸化物半導体層は、インジウム(In)、ガリウム(Ga)、亜鉛(Zn)、スズ(Sn)および酸素(O)を含み、
前記酸化物半導体層では、前記インジウム(In)の含有量は前記ガリウム(Ga)の含有量よりも多く、
前記インジウム(In)と前記亜鉛(Zn)の含有量は実質的に同一であり、
前記インジウム(In)に対する前記のスズ(Sn)の割合(Sn/In)は0.1〜0.25である薄膜トランジスタ。 - 前記酸化物半導体層が、20nm以上の厚さを有する請求項1に記載の薄膜トランジスタ。
- 前記酸化物半導体層が、18cm2/V・s以上の移動度(Mobility)を有する請求項1に記載の薄膜トランジスタ。
- 前記酸化物半導体層が、5x1017個/cm3以上のキャリア濃度を有する請求項1に記載の薄膜トランジスタ。
- 前記酸化物半導体層が、6.5g/cm3以上の密度を有する請求項1に記載の薄膜トランジスタ。
- 前記酸化物半導体層が、2.0x1017spins/cm3以下のスピン密度(spin density)を有する請求項1に記載の薄膜トランジスタ。
- 前記酸化物半導体層が、順次に積層された第1層及び第2層を有し、
前記第2層の酸素(O)の含有量は、前記第1層の酸素(O)の含有量よりも多い請求項1に記載の薄膜トランジスタ。 - 前記第2層が、前記酸化物半導体層の厚さの5〜20%の厚さを有する請求項7に記載の薄膜トランジスタ。
- 前記第2層のうち前記ソース電極及び前記ドレイン電極と重畳しない領域の厚さが、前記ソース電極及び前記ドレイン電極のうち少なくとも一つと重畳する領域の厚さよりも厚い請求項7に記載の薄膜トランジスタ。
- 基板上にゲート電極を形成する工程、
前記ゲート電極と絶縁されて前記ゲート電極と少なくとも一部重畳する酸化物半導体層を形成する工程、
前記ゲート電極と前記酸化物半導体層を相互に絶縁させるゲート絶縁膜を形成する工程、および
前記酸化物半導体層とそれぞれ接続され、互いに離隔して配置されるソース電極およびドレイン電極を形成する工程を含み、
前記酸化物半導体層は、インジウム(In)、ガリウム(Ga)、亜鉛(Zn)、スズ(Sn)および酸素(O)を含み、
前記酸化物半導体層では、前記インジウム(In)の含有量が前記ガリウム(Ga)の含有量よりも多く、
前記インジウム(In)と前記亜鉛(Zn)の含有量は実質的に同一であり、
前記インジウム(In)に対する前記のスズ(Sn)の割合(Sn/In)は0.1〜0.25である、
薄膜トランジスタの製造方法。 - 前記酸化物半導体層が、蒸着によって形成され、
前記蒸着は、150℃以上の温度で行われる請求項10に記載の薄膜トランジスタの製造方法。 - 前記酸化物半導体層が20nm以上の厚さを有する、請求項10に記載の薄膜トランジスタの製造方法。
- 前記酸化物半導体層をプラズマ処理する工程をさらに含む、請求項10に記載の薄膜トランジスタの製造方法。
- 前記プラズマ処理する工程で2.0〜2.5kW/m2のエネルギーが印加される、請求項13に記載の薄膜トランジスタの製造方法。
- 前記酸化物半導体層を形成する工程後、300℃以上の温度で前記酸化物半導体層を熱処理する工程をさらに含む、請求項10に記載の薄膜トランジスタの製造方法。
- 前記基板上に、前記ゲート電極、前記ゲート絶縁膜及び前記酸化物半導体層を順次に形成する、請求項10に記載の薄膜トランジスタの製造方法。
- 前記基板上に、前記酸化物半導体層、前記ゲート絶縁膜及び前記ゲート電極を順次に形成する、請求項10に記載の薄膜トランジスタの製造方法。
- 基板、
前記基板上に配置された薄膜トランジスタ、および
前記薄膜トランジスタと接続された第1電極を含み、
前記薄膜トランジスタは、
前記基板上に配置されたゲート電極、
前記ゲート電極と絶縁されて前記ゲート電極と少なくとも一部重畳する酸化物半導体層、
前記ゲート電極と前記酸化物半導体層間に配置されたゲート絶縁膜、
前記酸化物半導体層と接続されたソース電極、および
前記ソース電極と離隔され前記酸化物半導体層と接続されたドレイン電極を含み、
前記酸化物半導体層は、インジウム(In)、ガリウム(Ga)、亜鉛(Zn)、スズ(Sn)および酸素(O)を含み、
前記酸化物半導体層では、前記インジウム(In)の含有量が前記ガリウム(Ga)の含有量よりも多く、
前記インジウム(In)と前記亜鉛(Zn)の含有量は実質的に同一であり、
前記インジウム(In)に対する前記のスズ(Sn)の割合(Sn/In)は0.1〜0.25である
表示装置。
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US20180374956A1 (en) | 2018-12-27 |
CN109148592B (zh) | 2022-03-11 |
JP6599518B2 (ja) | 2019-10-30 |
CN109148592A (zh) | 2019-01-04 |
EP3422419A1 (en) | 2019-01-02 |
US20220069130A1 (en) | 2022-03-03 |
US10608117B2 (en) | 2020-03-31 |
EP3422419B1 (en) | 2020-08-26 |
US20200185531A1 (en) | 2020-06-11 |
TW201906173A (zh) | 2019-02-01 |
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US11201248B2 (en) | 2021-12-14 |
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