JP2015070223A - 薄膜半導体装置及びその製造方法 - Google Patents
薄膜半導体装置及びその製造方法 Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
Description
本発明者らは、従来の薄膜半導体装置に関し、以下の問題が生じることを見出した。
本開示に係る薄膜半導体装置は、基板と、基板の上方に形成されたゲート電極と、ゲート電極に対向するように基板の上方に形成された酸化物半導体層と、酸化物半導体層上に形成された第1絶縁層と、酸化物半導体層に接続されたソース電極及びドレイン電極とを備え、酸化物半導体層の酸素欠陥の状態密度DOS[eV−1cm−3]は、酸化物半導体層の伝導帯端のエネルギー準位をEc[eV]とし、酸化物半導体層の所定のエネルギー準位をE[eV]としたとき、2.0eV≦Ec−E≦2.7eVにおいて、DOS≦1.710×1017×(Ec−E)2−6.468×1017×(Ec−E)+6.113×1017を満たす。
[有機EL表示装置]
まず、本実施の形態に係る有機EL表示装置10の構成について、図4を用いて説明する。図4は、本実施の形態に係る有機EL表示装置の一部切り欠き斜視図である。
以下では、本実施の形態に係る薄膜半導体装置について説明する。なお、本実施の形態に係る薄膜半導体装置は、ボトムゲート型、かつ、チャネル保護型の薄膜トランジスタである。
続いて、本実施の形態に係る薄膜半導体装置の製造方法について、図7を用いて説明する。図7は、本実施の形態に係る薄膜半導体装置の製造方法を示す概略断面図である。
まず、酸化物半導体層140の酸素欠陥の状態密度の測定方法について説明する。
続いて、本実施の形態の薄膜半導体装置100による閾値電圧の低下の抑制効果について、図10A〜図11を用いて説明する。
続いて、本実施の形態の薄膜半導体装置100による移動度ピークの抑制効果について、図12を用いて説明する。
次に、実施の形態2について説明する。なお、本実施の形態に係る有機EL表示装置の構成は、実施の形態1に係る有機EL表示装置10の構成と同様であるので、その説明は省略し、薄膜半導体装置について説明する。
以下では、本実施の形態に係る薄膜半導体装置について説明する。なお、本実施の形態に係る薄膜半導体装置は、ボトムゲート型、かつ、チャネルエッチ型の薄膜トランジスタである。
続いて、本実施の形態に係る薄膜半導体装置の製造方法について、図15を用いて説明する。図15は、本実施の形態に係る薄膜半導体装置の製造方法を示す概略断面図である。
次に、実施の形態3について説明する。なお、本実施の形態に係る有機EL表示装置の構成は、実施の形態1に係る有機EL表示装置10の構成と同様であるので、その説明は省略し、薄膜半導体装置について説明する。
以下では、本実施の形態に係る薄膜半導体装置について説明する。なお、本実施の形態に係る薄膜半導体装置は、トップゲート型の薄膜トランジスタである。
続いて、本実施の形態に係る薄膜半導体装置の製造方法について、図17を用いて説明する。図17は、本実施の形態に係る薄膜半導体装置の製造方法を示す概略断面図である。
以上のように、本出願において開示する技術の例示として、実施の形態1〜3を説明した。しかしながら、本開示における技術は、これらに限定されず、適宜、変更、置き換え、付加、省略などを行った実施の形態にも適用可能である。
20 TFT基板
30 画素
31 画素回路
32、33 薄膜トランジスタ
32d、33d、160d、260d、360d ドレイン電極
32g、33g、120、320、420 ゲート電極
32s、33s、160s、260s、360s ソース電極
34 キャパシタ
40 有機EL素子
41 陽極
42 EL層
43 陰極
50 ゲート配線
60 ソース配線
70 電源配線
100、200、300 薄膜半導体装置
110、410 基板
130、330、430 ゲート絶縁膜
140、240、340、440 酸化物半導体層
140a、240a、340a 酸化物半導体膜
141、241、341 酸素リッチ層
150、250、450 チャネル保護層
170 プラズマ
350 絶縁層
Claims (16)
- 基板と、
前記基板の上方に形成されたゲート電極と、
前記ゲート電極に対向するように前記基板の上方に形成された酸化物半導体層と、
前記酸化物半導体層上に形成された第1絶縁層と、
前記酸化物半導体層に接続されたソース電極及びドレイン電極とを備え、
前記酸化物半導体層の酸素欠陥の状態密度DOS[eV−1cm−3]は、
前記酸化物半導体層の伝導帯端のエネルギー準位をEc[eV]とし、前記酸化物半導体層の所定のエネルギー準位をE[eV]としたとき、
2.0eV≦Ec−E≦2.7eVにおいて、DOS≦1.710×1017×(Ec−E)2−6.468×1017×(Ec−E)+6.113×1017
を満たす
薄膜半導体装置。 - 前記状態密度DOS[eV−1cm−3]は、さらに、
2.0eV≦Ec−E≦2.7eVにおいて、DOS≦1.332×1010×(Ec−E)14.65
を満たす
請求項1に記載の薄膜半導体装置。 - 前記薄膜半導体装置は、さらに、前記ゲート電極上に形成された第2絶縁層を備え、
前記酸化物半導体層は、前記第2絶縁層上に形成され、
前記第1絶縁層には、前記酸化物半導体層の一部を露出させるためのコンタクトホールが形成され、
前記ソース電極及び前記ドレイン電極は、前記第1絶縁層上に形成され、前記コンタクトホールを介して前記酸化物半導体層に接続される
請求項1又は2に記載の薄膜半導体装置。 - 前記薄膜半導体装置は、さらに、前記ゲート電極上に形成された第2絶縁層を備え、
前記酸化物半導体層は、前記第2絶縁層上に形成され、
前記ソース電極及び前記ドレイン電極は、前記酸化物半導体層上に形成され、
前記第1絶縁層は、前記ソース電極、前記ドレイン電極及び前記酸化物半導体層上に形成される
請求項1又は2に記載の薄膜半導体装置。 - 前記ゲート電極は、前記第1絶縁層上に形成される
請求項1又は2に記載の薄膜半導体装置。 - 前記酸化物半導体層は、透明アモルファス酸化物半導体である
請求項1〜5のいずれか1項に記載の薄膜半導体装置。 - 基板の上方にゲート電極を形成する工程と、
前記基板の上方、かつ、前記ゲート電極に対向する位置に酸化物半導体層を形成する工程と、
前記酸化物半導体層に、酸素を含むガスを用いたプラズマ処理を行う工程と、
前記酸化物半導体層上に第1絶縁層を形成する工程と、
前記酸化物半導体層に接続されたソース電極及びドレイン電極を形成する工程とを含み、
前記プラズマ処理を行う工程では、
前記酸化物半導体層の酸素欠陥の状態密度DOS[eV−1cm−3]が、
前記酸化物半導体層の伝導帯端のエネルギー準位をEc[eV]とし、前記酸化物半導体層の所定のエネルギー準位をE[eV]としたとき、
2.0eV≦Ec−E≦2.7eVにおいて、DOS≦1.710×1017×(Ec−E)2−6.468×1017×(Ec−E)+6.113×1017
を満たすような所定の条件で前記プラズマ処理を行う
薄膜半導体装置の製造方法。 - 前記ガスは、亜酸化窒素を含むガスであり、
前記プラズマ処理のパワー密度は、1[W/cm2]以下である
請求項7に記載の薄膜半導体装置の製造方法。 - 前記プラズマ処理のパワー密度は、0.2[W/cm2]以上である
請求項8に記載の薄膜半導体装置の製造方法。 - 前記ガスは、亜酸化窒素を含むガスであり、
前記プラズマ処理を行う工程では、2.0[Torr]以上の圧力下で前記プラズマ処理を行う
請求項7〜9のいずれか1項に記載の薄膜半導体装置の製造方法。 - 前記薄膜半導体装置の製造方法は、さらに、前記ゲート電極上に第2絶縁層を形成する工程を含み、
前記酸化物半導体層を形成する工程では、前記第2絶縁層上に前記酸化物半導体層を形成し、
前記第1絶縁層を形成する工程では、前記酸化物半導体層の一部が露出するように前記第1絶縁層を形成し、
前記ソース電極及び前記ドレイン電極を形成する工程では、前記露出した部分で前記酸化物半導体層に接続されるように前記ソース電極及び前記ドレイン電極を形成する
請求項7〜10のいずれか1項に記載の薄膜半導体装置の製造方法。 - 前記薄膜半導体装置の製造方法は、さらに、前記ゲート電極上に第2絶縁層を形成する工程を含み、
前記酸化物半導体層を形成する工程では、前記第2絶縁層上に前記酸化物半導体層を形成し、
前記ソース電極及び前記ドレイン電極を形成する工程では、前記酸化物半導体層上に前記ソース電極及び前記ドレイン電極を形成し、
前記第1絶縁層を形成する工程では、前記ソース電極、前記ドレイン電極及び前記酸化物半導体層上に前記第1絶縁層を形成する
請求項7〜10のいずれか1項に記載の薄膜半導体装置の製造方法。 - 前記プラズマ処理を行う工程は、前記ソース電極及び前記ドレイン電極を形成する工程の前に行う
請求項12に記載の薄膜半導体装置の製造方法。 - 前記ゲート電極を形成する工程では、前記第1絶縁層上に前記ゲート電極を形成する
請求項7〜10のいずれか1項に記載の薄膜半導体装置の製造方法。 - 前記プラズマ処理を行う工程は、前記第1絶縁層を形成する工程の前に行う
請求項7〜14のいずれか1項に記載の薄膜半導体装置の製造方法。 - 前記酸化物半導体層は、透明アモルファス酸化物半導体である
請求項7〜15のいずれか1項に記載の薄膜半導体装置の製造方法。
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