JP2016181717A - マルチ窪みのシャロートレンチアイソレーションを有する集積回路 - Google Patents
マルチ窪みのシャロートレンチアイソレーションを有する集積回路 Download PDFInfo
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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Abstract
【解決手段】基板上に第一パターンを有するフォトレジスト層形成し、それをマスクとして第一深さを有する第一STI構造を形成し、第二パターンを有する第二フォトレジスト層を形成し、それをマスクとして第二深さを有する第二STI構造を形成し、
前記第二フォトレジスト層を除去し、第三パターンを有する第三フォトレジスト層形成し、第三STI構造を形成する。その後、基板を平坦化する。
【選択図】図3b
Description
Claims (10)
- シャロートレンチアイソレーション(STI)構造を形成する方法であって、
第一平坦部分と第二平坦部分とを有し、第一平坦部分は第二平坦部分から分離しており、横方向に移動している基板の上表面に、第一フォトレジスト層を設け、
前記基板の上表面の前記第一平坦部分を露出させる複数の第一開口を有する第一パターンで前記第一フォトレジスト層をパターニングし、
前記第一フォトレジスト層を第一マスクとして用い、前記基板の前記上表面から前記基板の内部に第一深さにエッチングすることで複数の第一STI構造を形成し、
前記基板の前記上表面に前記第一フォトレジスト層とは異なる第二フォトレジスト層を設け、
前記複数の第一STI構造のいずれの1つも露出させないで前記基板の前記上表面の第二平坦部分を露出させる複数の第二開口を有する第二パターンで前記第二フォトレジスト層をパターニングし、
前記第二フォトレジスト層を第二マスクとして用い、前記基板の前記上表面から前記基板の内部に第二深さにエッチングすることで複数の第二STI構造を形成し、前記複数の第二STI構造の各々は、前記第二パターン内の第二開口の異なる一つに対応し、前記複数の第一STI構造の各々は、分離しており、前記複数の第二STI構造の各々から横方向にスペースが開けられており、
前記基板を平坦化する
ことを特徴とするSTI構造を形成する方法。 - 前記第一深さと前記第二深さとは、異なる深さである請求項1記載の方法。
- 前記第二フォトレジスト層を設ける前に、前記基板を平坦化する請求項1記載の方法。
- 前記第一フォトレジスト層を設ける前に、前記基板上にハードマスクを設け、前記第一フォトレジスト層を前記第一パターンにパターニングする工程が、前記第一開口を有する第一パターンに前記ハードマスクをパターニングすることを含む請求項1記載の方法。
- シャロートレンチアイソレーション(STI)構造を形成する方法であって、
基板上に第一フォトレジスト層を設け、
前記第一フォトレジスト層をパターニングして第一パターンを形成し、
前記第一フォトレジスト層を第一マスクとして用い、前記基板の内部にエッチングすることで第一深さを有する第一STI構造を形成し、
前記第一フォトレジスト層を除去し、
前記基板上に第二フォトレジスト層を設け、
前記第二フォトレジスト層をパターニングして第二パターンを形成し、
前記第二フォトレジスト層を第二マスクとして用い、前記基板の内部にエッチングすることで第二深さを有する第二STI構造を形成し、
前記第二フォトレジスト層を除去し、
前記基板上に第三フォトレジスト層を設け、
前記第三フォトレジスト層をパターニングして第三パターンを形成し、
前記第三フォトレジスト層を第三マスクとして用い、前記基板の内部にエッチングすることで、第三深さを有する第三STI構造を形成し、
前記第三フォトレジスト層を除去し、
前記基板を平坦化する方法。 - 前記基板内に前記第一STI構造を形成した後で、前記第二フォトレジスト層を前記基板上に設ける前に、前記基板を平坦化する請求項5記載の方法。
- 前記第一深さ、前記第二深さおよび前記第三深さは、異なる深さである請求項5記載の方法。
- シャロートレンチアイソレーション(STI)構造を形成する方法であって、
基板上に第一フォトレジスト層を設け、
前記第一フォトレジスト層をパターニングして第一パターンを形成し、
前記第一フォトレジスト層を第一マスクとして用い、前記基板の内部にエッチングすることで第一深さを有する全てのSTI構造を形成し、
前記基板上に第二フォトレジスト層を設け、
前記第二フォトレジスト層をパターニングして第二パターンを形成し、
前記パターン化された前記第二フォトレジスト層を第二マスクとして用い、エッチングすることで前記STI構造の第二深さを有する第一サブセットを形成し、
前記基板上に第三フォトレジスト層を設け、
前記第三フォトレジスト層をパターニングして第三パターンを形成し、
前記パターン化された前記第3のフォトレジスト層を第三マスクとして用い、エッチングすることで、前記STI構造の第三深さを有する第二サブセットを形成し、
前記基板を平坦化する方法。 - 前記第一深さ、前記第二深さおよび前記第三深さは、異なる深さである請求項8記載の方法。
- 前記STI構造の全てを酸化物充填物で充填する工程をさらに有する請求項8記載の方法。
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US25235109P | 2009-10-16 | 2009-10-16 | |
US61/252,351 | 2009-10-16 | ||
US12/838,264 US8610240B2 (en) | 2009-10-16 | 2010-07-16 | Integrated circuit with multi recessed shallow trench isolation |
US12/838,264 | 2010-07-16 |
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JP2016119322A Pending JP2016181717A (ja) | 2009-10-16 | 2016-06-15 | マルチ窪みのシャロートレンチアイソレーションを有する集積回路 |
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Also Published As
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US8610240B2 (en) | 2013-12-17 |
KR20110041993A (ko) | 2011-04-22 |
US20110089526A1 (en) | 2011-04-21 |
TWI415214B (zh) | 2013-11-11 |
JP2011086945A (ja) | 2011-04-28 |
US20130267075A1 (en) | 2013-10-10 |
US8846465B2 (en) | 2014-09-30 |
CN102044470A (zh) | 2011-05-04 |
TW201115682A (en) | 2011-05-01 |
JP2014112738A (ja) | 2014-06-19 |
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