JP2013229587A - 半導体装置、及び当該半導体装置を有する電子機器 - Google Patents
半導体装置、及び当該半導体装置を有する電子機器 Download PDFInfo
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- JP2013229587A JP2013229587A JP2013065395A JP2013065395A JP2013229587A JP 2013229587 A JP2013229587 A JP 2013229587A JP 2013065395 A JP2013065395 A JP 2013065395A JP 2013065395 A JP2013065395 A JP 2013065395A JP 2013229587 A JP2013229587 A JP 2013229587A
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- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium atom Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 description 1
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- 230000007704 transition Effects 0.000 description 1
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- 229910052724 xenon Inorganic materials 0.000 description 1
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- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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Abstract
【解決手段】半導体装置として、酸化物半導体膜をチャネル形成領域として含むトランジスタにおいて、チャネル形成領域に接して酸素放出型の酸化物絶縁膜を形成し、該酸化物絶縁膜より酸化物半導体膜に酸素を供給する。また、チャネル形成領域の外周には酸素バリア膜を形成することで、トランジスタに接続された配線、及び電極等への酸素の拡散を抑制することができる。
【選択図】図1
Description
本実施の形態では、半導体装置の一形態を、図1乃至図4を用いて説明する。本実施の形態では、半導体装置の一例として積層型の半導体装置の断面図を示す。
本実施の形態では、実施の形態1に示す半導体装置と異なる形態であり、より詳細な構成について図5を用いて説明し、その後、図6乃至図11を用いて図5に示した半導体装置の作製方法について説明する。
本実施の形態では、実施の形態2の図5に示す半導体装置を使用し、電力が供給されない状況でも記憶内容の保持が可能で、且つ書き込み回数にも制限が無い半導体装置の回路構成の一例について説明する。
本実施の形態では、実施の形態2で示した半導体装置及び実施の形態3で示した回路構成を用い、複数の回路により構成された記憶処理装置について、図13を用いて説明を行う。
本実施の形態では、本発明の一態様の半導体装置を記憶回路に適用し、記憶回路の一例であるCPUの構成について説明する。
本実施の形態においては、本発明の一態様に係る半導体装置を用いることで、消費電力の低い電子機器について説明を行う。
104 ソース領域
106 ドレイン領域
108 第1のチャネル形成領域
110 第1のゲート絶縁膜
112 第1のゲート電極
114 層間絶縁膜
115 酸素バリア膜
116 酸化物絶縁膜
117 バックゲート電極
118 酸素バリア膜
120 酸化物半導体膜
120a 第2のチャネル形成領域
121 酸化物半導体膜
121a 第2のチャネル形成領域
122 ソース電極
123 酸素バリア膜
124 ドレイン電極
126 第2のゲート絶縁膜
127 第2のゲート絶縁膜
128 第2のゲート電極
129 第2のゲート電極
150 第1のトランジスタ
152 第2のトランジスタ
160 第1のトランジスタ
162 第2のトランジスタ
170 第1のトランジスタ
172 第2のトランジスタ
180 第1のトランジスタ
182 第2のトランジスタ
202 半導体基板
204 素子分離領域
206 pウェル領域
208a 第1のゲート絶縁膜
208b 第1のゲート絶縁膜
210a 第1のゲート電極
210b 第1のゲート電極
212 第1のチャネル形成領域
212a ソース領域
212b ドレイン領域
214 第1のチャネル形成領域
214a ソース領域
214b ドレイン領域
216 絶縁膜
218 絶縁膜
220a コンタクトプラグ
220b コンタクトプラグ
220c コンタクトプラグ
220d コンタクトプラグ
222a 絶縁膜
222d 絶縁膜
224a 配線
224c 配線
226a 絶縁膜
226b 絶縁膜
228 コンタクトプラグ
232 配線
234a 絶縁膜
234b 絶縁膜
236 酸素バリア膜
238 酸化物絶縁膜
240 酸化物半導体膜
240a 第2のチャネル形成領域
242 酸素バリア膜
242a 酸素バリア膜
242b 酸素バリア膜
242c 酸素バリア膜
242d 酸素バリア膜
244a 電極
244b ソース電極
244c ドレイン電極
246 第2のゲート絶縁膜
248a 電極
248b 第2のゲート電極
250 絶縁膜
252 絶縁膜
254 電極
256a 絶縁膜
256b 絶縁膜
258 配線
260 絶縁膜
280a 第1のp型トランジスタ
280b 第1のn型トランジスタ
280c 第1のn型トランジスタ
281 容量素子
282 第2のトランジスタ
350 記憶処理装置
351 演算回路
352 演算回路
353 記憶回路
354 記憶回路
355 記憶回路
356 制御回路
357 電源制御回路
901 RF回路
902 アナログベースバンド回路
903 デジタルベースバンド回路
904 バッテリー
905 電源回路
906 アプリケーションプロセッサ
907 CPU
908 DSP
910 フラッシュメモリ
911 ディスプレイコントローラ
912 メモリ回路
913 ディスプレイ
914 表示部
915 ソースドライバ
916 ゲートドライバ
917 音声回路
918 キーボード
919 タッチセンサ
1001 バッテリー
1002 電源回路
1003 マイクロプロセッサ
1004 フラッシュメモリ
1005 音声回路
1006 キーボード
1007 メモリ回路
1008 タッチパネル
1009 ディスプレイ
1010 ディスプレイコントローラ
1011 CPU
1012 DSP
1013 インターフェース
9900 基板
9901 ALU
9902 ALU・Controller
9903 Instruction・Decoder
9904 Interrupt・Controller
9905 Timing・Controller
9906 Register
9907 Register・Controller
9908 Bus・I/F
9909 ROM
9920 ROM・I/F
Claims (10)
- 第1の半導体材料により形成された第1のチャネル形成領域を含む第1のトランジスタと、
前記第1のトランジスタの上方に設けられ、第2の半導体材料により形成された第2のチャネル形成領域を含む第2のトランジスタと、
前記第1のトランジスタと前記第2のトランジスタの間に設けられた酸化物絶縁膜と、を有し、
前記酸化物絶縁膜は、少なくとも前記第2のチャネル形成領域と接して設けられ、
前記第2のチャネル形成領域の外周に、前記酸化物絶縁膜を貫通する酸素バリア膜を有する
ことを特徴とする半導体装置。 - 第1の半導体材料により形成された第1のチャネル形成領域と、
前記第1のチャネル形成領域上に形成された第1のゲート絶縁膜と、
前記第1のゲート絶縁膜と接し、前記第1のチャネル形成領域と重畳する位置に形成された第1のゲート電極と、
前記第1のチャネル形成領域を挟むように形成されたソース領域及びドレイン領域と、を含む第1のトランジスタと、
第2の半導体材料により形成された第2のチャネル形成領域と、
前記第2のチャネル形成領域上に形成された第2のゲート絶縁膜と、
前記第2のゲート絶縁膜と接し、前記第2のチャネル形成領域と重畳する位置に形成された第2のゲート電極と、
前記第2のチャネル形成領域と電気的に接続されたソース電極及びドレイン電極と、
を含む第2のトランジスタと、
前記第1のトランジスタと前記第2のトランジスタの間に設けられた酸化物絶縁膜と、を有し、
前記酸化物絶縁膜は、少なくとも前記第2のチャネル形成領域と接して設けられ、
前記第2のチャネル形成領域の外周に、前記酸化物絶縁膜を貫通する酸素バリア膜を有する
ことを特徴とする半導体装置。 - 請求項1または請求項2において、
さらに、前記第2のトランジスタと同一平面上に設けられた容量素子を、有する
ことを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記酸化物絶縁膜を貫通して、前記第1のトランジスタと前記第2のトランジスタを電気的に接続する接続電極を、有する
ことを特徴とする半導体装置。 - 請求項4において、
前記接続電極は、前記酸素バリア膜と接して設けられる
ことを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記酸素バリア膜は、アルミニウム、ルテニウム、イリジウム、ハフニウム、及びタンタルの中から選ばれた金属膜、金属酸化膜、または金属窒化膜である
ことを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記第1の半導体材料は、シリコンを含む材料である
ことを特徴とする半導体装置。 - 請求項1乃至請求項7のいずれか一において、
前記第2の半導体材料は、酸化物半導体である
ことを特徴とする半導体装置。 - 請求項8において、
前記酸化物半導体膜は、少なくともインジウムまたは亜鉛を含む
ことを特徴とする半導体装置。 - 請求項1乃至請求項9のいずれか一に記載の半導体装置を有する電子機器。
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Cited By (9)
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WO2015097589A1 (en) * | 2013-12-26 | 2015-07-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP2015179839A (ja) * | 2014-02-28 | 2015-10-08 | 株式会社半導体エネルギー研究所 | 半導体装置、該半導体装置を有する表示装置、該表示装置を有する表示モジュール、並びに該半導体装置、該表示装置、及び該表示モジュールを有する電子機器 |
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US10249766B2 (en) | 2019-04-02 |
JP2017103474A (ja) | 2017-06-08 |
JP2018117158A (ja) | 2018-07-26 |
US9349849B2 (en) | 2016-05-24 |
US20130299818A1 (en) | 2013-11-14 |
JP6081838B2 (ja) | 2017-02-15 |
JP2020039004A (ja) | 2020-03-12 |
JP6630394B2 (ja) | 2020-01-15 |
US20160240685A1 (en) | 2016-08-18 |
JP6330065B2 (ja) | 2018-05-23 |
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