JP2013145901A - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】半導体基板と、半導体基板上に形成された第1の導電膜パターンと、第1の導電膜パターン上に形成された絶縁膜と、絶縁膜上に形成された第2の導電膜パターンと、第2の導電膜パターン及び絶縁膜全面に形成され、半導体基板に輻射される紫外線を遮断する第1の紫外線遮断膜と、第1の紫外線遮断膜上に形成された金属間絶縁膜と、金属間絶縁膜上に形成された第3の導電膜パターンと、第3の導電膜パターン及び金属間絶縁膜全面に形成され、半導体基板に輻射される紫外線を遮断する第2の紫外線遮断膜と、を含む。これにより、半導体基板に紫外線が輻射されることを遮断して外部イオン及び水分が半導体基板に浸透することを遮断でき、半導体集積回路装置の動作特性を向上させうる。
【選択図】図2
Description
幅/長さが25μm/4μmであるNMOS高電圧駆動トランジスタとPMOS高電圧駆動トランジスタをそれぞれ42個ずつ製造した後、それぞれ11個ずつ(N1〜N11、P1〜P11)は、第1の配線上に260ÅのSiON膜を形成し、それぞれ25個ずつ(N12〜N36、P12〜P36)は、第1の配線上に600ÅのSiON膜を形成し、それぞれ6個ずつ(N37〜N42、P37〜P42)は第1の配線上にSiON膜を形成しなかった。
120 Pウェル
130 Nウェル
200 NMOS高電圧駆動トランジスタ
210 ゲート絶縁膜
220 ゲート電極
230 ソース領域
232 低濃度不純物領域
234 高濃度不純物領域
240 ドレーン領域
300 PMOS高電圧駆動トランジスタ
410 層間絶縁膜
423 コンタクト
430 第1の配線
440 第1の紫外線遮断膜
450 第1の金属間絶縁膜
463 第1のビア
470 第2の配線
480 第2の金属間絶縁膜
493 第2のビア
495 第3の配線
496 保護膜
Claims (12)
- 第1の不純物を含む半導体基板と、
前記半導体基板上に形成された第1の導電膜パターンと、
前記第1の導電膜パターン上に形成された層間絶縁膜と、
前記層間絶縁膜上に形成された第2の導電膜パターンと、
前記第2の導電膜パターン及び前記層間絶縁膜全面に形成され、前記半導体基板に輻射される紫外線を遮断する第1の紫外線遮断膜と、
前記第1の紫外線遮断膜上にプラズマ蒸着工程によって形成された金属間絶縁膜と、
前記金属間絶縁膜上に形成された第3の導電膜パターンと、
前記第3の導電膜パターン及び前記金属間絶縁膜全面に形成され、前記半導体基板に輻射される紫外線を遮断する第2の紫外線遮断膜と、
を含むことを特徴とする半導体集積回路装置。 - 前記第1の紫外線遮断膜下部に形成された第1の酸化膜をさらに含むことを特徴とする請求項1に記載の半導体集積回路装置。
- 前記第1の紫外線遮断膜は、シリコン酸化物よりバンドギャップが小さい物質から構成されることを特徴とする請求項1又は請求項2に記載の半導体集積回路装置。
- 前記第1の紫外線遮断膜は、窒化膜を含むことを特徴とする請求項3に記載の半導体集積回路装置。
- 前記第1の紫外線遮断膜は、SiN膜又はSiON膜であることを特徴とする請求項4に記載の半導体集積回路装置。
- 前記第1の導電膜パターンは、高電圧駆動トランジスタのゲート電極であることを特徴とする請求項1又は請求項2に記載の半導体集積回路装置。
- 前記高電圧駆動トランジスタは、第2の不純物を含む低濃度不純物領域と高濃度不純物領域とを含むことソース/ドレーン領域を含み、前記低濃度不純物領域は、前記ゲート電極に整列されて前記半導体基板内に形成され、前記半導体基板と異なる導電型を有し、前記高濃度不純物領域は、前記ゲート電極から所定距離離隔され、前記低濃度不純物領域の深さより低い深さに形成され、前記半導体基板と異なる導電型を有することを特徴とする請求項6に記載の半導体集積回路装置。
- 前記第1の不純物の不純物濃度は、1×1015〜1×1017原子/cm3であることを特徴とする請求項7に記載の半導体集積回路装置。
- 前記第2の不純物の不純物濃度は、1×1014〜1×1016原子/cm3であることを特徴とする請求項7に記載の半導体集積回路装置。
- 前記金属間絶縁膜は、順次に形成された第1及び第2の絶縁膜を含み、前記第1の絶縁膜は前記第2の絶縁膜よりギャップフィル特性に優れたことを特徴とする請求項1に記載の半導体集積回路装置。
- 前記第2の紫外線遮断膜下部に形成された第2の酸化膜をさらに含むことを特徴とする請求項1に記載の半導体集積回路装置。
- 前記第2の紫外線遮断膜は、シリコン酸化物よりバンドギャップが小さい物質から構成されることを特徴とする請求項1に記載の半導体集積回路装置。
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KR10-2005-0049016 | 2005-06-08 | ||
KR1020050049016A KR100703971B1 (ko) | 2005-06-08 | 2005-06-08 | 반도체 집적 회로 장치 및 그 제조 방법 |
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JP2013037641A Pending JP2013145901A (ja) | 2005-06-08 | 2013-02-27 | 半導体集積回路装置 |
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US (3) | US7304387B2 (ja) |
JP (2) | JP2006344956A (ja) |
KR (1) | KR100703971B1 (ja) |
CN (1) | CN1877834B (ja) |
DE (1) | DE102006024654A1 (ja) |
TW (1) | TWI302377B (ja) |
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JP3833189B2 (ja) * | 2003-05-27 | 2006-10-11 | 株式会社リコー | 半導体装置及びその製造方法 |
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2005
- 2005-06-08 KR KR1020050049016A patent/KR100703971B1/ko active IP Right Grant
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2006
- 2006-05-05 US US11/429,370 patent/US7304387B2/en active Active
- 2006-05-22 DE DE102006024654A patent/DE102006024654A1/de not_active Ceased
- 2006-06-05 JP JP2006156332A patent/JP2006344956A/ja not_active Withdrawn
- 2006-06-06 CN CN2006100916013A patent/CN1877834B/zh active Active
- 2006-06-08 TW TW095120308A patent/TWI302377B/zh active
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2007
- 2007-10-23 US US11/977,039 patent/US8058185B2/en active Active
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2011
- 2011-10-13 US US13/272,675 patent/US20120032269A1/en not_active Abandoned
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2013
- 2013-02-27 JP JP2013037641A patent/JP2013145901A/ja active Pending
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Also Published As
Publication number | Publication date |
---|---|
US8058185B2 (en) | 2011-11-15 |
KR20060127687A (ko) | 2006-12-13 |
CN1877834A (zh) | 2006-12-13 |
US20120032269A1 (en) | 2012-02-09 |
US20080057689A1 (en) | 2008-03-06 |
TWI302377B (en) | 2008-10-21 |
CN1877834B (zh) | 2010-09-29 |
DE102006024654A1 (de) | 2007-02-01 |
US7304387B2 (en) | 2007-12-04 |
KR100703971B1 (ko) | 2007-04-06 |
US20060278949A1 (en) | 2006-12-14 |
TW200721451A (en) | 2007-06-01 |
JP2006344956A (ja) | 2006-12-21 |
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