JP2012256408A - 半導体記憶装置およびその駆動方法 - Google Patents
半導体記憶装置およびその駆動方法 Download PDFInfo
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- JP2012256408A JP2012256408A JP2012100730A JP2012100730A JP2012256408A JP 2012256408 A JP2012256408 A JP 2012256408A JP 2012100730 A JP2012100730 A JP 2012100730A JP 2012100730 A JP2012100730 A JP 2012100730A JP 2012256408 A JP2012256408 A JP 2012256408A
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Classifications
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- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
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- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
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- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
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Abstract
【解決手段】酸化物半導体を用いた第1のトランジスタ、および第1のキャパシタからなるメモリセルをマトリクス状に有するメモリセルアレイと、pチャネル型である第3のトランジスタ、第2のキャパシタおよび酸化物半導体を用いた第2のトランジスタを有する参照セル、ならびに抵抗素子およびコンパレータを有するリフレッシュタイミング検出回路と、を有するメモリモジュールにおいて、第1のトランジスタを介して第1のキャパシタに電位が与えられると第2のトランジスタを介して第2のキャパシタに電位が与えられ、第2のキャパシタの電位に応じて第3のトランジスタのドレイン電流値が変化し、第3のトランジスタのドレイン電流値が任意の値より大きくなると、メモリセルアレイおよび参照セルのリフレッシュ動作を行う。
【選択図】図1
Description
本実施の形態では、本発明の一態様を適用した半導体記憶装置について説明する。
上式の両辺をVgで割り、更に両辺の対数を取ると、以下のようになる。
本実施の形態では、実施の形態1に示したメモリモジュール100とは異なる構造のメモリモジュール200について図2を用いて説明する。
本実施の形態では、実施の形態1および実施の形態2に示したメモリモジュール100およびメモリモジュール200とは異なる構造のメモリモジュール300について図3を用いて説明する。
実施の形態1乃至実施の形態3で示した半導体記憶装置を少なくとも一部に用いてCPU(Central Processing Unit)を構成することができる。
本実施の形態では、実施の形態1乃至実施の形態4の少なくともいずれかを適用した電子機器の例について説明する。
110 ローデコーダ
112 カラムデコーダ
116 コンパレータ
118 抵抗素子
130 第1のキャパシタ
132 第2のキャパシタ
140 第1のトランジスタ
142 第2のトランジスタ
144 第3のトランジスタ
150 メモリセル
152 参照セル
160 ビット線
170 ワード線
180 メモリセルアレイ
190 比較回路
200 メモリモジュール
201 基板
202 下地絶縁膜
203 下地絶縁膜
204 低抵抗領域
206 高抵抗領域
207 高抵抗領域
208 ゲート絶縁膜
209 ゲート絶縁膜
210 ゲート電極
211 ゲート電極
212 層間絶縁膜
213 層間絶縁膜
214 電極
280 メモリセルアレイ
282 参照セル群
300 メモリモジュール
352 参照セル
500 基板
502 下地絶縁膜
504 保護絶縁膜
506 酸化物半導体膜
506a 高抵抗領域
506b 低抵抗領域
508 ゲート絶縁膜
510 ゲート電極
512 側壁絶縁膜
514 電極
516 層間絶縁膜
518 配線
600 基板
602 下地絶縁膜
606 酸化物半導体膜
608 ゲート絶縁膜
610 ゲート電極
614 電極
616 層間絶縁膜
618 配線
620 保護膜
1010 下地絶縁膜
1020 埋め込み絶縁物
1030a 半導体領域
1030b 半導体領域
1030c 半導体領域
1040 ゲート絶縁膜
1050 ゲート
1060a 側壁絶縁物
1060b 側壁絶縁物
1070 絶縁物
1080a ソース
1080b ドレイン
1141 スイッチング素子
1142 半導体記憶装置
1143 半導体記憶装置群
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
9300 筐体
9301 ボタン
9302 マイクロフォン
9303 表示部
9304 スピーカ
9305 カメラ
9320 筐体
9321 ボタン
9322 マイクロフォン
9323 表示部
Claims (12)
- 酸化物半導体を用いた第1のトランジスタ、および第1のキャパシタからなり、前記第1のトランジスタを介して前記第1のキャパシタに電位が与えられるメモリセルをマトリクス状に有するメモリセルアレイと、
第2のキャパシタおよび酸化物半導体を用いた第2のトランジスタを有し、前記第2のトランジスタを介して前記第2のキャパシタに電位が与えられる参照セルと、コンパレータと、を有するリフレッシュタイミング検出回路と、を有し、
少なくともメモリセルの1つがリフレッシュタイミング検出回路に接続する半導体記憶装置。 - 請求項1において、
前記リフレッシュタイミング検出回路は、前記第2のキャパシタの一対の電極の一方が抵抗素子の一対の電極の一方および前記コンパレータの一対の電極の一方と接続され、前記第2のキャパシタの一対の電極の他方および前記抵抗素子の一対の電極の他方が接地され、前記第2のトランジスタのソースが参照ビット線と接続され、前記第1のトランジスタのゲートが参照ワード線と接続されることを特徴とする半導体記憶装置。 - 酸化物半導体を用いた第1のトランジスタ、および第1のキャパシタからなり、前記第1のトランジスタを介して前記第1のキャパシタに電位が与えられるメモリセルをマトリクス状に有するメモリセルアレイと、
pチャネル型である第3のトランジスタ、第2のキャパシタおよび酸化物半導体を用いた第2のトランジスタを有し、前記第2のトランジスタを介して前記第2のキャパシタおよび前記第3のトランジスタのゲートに電位が与えられる参照セルと、抵抗素子およびコンパレータと、を有するリフレッシュタイミング検出回路と、を有する半導体記憶装置。 - 請求項3において、
前記リフレッシュタイミング検出回路は、前記第3のトランジスタのゲートが前記第2のトランジスタのドレインおよび前記第2のキャパシタの一対の電極の一方と接続され、前記第3のトランジスタのソースがハイレベルの電源電位と接続され、前記第3のトランジスタのドレインが前記抵抗素子の一対の電極の一方および前記コンパレータの一対の電極の一方と接続され、前記第2のキャパシタの一対の電極の他方および前記抵抗素子の一対の電極の他方が接地され、前記第2のトランジスタのソースが参照ビット線と接続され、前記第1のトランジスタのゲートが参照ワード線と接続されることを特徴とする半導体記憶装置。 - 請求項1乃至請求項4のいずれか一において、
前記メモリセルは、前記第1のトランジスタのドレインと前記第1のキャパシタの一対の電極の一方が接続され、前記第1のキャパシタの一対の電極の他方が接地され、前記第1のトランジスタのソースがビット線と接続され、前記第1のトランジスタのゲートがワード線と接続されることを特徴とする半導体記憶装置。 - 請求項2または請求項4において、
前記参照ビット線は、前記ビット線と共通化されることを特徴とする半導体記憶装置。 - 請求項2、請求項4または請求項6において、
前記参照ワード線は、前記ワード線と共通化されることを特徴とする半導体記憶装置。 - 請求項1乃至請求項7のいずれか一において、
前記第1のトランジスタおよび前記第2のトランジスタが同一の構成であることを特徴とする半導体記憶装置。 - 請求項1乃至請求項8のいずれか一において、
前記第2のキャパシタの保持容量は前記第1のキャパシタの保持容量よりも小さいことを特徴とする半導体記憶装置。 - 請求項1乃至請求項9のいずれか一において、
前記リフレッシュタイミング検出回路において、前記参照セルを複数設けることを特徴とする半導体記憶装置。 - 酸化物半導体を用いた第1のトランジスタ、および第1のキャパシタからなり、前記第1のトランジスタを介して前記第1のキャパシタに電位が与えられるメモリセルをマトリクス状に有するメモリセルアレイと、
pチャネル型である第3のトランジスタ、第2のキャパシタおよび酸化物半導体を用いた第2のトランジスタを有し、前記第2のトランジスタを介して前記第2のキャパシタおよび前記第3のトランジスタのゲートに電位が与えられる参照セルと、
抵抗素子およびコンパレータを有するリフレッシュタイミング検出回路と、を有し、
前記第2のキャパシタに保持される電位に応じて前記第3のトランジスタのドレイン電流値が変化し、
前記第3のトランジスタの前記ドレイン電流値が任意の値より大きくなると、前記メモリセルアレイおよび前記参照セルのリフレッシュ動作を行うことを特徴とする半導体記憶装置の駆動方法。 - 酸化物半導体を用いた第1のトランジスタ、および第1のキャパシタからなり、前記第1のトランジスタを介して前記第1のキャパシタに電位が与えられるメモリセルをマトリクス状に有するメモリセルアレイと、
第2のキャパシタおよび酸化物半導体を用いた第2のトランジスタを有し、前記第2のトランジスタを介して前記第2のキャパシタに電位が与えられる参照セルと、
コンパレータを有するリフレッシュタイミング検出回路と、を有し、
前記第2のキャパシタに保持される電位が任意の値より低くなると、前記メモリセルアレイおよび前記参照セルのリフレッシュ動作を行うことを特徴とする半導体記憶装置の駆動方法。
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US9406370B2 (en) | 2014-05-29 | 2016-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Memory device, and semiconductor device and electronic appliance including the same |
US9715920B2 (en) | 2014-05-29 | 2017-07-25 | Semiconductor Energy Laboratory Co., Ltd. | Memory device, and semiconductor device and electronic appliance including the same |
JP2017139047A (ja) * | 2016-01-28 | 2017-08-10 | 株式会社半導体エネルギー研究所 | 半導体装置の動作方法 |
US11961916B2 (en) | 2018-08-09 | 2024-04-16 | Semiconductor Energy Laboratory Co., Ltd. | Memory device |
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JP6375404B2 (ja) | 2018-08-15 |
KR20120122913A (ko) | 2012-11-07 |
JP2017162538A (ja) | 2017-09-14 |
US20120275214A1 (en) | 2012-11-01 |
US20150213842A1 (en) | 2015-07-30 |
KR101963457B1 (ko) | 2019-03-28 |
JP6114504B2 (ja) | 2017-04-12 |
US9443563B2 (en) | 2016-09-13 |
US9001563B2 (en) | 2015-04-07 |
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