JP2012119048A - 半導体メモリ装置およびその駆動方法 - Google Patents
半導体メモリ装置およびその駆動方法 Download PDFInfo
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- JP2012119048A JP2012119048A JP2011213630A JP2011213630A JP2012119048A JP 2012119048 A JP2012119048 A JP 2012119048A JP 2011213630 A JP2011213630 A JP 2011213630A JP 2011213630 A JP2011213630 A JP 2011213630A JP 2012119048 A JP2012119048 A JP 2012119048A
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- bit line
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Abstract
【解決手段】1つのビット線MBL_mに複数個のセルを接続させる。各セルはサブビット線SBL_n_mと4乃至64個のメモリセル(CL_n_m_1、等)を有する。さらに各セルは選択トランジスタSTr1_n_mとSTr2_n_mを有し、また、選択トランジスタSTr2_n_mには相補型インバータ等の増幅回路AMP_n_mを接続する。サブビット線SBL_n_mの寄生容量は十分に小さいため、各メモリセルの容量素子の電荷による電位変動を増幅回路AMP_n_mでエラーなく増幅でき、ビット線に出力できる。
【選択図】図1
Description
本実施の形態では、図1に示す半導体メモリ装置およびその動作の例について、図2乃至図5を用いて説明する。なお、電位として、以下に具体的な数値を挙げるが、それは、本発明の技術思想の理解を助けることが目的である。言うまでもなく、それらの値はトランジスタや容量素子のさまざまな特性によって、あるいは実施者の都合によって変更される。また、本実施の形態に示される半導体メモリ装置は、以下の方法以外の方法によっても、データを書き込み、あるいは読み出すことができる。
本発明の技術思想の一部にしたがった半導体メモリ装置の作製方法の例について図6乃至図8を用いて説明する。なお、図6乃至図8は半導体メモリ装置の一断面を作製工程を追って説明するためのものであるが、特定の部分の断面を示すものではない。
本実施の形態では、図10に示す半導体メモリ装置およびその動作の例について説明する。図10には半導体メモリ装置の第n行第m列のセルと第n行第(m+1)列のセルと、第m列および第(m+1)列のドライバー回路の一部を示す。
本実施の形態では、図10に示す半導体メモリ装置と同様な半導体メモリ装置のレイアウト例および作製工程例を図12および図13を用いて説明する。図12には第n行第m列のセルと第n行第(m+1)列のセルの主要な配線等の各層ごとのレイアウト例を示す。本実施の形態の半導体メモリ装置は、これらを積層して形成される。
本実施の形態では、図14に示す半導体メモリ装置について説明する。図14には半導体メモリ装置の第n行第m列のセルと第n行第(m+1)列のセルと、第m列および第(m+1)列のドライバー回路の一部を示す。
当初、フリップフロップ回路FF_m/m+1の電源電位は、高電位側、低電位側とも+0.5Vとする。まず、第1の列ドライバー線RL1と第1選択線SL1_nの電位をHとし、第1の列トランジスタCTr1_mおよびCTr_m+1、第1の選択トランジスタSTr1_n_mおよびSTr1_n_m+1をオンとする。
次に、ワード線WL_n_1の電位をHとする。第n行第m列のセルには、ワード線WL_n_1と接続するトランジスタを有するメモリセルがあるため、このトランジスタがオンとなり、容量素子に蓄積されていた電荷が放出されてサブビット線SBL_n_mの電位が変動する。
そして、第2選択線SL2b_nの電位をHとして、第2の選択トランジスタSTr2_n_m+1をオンとする。このとき、第2選択線SL2a_nの電位はLのままとする。その結果、ビット線MBL_m+1の電位のみ当初の0.5Vから変動する。ビット線MBL_mの電位は+0.5Vのままである。なお、第(m+1)列のセルのデータを読み出す際には、第2選択線SL2b_nの電位はLのまま、第2選択線SL2a_nの電位をHとすればよい。
そして、第2の列ドライバー線RL2の電位をHとし、第2の列トランジスタCTr2_mおよびCTr2_m+1をオンとする。さらに、フリップフロップ回路FF_m/m+1の電源電位は、高電位側を+1V、低電位側を0Vとする。この結果、フリップフロップ回路FF_m/m+1が動作し、電位の高いビット線MBL_mの電位は+1Vに、電位の低いビット線MBL_m+1の電位は0Vとなる。その結果、ビット線MBL_mの電位が第m列のデータ入出力端子DATA_mに出力される。
本実施の形態では、図14に示す半導体メモリ装置と同様な半導体メモリ装置のレイアウト例および断面構造例を図15乃至図17を用いて説明する。図15および図16には第n行第m列のセルとこれに隣接するセルの主要な配線等の各層ごとのレイアウト例を示す。本実施の形態の半導体メモリ装置は、これらを積層して形成される。なお、本実施の形態で示す半導体メモリ装置の詳細については他の実施の形態を参酌することができる。
102 素子分離絶縁物
103N N型不純物領域
103P P型不純物領域
104N ゲート
104P ゲート
105 第1層間絶縁物
106a 第1コンタクトプラグ
106b 第1コンタクトプラグ
106c 第1コンタクトプラグ
106d 第1コンタクトプラグ
107 第1埋め込み絶縁物
108a 第1層配線
108b 第1層配線
108c 第1層配線
108d 第1層配線
109 第2層間絶縁物
110a 第2コンタクトプラグ
110b 第2コンタクトプラグ
111 第2埋め込み絶縁物
112a 第2層配線
112b 第2層配線
112c 第2層配線
112d 第2層配線
112e 第2層配線
112f 第2層配線
112g 第2層配線
113 容量素子用絶縁物
114a 酸化物半導体層
114b 酸化物半導体層
115 ゲート絶縁物
116a ワード線
116b ワード線
116c ワード線
116d ワード線
117 第3層間絶縁物
118a 第3コンタクトプラグ
118b 第3コンタクトプラグ
119 第6埋め込み絶縁物
120 第6層配線
201 基板
202 素子分離絶縁物
203 N型不純物領域
204a 第1層配線
204b 第1層配線
204c 第1層配線
204d 第1層配線
205 第1層間絶縁物
206a 第1コンタクトプラグ
206b 第1コンタクトプラグ
206c 第1コンタクトプラグ
206d 第1コンタクトプラグ
207 第1埋め込み絶縁物
208a 第2層配線
208b 第2層配線
208c 第2層配線
208d 第2層配線
208e 第2層配線
209 第2層間絶縁物
210a 第2コンタクトプラグ
210b 第2コンタクトプラグ
210c 第2コンタクトプラグ
210d 第2コンタクトプラグ
211 第2埋め込み絶縁物
212a 第3層配線
212b 第3層配線
212c 第3層配線
212d 第3層配線
212e 第3層配線
212f 第3層配線
212g 第3層配線
213 容量素子用絶縁物
214a 酸化物半導体層
214b 酸化物半導体層
215 ゲート絶縁物
216a ワード線
216b ワード線
216c ワード線
216d ワード線
216e ワード線
216f ワード線
217 第3層間絶縁物
218a 第3コンタクトプラグ
218b 第3コンタクトプラグ
218c 第3コンタクトプラグ
218d 第3コンタクトプラグ
301 基板
302 素子分離絶縁物
303N N型不純物領域
303P P型不純物領域
304a 第1層配線
304b 第1層配線
304c 第1層配線
304d 第1層配線
304e 第1層配線
304f 第1層配線
304g 第1層配線
304h 第1層配線
305 第1層間絶縁物
306 第1コンタクトプラグ
307 第1埋め込み絶縁物
308a 第2層配線
308b 第2層配線
308c 第2層配線
308d 第2層配線
308e 第2層配線
308f 第2層配線
309 第2層間絶縁物
310 第2コンタクトプラグ
311 第2埋め込み絶縁物
312a 第3層配線
312b 第3層配線
313 第3層間絶縁物
314 第3コンタクトプラグ
315 第3埋め込み絶縁物
316a 第4層配線
316b 第4層配線
317 容量素子用絶縁物
318 酸化物半導体層
319 ゲート絶縁物
320 ワード線
321 第4層間絶縁物
322 第4コンタクトプラグ
AMP 増幅回路
CMOS 相補型インバータ
CS 寄生容量
CTr1 第1の列トランジスタ
CTr2 第2の列トランジスタ
CTr3 第3の列トランジスタ
DATA データ入出力端子
FF フリップフロップ回路
MBL ビット線
NMOS Nチャネル型トランジスタ
PMOS Pチャネル型トランジスタ
RL1 第1の列ドライバー線
RL2 第2の列ドライバー線
RL3 第3の列ドライバー線
SBL サブビット線
SL1 第1選択線
SL2 第2選択線
SL2a 第2選択線
SL2b 第2選択線
STr1 第1の選択トランジスタ
STr2 第2の選択トランジスタ
WL ワード線
Claims (9)
- 1以上のビット線と4以上のワード線と2以上のセルを有し、前記セルは、2以上のメモリセルと、サブビット線と第1の選択トランジスタと第2の選択トランジスタと増幅回路を有し、前記第1の選択トランジスタのドレインは第1のビット線に接続し、前記第1の選択トランジスタのソースと前記増幅回路の第1の端子は前記サブビット線に接続し、前記増幅回路の第2の端子は前記第2の選択トランジスタのソースに接続し、前記第2の選択トランジスタのドレインもしくは前記増幅回路の第3の端子は、前記第1のビット線あるいは他のビット線に接続し、メモリセルは1以上のトランジスタと1以上の容量素子を有し、容量素子の容量は1fF以下であり、前記メモリセルのトランジスタの一のゲートとドレインとソースは、それぞれ、前記ワード線の一と前記サブビット線と前記容量素子の電極の一に接続することを特徴とする半導体メモリ装置。
- 1以上のビット線と4以上のワード線とワード線と平行な1以上の第1選択線とワード線と平行な1以上の第2選択線と2以上のセルを有し、前記セルは、2以上のメモリセルと、サブビット線と第1の選択トランジスタと第2の選択トランジスタと増幅回路を有し、前記第1の選択トランジスタのドレインは第1のビット線に接続し、前記第1の選択トランジスタのゲートと前記第2の選択トランジスタのゲートは、それぞれ、前記第1選択線の一と前記第2選択線の一に接続し、前記第1の選択トランジスタのソースと前記増幅回路の第1の端子は前記サブビット線に接続し、前記増幅回路の第2の端子は第2の選択トランジスタのソースに接続し、前記第2の選択トランジスタのドレインもしくは前記増幅回路の第3の端子は、前記第1のビット線あるいは他のビット線に接続し、メモリセルは1以上のトランジスタと1以上の容量素子を有し、容量素子の容量は1fF以下であり、前記メモリセルのトランジスタの一のゲートは前記ワード線の一に接続することを特徴とする半導体メモリ装置。
- 請求項1および2のいずれか一において、前記第1の選択トランジスタと前記メモリセルの一のトランジスタの一は異なる層に設けられていることを特徴とする半導体メモリ装置。
- 請求項1乃至3のいずれか一において、前記第1の選択トランジスタに用いられる半導体と前記メモリセルの一のトランジスタに用いられる半導体は異なる種類であることを特徴とする半導体メモリ装置。
- 請求項1乃至4のいずれか一において、前記メモリセルの一のトランジスタの一と他のメモリセルのトランジスタの一は異なる層に設けられていることを特徴とする半導体メモリ装置。
- 請求項1乃至5のいずれか一において、前記増幅回路は相補型インバータであることを特徴とする半導体メモリ装置。
- 請求項1乃至6のいずれか一において、前記セルは4乃至64のメモリセルを有することを特徴とする半導体メモリ装置。
- 請求項1乃至7のいずれか一において、前記容量素子は必要な深さあるいは高さが1μm以下であることを特徴とする半導体メモリ装置。
- 1以上のビット線と4以上のワード線と2以上のセルを有し、前記セルは、2以上のメモリセルと、サブビット線と第1の選択トランジスタと第2の選択トランジスタと増幅回路を有し、前記第1の選択トランジスタのドレインは前記ビット線の一に接続し、前記第1の選択トランジスタのソースと前記増幅回路の第1の端子は前記サブビット線に接続し、前記増幅回路の第2の端子は前記第2の選択トランジスタのソースに接続し、メモリセルは1以上のトランジスタと1以上の容量素子を有し、容量素子の容量は1fF以下であり、前記メモリセルのトランジスタの一のゲートとドレインとソースは、それぞれ、前記ワード線の一と前記サブビット線と前記容量素子の電極の一に接続する半導体メモリ装置において、前記第1の選択トランジスタをオンとすることにより前記サブビット線の電位を特定の電位とする第1の過程と、前記メモリセルの一のトランジスタの一をオンとする第2の過程と、を有することを特徴とする半導体メモリ装置の駆動方法。
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2011
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- 2011-09-15 KR KR1020110092885A patent/KR101911004B1/ko active IP Right Grant
- 2011-09-20 US US13/236,965 patent/US8837202B2/en not_active Expired - Fee Related
- 2011-09-29 JP JP2011213630A patent/JP5789465B2/ja not_active Expired - Fee Related
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JP2012138160A (ja) * | 2010-10-05 | 2012-07-19 | Semiconductor Energy Lab Co Ltd | 半導体メモリ装置およびその駆動方法 |
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JP2013122809A (ja) * | 2011-11-09 | 2013-06-20 | Semiconductor Energy Lab Co Ltd | 半導体メモリ装置およびその駆動方法 |
JP2015041388A (ja) * | 2013-08-20 | 2015-03-02 | 株式会社半導体エネルギー研究所 | 記憶装置、及び半導体装置 |
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JP2022125146A (ja) * | 2014-05-30 | 2022-08-26 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP7337233B2 (ja) | 2014-05-30 | 2023-09-01 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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JP7462575B2 (ja) | 2019-01-25 | 2024-04-05 | 株式会社半導体エネルギー研究所 | 半導体装置 |
Also Published As
Publication number | Publication date |
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US20120075917A1 (en) | 2012-03-29 |
JP5789465B2 (ja) | 2015-10-07 |
US8837202B2 (en) | 2014-09-16 |
TWI574259B (zh) | 2017-03-11 |
US20160284711A1 (en) | 2016-09-29 |
KR101911004B1 (ko) | 2018-10-23 |
US9825042B2 (en) | 2017-11-21 |
US9384816B2 (en) | 2016-07-05 |
KR20120033244A (ko) | 2012-04-06 |
US20140369111A1 (en) | 2014-12-18 |
TW201225080A (en) | 2012-06-16 |
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