JP2011171718A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2011171718A JP2011171718A JP2011003557A JP2011003557A JP2011171718A JP 2011171718 A JP2011171718 A JP 2011171718A JP 2011003557 A JP2011003557 A JP 2011003557A JP 2011003557 A JP2011003557 A JP 2011003557A JP 2011171718 A JP2011171718 A JP 2011171718A
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- Prior art keywords
- transistor
- insulating layer
- electrode
- channel formation
- drain electrode
- Prior art date
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Images
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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Abstract
【解決手段】基板または基板上に設けられた第1のトランジスタと、第1のトランジスタよりも上に設けられた第2のトランジスタを有する半導体装置において、第1のトランジスタと第2のトランジスタの少なくとも一部を重畳させ、第1のトランジスタのゲート電極と、第2のトランジスタのソース電極またはドレイン電極を電気的に接続させる。第1のトランジスタとしてはシリコン単結晶により設けられたものが好ましく、第2のトランジスタとしてはオフ電流が極端に小さい酸化物半導体により設けられたものが好ましい。
【選択図】図6
Description
102 保護層
104 半導体領域
106 素子分離絶縁層
108a ゲート絶縁層
110 ゲート電極
112 絶縁膜
114 不純物領域
116 チャネル形成領域
118 サイドウォール絶縁層
120 高濃度不純物領域
122 金属膜
124 金属化合物領域
125 層間絶縁層
126 層間絶縁層
128 層間絶縁層
141a 絶縁層
141b 絶縁層
142a ソース電極またはドレイン電極
142b ソース電極またはドレイン電極
143a 絶縁層
143b 絶縁層
144 酸化物半導体層
146 ゲート絶縁層
148a ゲート電極
148b 電極
150 層間絶縁層
151 開口
152 層間絶縁層
154 ソース電極またはドレイン電極
160 トランジスタ
162 トランジスタ
164 容量素子
500 ベース基板
502 窒素含有層
510 単結晶半導体基板
512 酸化膜
514 脆化領域
516 単結晶半導体層
518 単結晶半導体層
520 半導体層
522 絶縁層
522a ゲート絶縁層
524 ゲート電極
526 不純物領域
528 サイドウォール絶縁層
530 高濃度不純物領域
532 低濃度不純物領域
534 チャネル形成領域
536 層間絶縁層
538 層間絶縁層
570 トランジスタ
901 筐体
902 筐体
903 表示部
904 キーボード
911 本体
912 スタイラス
913 表示部
914 操作ボタン
915 外部インターフェイス
920 電子書籍
921 筐体
923 筐体
925 表示部
927 表示部
931 電源
933 操作キー
935 スピーカー
937 軸部
940 筐体
941 筐体
942 表示パネル
943 スピーカー
944 マイクロフォン
945 操作キー
946 ポインティングデバイス
947 カメラ用レンズ
948 外部接続端子
949 太陽電池セル
950 外部メモリスロット
961 本体
963 接眼部
964 操作スイッチ
965 表示部
966 バッテリー
967 表示部
970 テレビジョン装置
971 筐体
973 表示部
975 スタンド
980 リモコン操作機
1100 記憶素子
1111 第1の駆動回路
1112 第2の駆動回路
1113 第3の駆動回路
1114 第4の駆動回路
Claims (10)
- 第1のトランジスタと第2のトランジスタを有する半導体装置であって、
前記第1のトランジスタは、
第1の半導体材料が用いられた第1のチャネル形成領域と、
前記第1のチャネル形成領域を挟んで設けられた不純物領域と、
前記第1のチャネル形成領域上に設けられた第1のゲート絶縁層と、
少なくとも前記第1のチャネル形成領域と重畳して前記第1のゲート絶縁層上に設けられた第1のゲート電極と、
前記不純物領域と電気的に接続された第1のソース電極及び第1のドレイン電極と、を含み、
前記第2のトランジスタは、
第2のソース電極及び第2のドレイン電極と、
第2の半導体材料が用いられ、前記第2のソース電極及び前記第2のドレイン電極と電気的に接続された第2のチャネル形成領域と、
前記第2のチャネル形成領域上に設けられた第2のゲート絶縁層と、
少なくとも前記第2のチャネル形成領域と重畳して前記第2のゲート絶縁層上に設けられた第2のゲート電極と、を含み、
前記第1のトランジスタと前記第2のトランジスタは、少なくとも一部が重畳して設けられ、
前記第2のソース電極及び前記第2のドレイン電極の一方は、前記第1のゲート電極と電気的に接続して設けられ、
前記第2のソース電極及び前記第2のドレイン電極の他方は、前記第1のゲート電極から離間して設けられていることを特徴とする半導体装置。 - 第1のトランジスタと、第2のトランジスタと、容量素子と、を有する半導体装置であって、
前記第1のトランジスタは、
第1の半導体材料が用いられた第1のチャネル形成領域と、
前記第1のチャネル形成領域を挟んで設けられた不純物領域と、
前記第1のチャネル形成領域上に設けられた第1のゲート絶縁層と、
少なくとも前記第1のチャネル形成領域と重畳して前記第1のゲート絶縁層上に設けられた第1のゲート電極と、
前記不純物領域と電気的に接続された第1のソース電極及び第1のドレイン電極と、を含み、
前記第2のトランジスタは、
第2のソース電極及び第2のドレイン電極と、
第2の半導体材料が用いられ、前記第2のソース電極及び前記第2のドレイン電極と電気的に接続された第2のチャネル形成領域と、
前記第2のチャネル形成領域上に設けられた第2のゲート絶縁層と、
少なくとも前記第2のチャネル形成領域と重畳して前記第2のゲート絶縁層上に設けられた第2のゲート電極と、を含み、
前記容量素子は、
前記第2のソース電極または第2のドレイン電極の一方と、
前記第2のゲート絶縁層と、
前記第2のゲート絶縁層上に設けられた容量素子用電極と、を含み、
前記第1のトランジスタと前記第2のトランジスタは、少なくとも一部が重畳して設けられ、
前記第2のソース電極及び前記第2のドレイン電極の一方は、前記第1のゲート電極と電気的に接続して設けられ、
前記第2のソース電極及び前記第2のドレイン電極の他方は、前記第1のゲート電極から離間して設けられていることを特徴とする半導体装置。 - 第1のトランジスタと、第2のトランジスタと、容量素子と、を有する半導体装置であって、
前記第1のトランジスタは、
第1の半導体材料が用いられた第1のチャネル形成領域と、
前記第1のチャネル形成領域を挟んで設けられた不純物領域と、
前記第1のチャネル形成領域上に設けられた第1のゲート絶縁層と、
少なくとも前記第1のチャネル形成領域と重畳して前記第1のゲート絶縁層上に設けられた第1のゲート電極と、
前記不純物領域と電気的に接続された第1のソース電極及び第1のドレイン電極と、を含み、
前記第2のトランジスタは、
第2のソース電極及び第2のドレイン電極と、
第2の半導体材料が用いられ、前記第2のソース電極及び前記第2のドレイン電極と電気的に接続された第2のチャネル形成領域と、
前記第2のチャネル形成領域上に設けられた第2のゲート絶縁層と、
少なくとも前記第2のチャネル形成領域と重畳して前記第2のゲート絶縁層上に設けられた第2のゲート電極と、を含み、
前記容量素子は、
前記第2のソース電極または第2のドレイン電極の一方と、
前記第2のチャネル形成領域を一部に含む酸化物半導体層と、
前記第2のゲート絶縁層と、
前記第2のゲート絶縁層上に設けられた容量素子用電極と、を含み、
前記第1のトランジスタと前記第2のトランジスタは、少なくとも一部が重畳して設けられ、
前記第2のソース電極及び前記第2のドレイン電極の一方は、前記第1のゲート電極と電気的に接続して設けられ、
前記第2のソース電極及び前記第2のドレイン電極の他方は、前記第1のゲート電極から離間して設けられていることを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記第1の半導体材料と前記第2の半導体材料が異なることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
前記第2の半導体材料は、酸化物半導体であることを特徴とする半導体装置。 - 請求項5において、
前記第1のトランジスタと前記第2のトランジスタの間には複数の絶縁層を有し、
前記複数の絶縁層のうち、少なくとも第2のトランジスタに接する絶縁層が、スパッタリング法により形成されていることを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一において、
前記第2の半導体材料のエネルギーギャップは3eVより大きいことを特徴とする半導体装置。 - 請求項1乃至請求項7のいずれか一において、
前記第1のトランジスタは、前記第2のトランジスタよりも高速動作が可能であることを特徴とする半導体装置。 - 請求項1乃至請求項8のいずれか一において、
前記第2のトランジスタのオフ電流は、前記第1のトランジスタのオフ電流よりも小さいことを特徴とする半導体装置。 - 請求項9において、
前記第2のトランジスタの室温におけるオフ電流は、10zA以下であることを特徴とする半導体装置。
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WO2011096277A1 (en) | 2010-02-05 | 2011-08-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of driving semiconductor device |
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CN106847816A (zh) | 2010-02-05 | 2017-06-13 | 株式会社半导体能源研究所 | 半导体装置 |
KR101822962B1 (ko) | 2010-02-05 | 2018-01-31 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
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JP2016131260A (ja) | 2016-07-21 |
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