JP2009529784A - 集積回路の限界寸法を制御するトリム工程 - Google Patents

集積回路の限界寸法を制御するトリム工程 Download PDF

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Publication number
JP2009529784A
JP2009529784A JP2008558345A JP2008558345A JP2009529784A JP 2009529784 A JP2009529784 A JP 2009529784A JP 2008558345 A JP2008558345 A JP 2008558345A JP 2008558345 A JP2008558345 A JP 2008558345A JP 2009529784 A JP2009529784 A JP 2009529784A
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Prior art keywords
hard mask
mask layer
layer
trimming
etching
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Pending
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JP2008558345A
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Japanese (ja)
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JP2009529784A5 (enExample
Inventor
ケー． アベチェフ，マーザファー
ムラーリ サブラマニアン，クルパカー
ザオ，バオスゥオ
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マイクロン テクノロジー， インク．
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Publication of JP2009529784A publication Critical patent/JP2009529784A/ja
Publication of JP2009529784A5 publication Critical patent/JP2009529784A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
JP2008558345A 2006-03-09 2007-03-05 集積回路の限界寸法を制御するトリム工程 Pending JP2009529784A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/372,825 US7662718B2 (en) 2006-03-09 2006-03-09 Trim process for critical dimension control for integrated circuits
PCT/US2007/005639 WO2007103343A1 (en) 2006-03-09 2007-03-05 Trim process for critical dimension control for integrated circuits

Publications (2)

Publication Number Publication Date
JP2009529784A true JP2009529784A (ja) 2009-08-20
JP2009529784A5 JP2009529784A5 (enExample) 2010-04-15

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JP2008558345A Pending JP2009529784A (ja) 2006-03-09 2007-03-05 集積回路の限界寸法を制御するトリム工程

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US (2) US7662718B2 (enExample)
EP (1) EP2002465A1 (enExample)
JP (1) JP2009529784A (enExample)
KR (1) KR20080112281A (enExample)
CN (1) CN101421824B (enExample)
WO (1) WO2007103343A1 (enExample)

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JP2010003757A (ja) * 2008-06-18 2010-01-07 Fujitsu Microelectronics Ltd 半導体装置の製造方法
CN102478764A (zh) * 2010-11-30 2012-05-30 中芯国际集成电路制造(北京)有限公司 双重图形化方法
JP2013089827A (ja) * 2011-10-20 2013-05-13 Fujitsu Semiconductor Ltd 半導体装置の製造方法
JP2014507795A (ja) * 2010-12-27 2014-03-27 ブルーワー サイエンス アイ エヌ シー． 高度なパターン形成に必要な小型フィーチャのパターン形成プロセス
JP2014157956A (ja) * 2013-02-18 2014-08-28 Mitsubishi Electric Corp 炭化珪素半導体装置の製造方法
US9177809B2 (en) 2013-07-03 2015-11-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
KR20160030378A (ko) * 2014-09-09 2016-03-17 도쿄엘렉트론가부시키가이샤 서브-해상도 스케일들로 상이한 임계 치수들을 패터닝하기 위한 방법
US9779952B2 (en) 2013-08-27 2017-10-03 Tokyo Electron Limited Method for laterally trimming a hardmask

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US7910483B2 (en) 2011-03-22
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