JP2009529784A - 集積回路の限界寸法を制御するトリム工程 - Google Patents

集積回路の限界寸法を制御するトリム工程 Download PDF

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Publication number
JP2009529784A
JP2009529784A JP2008558345A JP2008558345A JP2009529784A JP 2009529784 A JP2009529784 A JP 2009529784A JP 2008558345 A JP2008558345 A JP 2008558345A JP 2008558345 A JP2008558345 A JP 2008558345A JP 2009529784 A JP2009529784 A JP 2009529784A
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Prior art keywords
hard mask
mask layer
layer
trimming
etching
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Japanese (ja)
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JP2009529784A5 (enExample
Inventor
ケー． アベチェフ，マーザファー
ムラーリ サブラマニアン，クルパカー
ザオ，バオスゥオ
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マイクロン テクノロジー， インク．
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H10P50/242—
    • H10P50/695—
    • H10P50/696—
    • H10P50/71—
    • H10P50/73—
    • H10P76/20—
    • H10P76/4085—
    • H10P76/4088—

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
JP2008558345A 2006-03-09 2007-03-05 集積回路の限界寸法を制御するトリム工程 Pending JP2009529784A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/372,825 US7662718B2 (en) 2006-03-09 2006-03-09 Trim process for critical dimension control for integrated circuits
PCT/US2007/005639 WO2007103343A1 (en) 2006-03-09 2007-03-05 Trim process for critical dimension control for integrated circuits

Publications (2)

Publication Number Publication Date
JP2009529784A true JP2009529784A (ja) 2009-08-20
JP2009529784A5 JP2009529784A5 (enExample) 2010-04-15

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JP2008558345A Pending JP2009529784A (ja) 2006-03-09 2007-03-05 集積回路の限界寸法を制御するトリム工程

Country Status (6)

Country Link
US (2) US7662718B2 (enExample)
EP (1) EP2002465A1 (enExample)
JP (1) JP2009529784A (enExample)
KR (1) KR20080112281A (enExample)
CN (1) CN101421824B (enExample)
WO (1) WO2007103343A1 (enExample)

Cited By (8)

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JP2010003757A (ja) * 2008-06-18 2010-01-07 Fujitsu Microelectronics Ltd 半導体装置の製造方法
CN102478764A (zh) * 2010-11-30 2012-05-30 中芯国际集成电路制造(北京)有限公司 双重图形化方法
JP2013089827A (ja) * 2011-10-20 2013-05-13 Fujitsu Semiconductor Ltd 半導体装置の製造方法
JP2014507795A (ja) * 2010-12-27 2014-03-27 ブルーワー サイエンス アイ エヌ シー． 高度なパターン形成に必要な小型フィーチャのパターン形成プロセス
JP2014157956A (ja) * 2013-02-18 2014-08-28 Mitsubishi Electric Corp 炭化珪素半導体装置の製造方法
US9177809B2 (en) 2013-07-03 2015-11-03 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
KR20160030378A (ko) * 2014-09-09 2016-03-17 도쿄엘렉트론가부시키가이샤 서브-해상도 스케일들로 상이한 임계 치수들을 패터닝하기 위한 방법
US9779952B2 (en) 2013-08-27 2017-10-03 Tokyo Electron Limited Method for laterally trimming a hardmask

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US7533068B2 (en) 2004-12-23 2009-05-12 D-Wave Systems, Inc. Analog processor comprising quantum devices
JP2007081383A (ja) * 2005-08-15 2007-03-29 Fujitsu Ltd 微細構造の製造方法
US7662718B2 (en) * 2006-03-09 2010-02-16 Micron Technology, Inc. Trim process for critical dimension control for integrated circuits
US20080102643A1 (en) * 2006-10-31 2008-05-01 United Microelectronics Corp. Patterning method
KR100777927B1 (ko) * 2006-12-05 2007-11-21 동부일렉트로닉스 주식회사 반도체 소자의 미세패턴 형성방법
KR100838394B1 (ko) * 2007-01-03 2008-06-13 주식회사 하이닉스반도체 하드마스크층을 이용한 반도체소자의 식각 방법
JP5108489B2 (ja) * 2007-01-16 2012-12-26 株式会社日立ハイテクノロジーズ プラズマ処理方法
KR20080086686A (ko) * 2007-03-23 2008-09-26 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7605600B2 (en) 2007-04-05 2009-10-20 D-Wave Systems Inc. Systems, methods and apparatus for anti-symmetric qubit-coupling
JP5236983B2 (ja) * 2007-09-28 2013-07-17 東京エレクトロン株式会社 半導体装置の製造方法、半導体装置の製造装置、制御プログラム及びプログラム記憶媒体
US7759201B2 (en) * 2007-12-17 2010-07-20 Sandisk 3D Llc Method for fabricating pitch-doubling pillar structures
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CN113785381B (zh) 2019-04-30 2025-04-22 朗姆研究公司 用于极紫外光刻抗蚀剂改善的原子层蚀刻及选择性沉积处理
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CN114200776A (zh) 2020-01-15 2022-03-18 朗姆研究公司 用于光刻胶粘附和剂量减少的底层
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CN114464624B (zh) * 2020-11-10 2025-05-30 华邦电子股份有限公司 半导体存储器结构的形成方法
CN115152008A (zh) 2020-11-13 2022-10-04 朗姆研究公司 用于干法去除光致抗蚀剂的处理工具
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CN114284134A (zh) * 2021-12-14 2022-04-05 华虹半导体(无锡)有限公司 半导体制程中铝线的刻蚀方法
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