CN101421824B - 对集成电路进行临界尺寸控制的修整工艺 - Google Patents

对集成电路进行临界尺寸控制的修整工艺 Download PDF

Info

Publication number
CN101421824B
CN101421824B CN2007800136527A CN200780013652A CN101421824B CN 101421824 B CN101421824 B CN 101421824B CN 2007800136527 A CN2007800136527 A CN 2007800136527A CN 200780013652 A CN200780013652 A CN 200780013652A CN 101421824 B CN101421824 B CN 101421824B
Authority
CN
China
Prior art keywords
hard mask
mask layer
layer
trimming
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2007800136527A
Other languages
English (en)
Chinese (zh)
Other versions
CN101421824A (zh
Inventor
米尔扎菲尔·K·阿巴切夫
克鲁帕卡尔·穆拉利·苏布拉马尼安
周葆所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN101421824A publication Critical patent/CN101421824A/zh
Application granted granted Critical
Publication of CN101421824B publication Critical patent/CN101421824B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
CN2007800136527A 2006-03-09 2007-03-05 对集成电路进行临界尺寸控制的修整工艺 Expired - Fee Related CN101421824B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/372,825 US7662718B2 (en) 2006-03-09 2006-03-09 Trim process for critical dimension control for integrated circuits
US11/372,825 2006-03-09
PCT/US2007/005639 WO2007103343A1 (en) 2006-03-09 2007-03-05 Trim process for critical dimension control for integrated circuits

Publications (2)

Publication Number Publication Date
CN101421824A CN101421824A (zh) 2009-04-29
CN101421824B true CN101421824B (zh) 2012-04-11

Family

ID=38219014

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800136527A Expired - Fee Related CN101421824B (zh) 2006-03-09 2007-03-05 对集成电路进行临界尺寸控制的修整工艺

Country Status (6)

Country Link
US (2) US7662718B2 (enExample)
EP (1) EP2002465A1 (enExample)
JP (1) JP2009529784A (enExample)
KR (1) KR20080112281A (enExample)
CN (1) CN101421824B (enExample)
WO (1) WO2007103343A1 (enExample)

Families Citing this family (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7533068B2 (en) 2004-12-23 2009-05-12 D-Wave Systems, Inc. Analog processor comprising quantum devices
JP2007081383A (ja) * 2005-08-15 2007-03-29 Fujitsu Ltd 微細構造の製造方法
US7662718B2 (en) * 2006-03-09 2010-02-16 Micron Technology, Inc. Trim process for critical dimension control for integrated circuits
US20080102643A1 (en) * 2006-10-31 2008-05-01 United Microelectronics Corp. Patterning method
KR100777927B1 (ko) * 2006-12-05 2007-11-21 동부일렉트로닉스 주식회사 반도체 소자의 미세패턴 형성방법
KR100838394B1 (ko) * 2007-01-03 2008-06-13 주식회사 하이닉스반도체 하드마스크층을 이용한 반도체소자의 식각 방법
JP5108489B2 (ja) * 2007-01-16 2012-12-26 株式会社日立ハイテクノロジーズ プラズマ処理方法
KR20080086686A (ko) * 2007-03-23 2008-09-26 주식회사 하이닉스반도체 반도체 소자의 제조방법
JP2010524064A (ja) 2007-04-05 2010-07-15 ディー−ウェイブ システムズ，インコーポレイテッド 汎用断熱量子コンピュータの物理的実現
JP5236983B2 (ja) * 2007-09-28 2013-07-17 東京エレクトロン株式会社 半導体装置の製造方法、半導体装置の製造装置、制御プログラム及びプログラム記憶媒体
US7759201B2 (en) * 2007-12-17 2010-07-20 Sandisk 3D Llc Method for fabricating pitch-doubling pillar structures
US7927782B2 (en) * 2007-12-28 2011-04-19 Texas Instruments Incorporated Simplified double mask patterning system
US8084366B2 (en) 2008-04-11 2011-12-27 Sandisk 3D Llc Modified DARC stack for resist patterning
US7713818B2 (en) * 2008-04-11 2010-05-11 Sandisk 3D, Llc Double patterning method
US7981592B2 (en) * 2008-04-11 2011-07-19 Sandisk 3D Llc Double patterning method
US7786015B2 (en) * 2008-04-28 2010-08-31 Sandisk 3D Llc Method for fabricating self-aligned complementary pillar structures and wiring
US8293460B2 (en) * 2008-06-16 2012-10-23 Applied Materials, Inc. Double exposure patterning with carbonaceous hardmask
JP5200687B2 (ja) * 2008-06-18 2013-06-05 富士通セミコンダクター株式会社 半導体装置の製造方法
US7781269B2 (en) 2008-06-30 2010-08-24 Sandisk 3D Llc Triangle two dimensional complementary patterning of pillars
US8076056B2 (en) * 2008-10-06 2011-12-13 Sandisk 3D Llc Method of making sub-resolution pillar structures using undercutting technique
JP2010226022A (ja) * 2009-03-25 2010-10-07 Elpida Memory Inc 半導体装置の製造方法
US7923305B1 (en) 2010-01-12 2011-04-12 Sandisk 3D Llc Patterning method for high density pillar structures
US8026178B2 (en) 2010-01-12 2011-09-27 Sandisk 3D Llc Patterning method for high density pillar structures
US8647980B2 (en) * 2010-02-25 2014-02-11 Sharp Kabushiki Kaisha Method of forming wiring and method of manufacturing semiconductor substrates
US20110244398A1 (en) * 2010-03-30 2011-10-06 United Microelectronics Corp Patterning method
KR20130141550A (ko) * 2010-10-27 2013-12-26 어플라이드 머티어리얼스, 인코포레이티드 포토레지스트 선폭 거칠기를 조절하기 위한 방법들 및 장치
US8691697B2 (en) 2010-11-11 2014-04-08 International Business Machines Corporation Self-aligned devices and methods of manufacture
CN102478764B (zh) * 2010-11-30 2013-08-07 中芯国际集成电路制造(北京)有限公司 双重图形化方法
CN102064096B (zh) * 2010-12-03 2012-07-25 北京大学 一种细线条的制备方法
US8535549B2 (en) * 2010-12-14 2013-09-17 Lam Research Corporation Method for forming stair-step structures
US8329051B2 (en) 2010-12-14 2012-12-11 Lam Research Corporation Method for forming stair-step structures
USRE46464E1 (en) 2010-12-14 2017-07-04 Lam Research Corporation Method for forming stair-step structures
KR101900976B1 (ko) * 2010-12-27 2018-09-20 브레우어 사이언스 인코포레이션 개선된 패터닝 요구를 위해 작은 특징 부분(feature)을 패터닝하는 방법
CN102129982A (zh) * 2010-12-29 2011-07-20 北京大学深圳研究生院 半导体精细图形及鳍形场效应管的fin体的制作方法
JP5485185B2 (ja) * 2011-01-05 2014-05-07 信越化学工業株式会社 レジスト下層膜材料及びこれを用いたパターン形成方法
US8871102B2 (en) * 2011-05-25 2014-10-28 Western Digital (Fremont), Llc Method and system for fabricating a narrow line structure in a magnetic recording head
US8541296B2 (en) * 2011-09-01 2013-09-24 The Institute of Microelectronics Chinese Academy of Science Method of manufacturing dummy gates in gate last process
CN102983073B (zh) * 2011-09-05 2015-12-09 中国科学院微电子研究所 小尺寸鳍形结构的制造方法
JP2013075984A (ja) * 2011-09-30 2013-04-25 Toshiba Corp 微細構造体の製造方法
JP2013089827A (ja) * 2011-10-20 2013-05-13 Fujitsu Semiconductor Ltd 半導体装置の製造方法
US20130130503A1 (en) * 2011-11-23 2013-05-23 Peking University Method for fabricating ultra-fine nanowire
US8722541B2 (en) * 2012-03-15 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Double patterning method for semiconductor devices
KR101912677B1 (ko) * 2012-08-10 2018-10-29 닛산 가가쿠 가부시키가이샤 레지스트 하층막 형성조성물
US8802565B2 (en) 2012-09-10 2014-08-12 International Business Machines Corporation Semiconductor plural gate lengths
US9105587B2 (en) 2012-11-08 2015-08-11 Micron Technology, Inc. Methods of forming semiconductor structures with sulfur dioxide etch chemistries
CN103928388A (zh) * 2013-01-10 2014-07-16 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
JP6091242B2 (ja) * 2013-02-18 2017-03-08 三菱電機株式会社 炭化珪素半導体装置の製造方法
US8999777B2 (en) * 2013-03-14 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of conducting a direction-specific trimming process for contact patterning
JP2015015287A (ja) 2013-07-03 2015-01-22 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
US9779952B2 (en) 2013-08-27 2017-10-03 Tokyo Electron Limited Method for laterally trimming a hardmask
TWI639179B (zh) 2014-01-31 2018-10-21 美商蘭姆研究公司 真空整合硬遮罩製程及設備
US10002107B2 (en) 2014-03-12 2018-06-19 D-Wave Systems Inc. Systems and methods for removing unwanted interactions in quantum devices
US9165765B1 (en) * 2014-09-09 2015-10-20 Tokyo Electron Limited Method for patterning differing critical dimensions at sub-resolution scales
KR102265271B1 (ko) 2015-01-14 2021-06-17 삼성전자주식회사 반도체 소자 및 그 제조방법
CN104716033A (zh) * 2015-03-20 2015-06-17 上海华力微电子有限公司 改善刻蚀腔体养护后多晶硅栅极关键尺寸稳定性的方法
US9673057B2 (en) 2015-03-23 2017-06-06 Lam Research Corporation Method for forming stair-step structures
US10008384B2 (en) 2015-06-25 2018-06-26 Varian Semiconductor Equipment Associates, Inc. Techniques to engineer nanoscale patterned features using ions
US9711359B2 (en) * 2015-08-13 2017-07-18 Lam Research Corporation Shadow trim line edge roughness reduction
US9741563B2 (en) 2016-01-27 2017-08-22 Lam Research Corporation Hybrid stair-step etch
US9899219B2 (en) * 2016-02-19 2018-02-20 Tokyo Electron Limited Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables
US10049875B2 (en) * 2016-03-04 2018-08-14 Tokyo Electron Limited Trim method for patterning during various stages of an integration scheme
US10566212B2 (en) 2016-12-19 2020-02-18 Lam Research Corporation Designer atomic layer etching
US11333968B2 (en) 2017-02-22 2022-05-17 Tokyo Electron Limited Method for reducing lithography defects and pattern transfer
US10276379B2 (en) * 2017-04-07 2019-04-30 Applied Materials, Inc. Treatment approach to improve film roughness by improving nucleation/adhesion of silicon oxide
US10832909B2 (en) 2017-04-24 2020-11-10 Lam Research Corporation Atomic layer etch, reactive precursors and energetic sources for patterning applications
US10796912B2 (en) * 2017-05-16 2020-10-06 Lam Research Corporation Eliminating yield impact of stochastics in lithography
US10312089B1 (en) * 2017-11-29 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for controlling an end-to-end distance in semiconductor device
WO2019126396A1 (en) 2017-12-20 2019-06-27 D-Wave Systems Inc. Systems and methods for coupling qubits in a quantum processor
US10522751B2 (en) 2018-05-22 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. MTJ CD variation by HM trimming
CN113039486B (zh) 2018-11-14 2024-11-12 朗姆研究公司 可用于下一代光刻法中的硬掩模制作方法
CN113227909B (zh) 2018-12-20 2025-07-04 朗姆研究公司 抗蚀剂的干式显影
TW202514246A (zh) 2019-03-18 2025-04-01 美商蘭姆研究公司 基板處理方法與設備
CN109950140B (zh) * 2019-04-18 2021-11-05 上海华力微电子有限公司 一种自对准双层图形的形成方法
CN109950141A (zh) * 2019-04-18 2019-06-28 上海华力微电子有限公司 一种半导体结构的形成方法
US12062538B2 (en) 2019-04-30 2024-08-13 Lam Research Corporation Atomic layer etch and selective deposition process for extreme ultraviolet lithography resist improvement
TWI869221B (zh) 2019-06-26 2025-01-01 美商蘭姆研究公司 利用鹵化物化學品的光阻顯影
US11521846B2 (en) * 2019-12-16 2022-12-06 Taiwan Semiconductor Manufacturing Company Limited Methods for patterning a silicon oxide-silicon nitride-silicon oxide stack and structures formed by the same
KR20250007037A (ko) 2020-01-15 2025-01-13 램 리써치 코포레이션 포토레지스트 부착 및 선량 감소를 위한 하부층
WO2021173557A1 (en) 2020-02-28 2021-09-02 Lam Research Corporation Multi-layer hardmask for defect reduction in euv patterning
TWI876020B (zh) 2020-04-03 2025-03-11 美商蘭姆研究公司 處理光阻的方法、以及用於沉積薄膜的設備
CN116626993A (zh) 2020-07-07 2023-08-22 朗姆研究公司 用于图案化辐射光致抗蚀剂图案化的集成干燥工艺
CN114464624B (zh) * 2020-11-10 2025-05-30 华邦电子股份有限公司 半导体存储器结构的形成方法
JP7562696B2 (ja) 2020-11-13 2024-10-07 ラム リサーチ コーポレーション フォトレジストのドライ除去用プロセスツール
CN114284134A (zh) * 2021-12-14 2022-04-05 华虹半导体(无锡)有限公司 半导体制程中铝线的刻蚀方法
EP4493981A4 (en) * 2022-03-17 2025-11-19 Photonic Inc SYSTEMS AND METHODS FOR ADJUSTING PHOTONIC INTEGRATED CIRCUITS

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6764903B1 (en) * 2003-04-30 2004-07-20 Taiwan Semiconductor Manufacturing Co., Ltd Dual hard mask layer patterning method
US6913958B1 (en) * 2003-02-14 2005-07-05 Advanced Micro Devices Method for patterning a feature using a trimmed hardmask

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4431477A (en) * 1983-07-05 1984-02-14 Matheson Gas Products, Inc. Plasma etching with nitrous oxide and fluoro compound gas mixture
EP0394597A1 (en) 1989-04-28 1990-10-31 International Business Machines Corporation Follow-up System for Monitoring the Etching Process in an RIE Equipment and its Application to Producing High-resolution and Reproducible Patterns
US5153691A (en) 1989-06-21 1992-10-06 Xicor, Inc. Apparatus for a dual thickness floating gate memory cell
US5431770A (en) 1993-10-13 1995-07-11 At&T Corp. Transistor gate formation
US5804088A (en) 1996-07-12 1998-09-08 Texas Instruments Incorporated Intermediate layer lithography
US5930634A (en) 1997-04-21 1999-07-27 Advanced Micro Devices, Inc. Method of making an IGFET with a multilevel gate
US5885887A (en) 1997-04-21 1999-03-23 Advanced Micro Devices, Inc. Method of making an igfet with selectively doped multilevel polysilicon gate
US5965461A (en) 1997-08-01 1999-10-12 Advanced Micro Devices, Inc. Controlled linewidth reduction during gate pattern formation using a spin-on barc
JPH1168095A (ja) 1997-08-11 1999-03-09 Fujitsu Ltd 半導体装置の製造方法
US6121123A (en) 1997-09-05 2000-09-19 Advanced Micro Devices, Inc. Gate pattern formation using a BARC as a hardmask
WO2000003303A1 (en) 1998-07-10 2000-01-20 Clariant International Ltd. Composition for bottom reflection preventive film and novel polymeric dye for use in the same
US6156629A (en) * 1998-10-01 2000-12-05 Taiwan Semiconductor Manufacturing Company Method for patterning a polysilicon gate in deep submicron technology
US6194323B1 (en) 1998-12-16 2001-02-27 Lucent Technologies Inc. Deep sub-micron metal etch with in-situ hard mask etch
US6156485A (en) 1999-01-19 2000-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Film scheme to solve high aspect ratio metal etch masking layer selectivity and improve photo I-line PR resolution capability in quarter-micron technology
US6890448B2 (en) 1999-06-11 2005-05-10 Shipley Company, L.L.C. Antireflective hard mask compositions
US6248635B1 (en) 1999-10-25 2001-06-19 Advanced Micro Devices, Inc. Process for fabricating a bit-line in a monos device using a dual layer hard mask
US6174818B1 (en) 1999-11-19 2001-01-16 Taiwan Semiconductor Manufacturing Company Method of patterning narrow gate electrode
US6420097B1 (en) 2000-05-02 2002-07-16 Advanced Micro Devices, Inc. Hardmask trim process
US6281130B1 (en) 2000-06-16 2001-08-28 Advanced Micro Devices, Inc. Method for developing ultra-thin resist films
US6429067B1 (en) 2001-01-17 2002-08-06 International Business Machines Corporation Dual mask process for semiconductor devices
JP2003031557A (ja) * 2001-07-16 2003-01-31 Toshiba Corp 半導体装置の製造方法
US20030092281A1 (en) * 2001-11-13 2003-05-15 Chartered Semiconductors Manufactured Limited Method for organic barc and photoresist trimming process
US6828205B2 (en) * 2002-02-07 2004-12-07 Taiwan Semiconductor Manufacturing Co., Ltd Method using wet etching to trim a critical dimension
US6921723B1 (en) * 2002-04-23 2005-07-26 Applied Materials, Inc. Etching method having high silicon-to-photoresist selectivity
US6762130B2 (en) 2002-05-31 2004-07-13 Texas Instruments Incorporated Method of photolithographically forming extremely narrow transistor gate elements
US6794230B2 (en) 2002-10-31 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Approach to improve line end shortening
US20040087153A1 (en) * 2002-10-31 2004-05-06 Yan Du Method of etching a silicon-containing dielectric material
US6900002B1 (en) 2002-11-19 2005-05-31 Advanced Micro Devices, Inc. Antireflective bi-layer hardmask including a densified amorphous carbon layer
JP2005045053A (ja) * 2003-07-23 2005-02-17 Elpida Memory Inc 半導体装置の製造方法
US7094613B2 (en) * 2003-10-21 2006-08-22 Applied Materials, Inc. Method for controlling accuracy and repeatability of an etch process
US7077903B2 (en) 2003-11-10 2006-07-18 International Business Machines Corporation Etch selectivity enhancement for tunable etch resistant anti-reflective layer
DE10356668B4 (de) 2003-12-04 2005-11-03 Infineon Technologies Ag Herstellungsverfahren für eine Hartmaske auf einer Halbleiterstruktur
US7354847B2 (en) * 2004-01-26 2008-04-08 Taiwan Semiconductor Manufacturing Company Method of trimming technology
US7097779B2 (en) * 2004-07-06 2006-08-29 Tokyo Electron Limited Processing system and method for chemically treating a TERA layer
KR100704470B1 (ko) * 2004-07-29 2007-04-10 주식회사 하이닉스반도체 비결정성 탄소막을 희생 하드마스크로 이용하는반도체소자 제조 방법
US7271106B2 (en) 2004-08-31 2007-09-18 Micron Technology, Inc. Critical dimension control for integrated circuits
US20070037101A1 (en) * 2005-08-15 2007-02-15 Fujitsu Limited Manufacture method for micro structure
US7662718B2 (en) * 2006-03-09 2010-02-16 Micron Technology, Inc. Trim process for critical dimension control for integrated circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6913958B1 (en) * 2003-02-14 2005-07-05 Advanced Micro Devices Method for patterning a feature using a trimmed hardmask
US6764903B1 (en) * 2003-04-30 2004-07-20 Taiwan Semiconductor Manufacturing Co., Ltd Dual hard mask layer patterning method

Also Published As

Publication number Publication date
US7662718B2 (en) 2010-02-16
WO2007103343A1 (en) 2007-09-13
US20070212889A1 (en) 2007-09-13
US7910483B2 (en) 2011-03-22
US20100173498A1 (en) 2010-07-08
CN101421824A (zh) 2009-04-29
KR20080112281A (ko) 2008-12-24
EP2002465A1 (en) 2008-12-17
JP2009529784A (ja) 2009-08-20

Similar Documents

Publication Publication Date Title
CN101421824B (zh) 对集成电路进行临界尺寸控制的修整工艺
US7563723B2 (en) Critical dimension control for integrated circuits
US7015124B1 (en) Use of amorphous carbon for gate patterning
US7977242B2 (en) Double mask self-aligned double patterning technology (SADPT) process
KR100876892B1 (ko) 반도체 소자의 제조방법
US7390750B1 (en) Method of patterning elements within a semiconductor topography
KR20070107017A (ko) 트리밍과 호환되는 라인 에지 조도 감소 방법
KR20140002739A (ko) 개선된 측벽 이미지 전사 프로세스
CN1495878A (zh) 于半导体元件的制造中缩小间距的方法
KR102650776B1 (ko) 반도체 패터닝 및 형성된 구조
US6423475B1 (en) Sidewall formation for sidewall patterning of sub 100 nm structures
CN100426453C (zh) 微细图案形成方法
KR20090011933A (ko) 반도체 소자의 제조방법
US11652003B2 (en) Gate formation process
CN1818799B (zh) 光致抗蚀剂层的表面处理方法及光致抗蚀剂层的形成方法
JP3906037B2 (ja) 半導体装置の製造方法
KR100571629B1 (ko) 반도체 소자 제조 방법
CN101188188A (zh) 图案化的方法
KR20080085280A (ko) 반도체 소자의 패턴 형성 방법
US20240429053A1 (en) Method for reducing critical dimension of patterns generated using a lithography tool
KR102647990B1 (ko) 반도체 디바이스들의 패터닝 및 그로부터 발생하는 구조물들
KR100816210B1 (ko) 반도체 장치 형성 방법
KR100699678B1 (ko) 하드 마스크를 이용한 패턴 형성 방법
KR20100011488A (ko) 반도체 소자의 패턴 형성방법
KR20080094403A (ko) 반도체 소자의 하드마스크 형성 방법 및 이를 이용한 패턴형성 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120411

Termination date: 20130305