CN113948371A - 半导体图案化及所得的结构 - Google Patents
半导体图案化及所得的结构 Download PDFInfo
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- CN113948371A CN113948371A CN202110421104.XA CN202110421104A CN113948371A CN 113948371 A CN113948371 A CN 113948371A CN 202110421104 A CN202110421104 A CN 202110421104A CN 113948371 A CN113948371 A CN 113948371A
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- layer
- hard mask
- oxide
- depositing
- mandrels
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 238000000059 patterning Methods 0.000 title claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 127
- 125000006850 spacer group Chemical group 0.000 claims abstract description 86
- 238000000151 deposition Methods 0.000 claims abstract description 74
- 238000005530 etching Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000005229 chemical vapour deposition Methods 0.000 claims description 16
- 238000000231 atomic layer deposition Methods 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 238000011066 ex-situ storage Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 439
- 239000011295 pitch Substances 0.000 description 19
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 238000002955 isolation Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000002086 nanomaterial Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000009966 trimming Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 4
- -1 SiO)2Etc.) Chemical compound 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000002243 precursor Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002135 nanosheet Substances 0.000 description 2
- 239000002070 nanowire Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VZPPHXVFMVZRTE-UHFFFAOYSA-N [Kr]F Chemical compound [Kr]F VZPPHXVFMVZRTE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000109 continuous material Substances 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001900 extreme ultraviolet lithography Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000000671 immersion lithography Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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Abstract
本公开涉及半导体图案化及所得的结构。一种方法包括在目标层之上沉积硬掩模。沉积硬掩模包括沉积具有第一密度的第一硬掩模层,以及在第一硬掩模层之上沉积第二硬掩模层,第二硬掩模层具有大于第一密度的第二密度。该方法进一步包括:在硬掩模之上形成多个心轴;在多个心轴之上并沿着多个心轴的侧壁沉积间隔件层;图案化间隔件层以在多个心轴的侧壁上提供多个间隔件;在图案化间隔件层之后,去除多个心轴;将多个间隔件的图案转移到硬掩模;以及使用硬掩模作为掩模来图案化目标层。
Description
技术领域
本公开一般地涉及半导体图案化及所得的结构。
背景技术
随着半导体器件日趋缩小,各种工艺技术(例如,光刻)适配于允许制造尺寸越来越小的器件。例如,随着栅极密度增加,器件中的各种特征(例如,上覆的互连特征)的制造工艺适配于与器件特征整体的缩小相兼容。然而,随着半导体工艺具有越来越小的工艺窗口,这些器件的制造已经接近以及甚至超过了光刻设备的理论极限。随着半导体器件不断缩小,器件的元件之间所需的间隔(即间距)小于使用传统的光学掩模和光刻设备可以制造的间距。
发明内容
根据本公开的一个实施例,提供了一种形成半导体器件的方法,包括:在目标层之上沉积硬掩模,其中,沉积所述硬掩模包括:沉积具有第一密度的第一硬掩模层;以及在所述第一硬掩模层之上沉积第二硬掩模层,所述第二硬掩模层具有大于所述第一密度的第二密度;在所述硬掩模之上形成多个心轴;在所述多个心轴之上并沿着所述多个心轴的侧壁沉积间隔件层;图案化所述间隔件层以在所述多个心轴的侧壁上提供多个间隔件;在图案化所述间隔件层之后,去除所述多个心轴;将所述多个间隔件的图案转移到所述硬掩模;以及使用所述硬掩模作为掩模来图案化所述目标层。
根据本公开的另一实施例,提供了一种形成半导体器件的方法,包括:在目标层之上沉积第一氧化物硬掩模层;在所述第一氧化物硬掩模层之上沉积第二氧化物硬掩模层,其中,所述第二氧化物硬掩模层具有比所述第一氧化物硬掩模层更大的密度;在所述第二氧化物硬掩模层之上沉积心轴层;蚀刻所述心轴层以限定多个心轴;在所述多个心轴的侧壁上形成间隔件;去除所述多个心轴以在所述间隔件之间限定开口;使用所述间隔件作为掩模来图案化所述第一氧化物硬掩模层;以及使用所述第一氧化物硬掩模层作为掩模来图案化所述目标层。
根据本公开的又一实施例,提供了一种形成半导体器件的方法,包括:在半导体层之上沉积第一氧化物层;在所述第一氧化物层之上沉积第二氧化物层,其中,所述第二氧化物层具有比所述第一氧化物层更大的密度,并且其中,所述第二氧化物层比所述第一氧化物层更薄;在所述第二氧化物层之上形成多个心轴;在所述多个心轴的侧壁上形成间隔件;去除所述多个心轴以在所述间隔件之间限定开口,其中,去除所述多个心轴在所述第二氧化物层中蚀刻凹部;使用所述间隔件作为掩模来图案化所述第一氧化物层;以及使用所述第一氧化物层作为掩模来图案化所述半导体层。
附图说明
在结合附图阅读下面时,可以从下面的具体实施方式最佳地理解本公开的各方面。注意,根据行业的标准做法,各种特征不是按比例绘制的。事实上,为了讨论的清楚起见,各种特征的尺寸可被任意增大或减小。
图1、图2、图3、图4、图5、图6、图7A、图7B、图8、图9和图10示出了根据各个实施例的制造半导体器件的各个中间阶段的截面图和透视图。
图11至图13示出了根据各种其他实施例的制造半导体器件的各个中间阶段的截面图和透视图。
具体实施方式
下面的公开内容提供了用于实现本发明的不同特征的许多不同的实施例或示例。下文描述了组件和布置的具体示例以简化本公开。当然,这些仅是示例而不意图是限制性的。例如,在下面的描述中,在第二特征上方或之上形成第一特征可包括以直接接触的方式形成第一特征和第二特征的实施例,并且还可包括可以在第一特征和第二特征之间形成附加特征,使得第一特征和第二特征可以不直接接触的实施例。此外,本公开可以在各个示例中重复参考数字和/或字母。该重复是出于简单和清楚的目的,并且其本身不指示所讨论的各种实施例和/或配置之间的关系。
此外,本文可使用空间相关术语(例如,“下方”、“之下”、“低于”、“以上”、“上部”等),以易于描述图中所示的一个要素或特征相对于另外(一个或多个)要素或(一个或多个)特征的关系。这些空间相关术语意在涵盖器件在使用或工作中除了图中所示朝向之外的不同朝向。装置可能以其他方式定向(旋转90度或处于其他朝向),并且本文中所用的空间相关描述符同样可被相应地解释。
关于具体图案化工艺描述了各种实施例,即自对准双图案化(SADP)工艺,其中,对心轴(mandrel)进行图案化,沿着心轴的侧壁形成间隔件,并且去除心轴,留下间隔件以限定半心轴间距的图案。然而,各种实施例可以针对其他图案化工艺,例如,自对准四重图案化(SAQP)等。
根据一些实施例,提供了一种半导体器件和方法。具体地,执行自对准双图案化工艺以将特征(例如,半导体鳍、栅极结构、导电线等)图案化到半导体器件中的目标层中。经图案化的特征的间距为使用光刻工艺可获得的最小间距的至少一半。在各种实施例中,在图案化工艺期间,多层氧化物被用作目标层之上的硬掩模。多层氧化物硬掩模可以包括第一氧化物层以及在第一氧化物层之上的第二氧化物层。第二氧化物层的密度可以大于第一氧化物层。使用实施例多层硬掩模可以实现优点。例如,相对致密的第二氧化物层可有助于减少图案化期间的氧化物损失并改善临界尺寸(CD)控制。此外,在其中使用双图案化工艺来图案化半导体鳍的实施例中,还可以实现减少的缺陷(例如,掩模层中的较少弯曲)以及改善的鳍轮廓控制(例如,更均匀的轮廓)。此外,与更致密的第二氧化物层相比,使用相对较不致密的第一氧化物层可以通过更快的第一氧化物层的沉积时间来降低成本并提高产量。
图1至图10示出了根据一些示例性实施例的在半导体器件100的目标层104中形成特征的中间阶段的截面图。目标层104是根据本公开的实施例的将在其中形成多个图案的层。在一些实施例中,半导体器件100作为较大晶圆的一部分而被处理。在这样的实施例中,在形成半导体器件100的各种特征(例如,有源器件、互连结构等)之后,可以应用分离工艺(singulation process)以对晶圆的线区域进行划线(scribe),以便将各个半导体管芯与晶圆分开(也称为分离)。
在一些实施例中,目标层104是半导体衬底。半导体衬底可以包括掺杂的或未掺杂的硅,或者绝缘体上半导体(SOI)衬底的有源层。目标层104可以包括其他半导体材料,例如,锗;化合物半导体,包括碳化硅,砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。还可以使用其他衬底,例如,多层衬底或梯度衬底。可以利用实施例工艺来图案化半导体衬底,并且可以使用后续工艺步骤来在衬底中形成浅沟槽隔离(STI)区域。半导体鳍可以从所形成的STI区域之间突出。可以在半导体鳍中形成源极/漏极区域,并且可以在鳍的沟道区域之上形成栅极电介质和电极层,从而形成诸如鳍场效应晶体管(finFET)之类的半导体器件。
在一些实施例中,目标层104是被毯式沉积的导电层,例如,金属层或多晶硅层。实施例图案化工艺可应用于目标层104,以图案化finFETS的半导体栅极和/或虚设栅极。通过使用实施例工艺来图案化导电目标层104,可以减小相邻的栅极之间的间隔并且可以增加栅极密度。在这样的实施例中,目标层104可被形成在例如如上所述的半导体衬底之上。
在一些实施例中,目标层104是金属间电介质(IMD)层。在这样的实施例中,目标层104包括介电常数(k值)例如小于3.8、小于约3.0或小于约2.5的低k电介质材料。在替代实施例中,目标层104是包括k值高于3.8的高k电介质材料的IMD层。可以利用实施例工艺在目标层104中图案化开口,并且可以在开口中形成导电线和/或通孔。在这样的实施例中,目标层可被形成在半导体衬底之上(例如,如上所述),并且可以在半导体衬底的有源表面之中和/或之上形成诸如晶体管、二极管、电容器、电阻器等之类的器件。
粘附层102被沉积在目标层104之上。粘附层102可通过物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)等来沉积。在一些实施例中,粘附层102可用作粘附层,并且在随后的鳍形成期间可用作蚀刻停止层。尽管图1示出粘附层102与目标层104实体接触,但是可以在粘附层102和目标层104之间设置任意数量的中间层。
膜堆叠还包括形成在粘附层102之上的硬掩模层106。硬掩模层106可以由与粘附层102相比可被选择性地蚀刻的材料形成。例如,在其中粘附层102包括氧化物的实施例中,硬掩模层106可以是氮化物,例如,氮化硅等。硬掩模层108可以例如通过PVD、CVD、ALD等来沉积。在一些实施例中,硬掩模层106可具有例如约至约的范围。
膜堆叠还包括在硬掩模层106之上的多层硬掩模108。多层硬掩模108可包括第一硬掩模层108A以及第一硬掩模层108A之上的第二硬掩模层108B。在一些实施例中,多层硬掩模108可以包括与硬掩模层106相比可被选择性地蚀刻的材料。例如,在其中硬掩模层106包括氮化物的实施例中,多层硬掩模108可包括氧化物。具体地,在一些实施例中,第一硬掩模层108A和第二硬掩模层108B各自包括氧化硅(例如,SiO2等)、氮氧化硅(SiON)、碳氮氧化硅(SiOCN)、其组合等。
在各种实施例中,第二硬掩模层108B的密度比第一硬掩模层108A更高。例如,第一硬掩模层108A的密度在约1.6g/cm3至约1.8g/cm3的范围内,而第二硬掩模层108B的密度在约1.8g/cm3至约2.3g/cm3的范围内。在各种实施例中,第二硬掩模层108B具有至少约1.8g/cm3的密度。通过在多层硬掩模108中使用相对致密(例如,在上述范围内)的顶层,第二硬掩模层108B可以在后续的图案化步骤期间保护下面的特征(例如,第一硬掩模层108A),并减少制造缺陷。例如,更致密的材料较不易被蚀刻,并且可以实现多层硬掩模108的氧化物损失,在目标层104中产生改进的掩模弯曲控制、改进的临界尺寸控制、以及改进的图案化特征(例如,鳍)的轮廓。
在一些实施例中,第一硬掩模层108A和第二硬掩模层108B两者都是使用CVD(例如,等离子体增强CVD(PECVD))来沉积的。第二硬掩模层108B可以与第一硬掩模层108A原位(in-situ)沉积(例如,在持续真空环境中的同一工艺室内)。在第一硬掩模层108A和第二硬掩模层108B两者的沉积期间使用的前体可以包括含硅气体(例如,SiH4)和含氧气体(例如,N2O)。在沉积期间也可以存在其他气体,例如,载气。在一些实施例中,可以以比第一硬掩模层108A更高的等离子体功率和/或更低的沉积速率来执行沉积第二硬掩模层108B,使得第二硬掩模层108B的密度可以大于第一硬掩模层108A的密度。例如,在沉积第二硬掩模层108B时施加的等离子体功率可以在约400W至约800W的范围内,而在沉积第一硬掩模层108A时施加的等离子体功率可以在约200W至约400W的范围内。作为另一示例,第二硬掩模层108B的沉积速率可以在约 至约的范围内,并且第一硬掩模层108A的沉积速率可以在约至约的范围内。
在其他实施例中,第一硬掩模层108A可以通过CVD(例如,使用上述工艺参数)来沉积,而第二硬掩模层108B使用与第一硬掩模层108A非原位(ex-situ)执行(例如,在不同的工艺室中)的不同工艺来沉积。例如,第二硬掩模层108B可通过原子层沉积(ALD)来沉积。在一些实施例中,ALD工艺可包括使含硅前体(例如,H2Si[N(C2H5)2]2、SAM 24等)和含氧前体(例如,氧等离子体等)流入工艺室中以沉积第二硬掩模层108B。在沉积期间也可以存在其他气体,例如,载气。
在所得的结构中,第二硬掩模层108B比第一硬掩模层108A更薄。例如,第一硬掩模层108A可以具有约至约的范围内的厚度T1,并且第二硬掩模层108B可以具有约至约的范围内的厚度T2。此外,厚度T2与厚度T1之比可以在约1:6至约1:4的范围内。已经观察到,当第一硬掩模层108A的厚度T1小于或大于上述范围时,沉积掩模层108的工艺时间可能过长,并且制造成本可能大得无法接受。此外,已经观察到,当厚度T2小于上述范围时,第二硬掩模层108B可能无法在图案化期间充分地保护下面的第一硬掩模层108A,这导致不可接受的高水平的氧化物损失和制造缺陷。
膜堆叠还包括形成在硬掩模108之上的心轴层112。心轴层112可以包括硅(例如,非晶硅)等。心轴层112可以使用诸如ALD、CVD、PVD等之类的任何合适的工艺来沉积。
三层光致抗蚀剂120在膜堆叠上被形成在心轴层112之上。三层光致抗蚀剂120包括底层114、底层114之上的中间层116、以及中间层116之上的上层118。底层114和上层118可以由包括有机材料的光致抗蚀剂(例如,光敏材料)形成。在一些实施例中,底层114也可以是底部抗反射涂覆(BARC)层。中间层116可以包括无机材料,其可以是氮化物(例如,氮化硅)、氧氮化物(例如,氧氮化硅)、氧化物(例如,氧化硅)等。相对于上层118和底层114,中间层116具有高蚀刻选择性。三层光致抗蚀剂120的各个层可以使用例如旋涂工艺来顺序地毯式沉积。尽管本文讨论了三层光致抗蚀剂120,但是在其他实施例中,光致抗蚀剂120可以是单层或双层(例如,仅包括底层114和上层118而没有中间层116)光致抗蚀剂。所使用的光致抗蚀剂的类型(例如,单层、双层或三层)可取决于用于对心轴层112进行图案化的光刻工艺。例如,在高级极紫外(EUV)光刻工艺中,可使用单层或双层光致抗蚀剂120。
在一些实施例中,使用光刻工艺来图案化上层118。随后,上层118被用作用于图案化中间层116(参见图2)的蚀刻掩模。然后,中间层116被用作用于图案化底层114的蚀刻掩模,并且然后底层114被用于图案化心轴层112(参见图3和图4)。已经观察到,通过使用三层光致抗蚀剂(例如,三层光致抗蚀剂120)来蚀刻目标层(例如,心轴层112),可以在目标层(例如,心轴层112)中实现精细间距图案的改善的清晰度。
使用任何合适的光刻工艺来图案化上层118以在其中形成开口122。作为在上层118中图案化开口122的示例,可以在上层118之上设置光掩模。上层118然后可以暴露于包括紫外线(UV)或准分子激光的辐射束,例如,来自氟化氪(KrF)准分子激光的248nm束、来自氟化氩(ArF)准分子激光的193nm束、或来自F2准分子激光的157nm束等,同时光掩模掩蔽上层118的区域。可以使用浸没光刻系统来执行顶部光致抗蚀剂层的暴露,以提高分辨率并减小最小可实现间距。可以执行烘烤或固化操作以硬化上层118,并且可以使用显影剂来去除上层118的暴露部分或未暴露部分,这取决于使用正性(positive)抗蚀剂还是负性(negative)抗蚀剂。开口122的间距P1可以是单独使用光刻工艺可获得的最小间距。例如,在一些实施例中,开口122的间距P1为约80nm或更小,或者甚至为约28nm或更小。还预期开口122的其他间距P1。
在上层118的图案化之后,上层118的图案在蚀刻工艺中被转移到中间层116。该蚀刻工艺是各向异性的,使得上层118中的开口122延伸穿过中间层116,并且在中间层116中具有与在上层118中大致相同的尺寸。所形成的结构在图2中示出。
可选地,可以执行修整工艺以增加中间层116中的开口122的尺寸。在实施例中,修整工艺是各向异性等离子体蚀刻工艺,其工艺气体包括O2、CO2、N2/H2、H2等、其组合、或适合于修整中间层116的任何其他气体。该修整可以增加开口122的宽度W1,并减小开口122之间的中间层116的部分的宽度W2。例如,在一些实施例中,在修整之后,宽度W2可以为20nm或更小。可执行该修整工艺以便获得宽度W1与宽度W2的期望比率,以使随后限定的结构被均匀地间隔开。在其他实施例中,中间层116初始地被图案化为具有宽度W1与宽度W2的期望比率,并且可以省略修整工艺。
在图3中,执行蚀刻工艺以将中间层116的图案转移到底层114,从而使开口122延伸穿过底层114。底层114的蚀刻工艺是各向异性的,使得中间层116中的开口122延伸穿过底层114,并且在中间层116中具有与在底层114中大致相同的尺寸。作为蚀刻底层114的一部分,上层118(参见图1和图2)可能被消耗。
在图4中,使用蚀刻工艺将底层114的图案(参见图3)转移到心轴层112。心轴层112的蚀刻工艺是各向异性的,使得底层114中的开口122延伸穿过心轴层112。开口122在心轴层112中具有与在底层114中大致相同的宽度。该蚀刻可以是干法蚀刻(例如,等离子体蚀刻)等。
在图案化心轴层112时,紧邻心轴层112下方的层(例如,硬掩模108)可被用作蚀刻停止层。具体地,该蚀刻工艺可以使用选择性地蚀刻心轴层112,而不显著地蚀刻第二硬掩模层108B的蚀刻剂。例如,在其中心轴层112包括硅并且硬掩模层包括氧化硅的实施例中,该蚀刻工艺可以使用HBr、CF4、Cl2、NF3等作为蚀刻剂。
因此,从心轴层112的其余部分(例如,开口122之间的心轴层112的部分)限定心轴124。心轴124具有间距P1(也参见图1)。在一些实施例中,间距P1是使用光刻工艺可获得的最小间距。此外,每个心轴112具有宽度W2,在一些实施例中,其可以为20nm或更小。在蚀刻心轴层112期间,中间层116被消耗,并且底层114可被至少部分地消耗。
在实施例中,当底层114在蚀刻心轴层112时未被完全消耗时,可以执行灰化工艺以去除底层114的剩余残留物。该灰化工艺可以包括氧等离子体带,其将心轴124暴露于氧等离子体。
在图5中,在心轴124之上并沿着心轴124的侧壁形成间隔件层126。间隔件层126可进一步在开口122中沿着硬掩模108的顶表面延伸。间隔件层126的材料被选择为相对于硬掩模层108和心轴124具有高蚀刻选择性。例如,间隔件层126可以包括SiN、SiCON、SiON、金属、金属合金等,并且可以使用任何合适的工艺来沉积,例如,ALD、CVD等。在一些实施例中,间隔件层126的沉积工艺是共形的,使得心轴124的侧壁上的间隔件层126的厚度基本上等于(例如,在制造公差内)心轴124的顶表面和开口122的底表面上的间隔件层126的厚度。
在图6中,间隔件层126被图案化以去除间隔件层126的横向部分,而在心轴124的侧壁上留下间隔件层128。蚀刻间隔件层126暴露心轴124以及心轴124的下方的层(例如,硬掩模108)的部分。图案化间隔件层126可以包括干法蚀刻工艺,该干法蚀刻工艺以比心轴124更高的速率选择性地蚀刻间隔件层126。用于蚀刻间隔件层126的示例蚀刻剂可以包括氟反应气体,例如,CF4、NF3、HCl、HBr等。其他处理气体可以与这些蚀刻剂结合使用,例如,氧(O2)、氮(N2)、氩(Ar)、其组合等。该干法蚀刻工艺可以是各向异性的并且蚀刻间隔件层126的暴露的横向部分,而留下心轴124上的间隔件层126的垂直部分(间隔件128)。
在图7A中,使用蚀刻工艺去除心轴124。由于心轴124和间隔件128相对于同一蚀刻工艺具有蚀刻选择性,因此可以在不去除间隔件128的情况下去除心轴124。刻蚀心轴124暴露下面的硬掩模108,其可以用作蚀刻停止层。在一些实施例中,蚀刻心轴124可减小间隔件128的高度,而不去除间隔件128。去除心轴124可以包括与图4中如上所述的用于图案化心轴124的工艺类似的干法蚀刻工艺。
在去除心轴124之后,间隔件127可具有间距P2。在采用如上所述的SADP工艺的实施例中,间距P2是通过光刻工艺可获得的最小间距(例如,间距P1)的一半。间隔件128限定硬掩模108的图案。在一些实施例中,间隔件128对应于随后被图案化到目标层104中的半导体鳍或栅极结构的图案。
图7B示出了图7A的区域100’的详细视图。如图7B所示,第二硬掩模层108B覆盖并保护下面的第一硬掩模层108A免受蚀刻,而去除心轴124,形成间隔件128(参见图6),并图案化心轴124(参见图4)。由于第二硬掩模层108B相对致密,因此它比第一硬掩模层108A更不易蚀刻。结果,可以减少氧化物损失。例如,由于去除心轴124、形成间隔件128并图案化心轴124,因此可以在第二硬掩模层108B中蚀刻凹部130,并且凹部130的深度D1可以小于约3nm,例如,在约1nm至约2nm的范围内。已经观察到,当下面的掩模层108的氧化物损失在上述范围内(例如,小于3nm)时,间隔件128是相对笔直的,并且避免了不期望的弯曲并可以控制间隔件128的基脚(footing)(例如,间隔件128周围的硬掩模108的轮廓)。结果,可以在随后图案化目标层104时实现较少的制造缺陷以及改进的轮廓/CD控制。
在图8中,使用间隔件128作为蚀刻掩模来蚀刻硬掩模108。因此,硬掩模108可具有与间隔件128相同的图案和间距。在一些实施例中,蚀刻硬掩模108包括各向异性干法蚀刻和/或湿法蚀刻。例如,硬掩模108可以通过以下工艺来图案化:干法刻蚀(例如,使用CF4、NF3、HCl、HBr等)、用于副产物去除的后续湿法刻蚀(例如,使用稀释氟化氢(DHF)、过氧化硫混合物(SPM)等)、以及用于颗粒清洁的清洁工艺(例如,标准清洁1(SC-1)等)。蚀刻硬掩模108可消耗间隔件128,消耗第二硬掩模层108B,并部分地消耗第一硬掩模层108A。结果,在硬掩模层108被蚀刻之后,仅第一硬掩模层108A可以保留,并且间隔件128和第二硬掩模层108B可被去除。
随后,在图9中,硬掩模108被用作蚀刻掩模以在目标层104中图案化开口140,其可以限定鳍142。蚀刻目标层104可以包括各向异性干法蚀刻工艺和/或湿法蚀刻工艺。目标层104的其余部分可以具有与图7A的间隔件128相同的图案。图案化目标层104可进一步消耗硬掩模108,并且可减小第一硬掩模层108A的高度。在各种实施例中,可以通过使用具有不同密度的两个不同层的硬掩模108来改善鳍142的轮廓。具体地,第二硬掩模层108B相对致密允许减少的氧化物损失,并且以改善的均匀性来图案化所形成的鳍142的宽度。
附加工艺步骤可被应用于结构100以形成鳍式场效应晶体管(FinFET)器件。例如,可以在鳍142周围沉积隔离区域,然后可以使隔离区域凹陷以暴露鳍142的上部。可以在鳍142的上部中图案化开口,并且可以开口中生长外延源极/漏极区域。此外,可以在鳍142的上部之上并沿着鳍142的上部的侧壁形成栅极结构。图10示出了根据一些实施例的三维视图中的FinFET的示例。FinFET包括鳍142,其可以根据以上图1-9中描述的工艺来进行图案化。鳍142在相邻的隔离区域56之上和之间突出。栅极电介质层92沿着鳍142的侧壁并且在鳍142的顶表面之上,并且栅极电极94在栅极电介质层92之上。源极/漏极区域82相对于栅极电介质层92和栅极电极94被布置在鳍142的相对侧。
以上实施例中的目标层104是单层材料。在其他实施例中,目标层104可具有多层结构。例如,图11示出了另一实施例,其中,目标层104包括交替的半导体层104A和104B。半导体层104A可以包括第一半导体材料,并且半导体层104B可以包括第二半导体材料,该第二半导体材料与第一半导体材料相比可被选择性地蚀刻。例如,半导体层104A可包括硅,而半导体层104B可包括硅锗。随后可以去除半导体层104B,并且可以对半导体层104A进行图案化,以形成纳米结构晶体管器件的沟道区域。在一些实施例中,纳米结构晶体管可以是纳米线晶体管、纳米片晶体管、栅极全环绕晶体管等。
图11示出了与图1的结构100相似的初始结构150,其中,相同的附图标记指示使用相同的工艺形成的相同的元件。例如,硬掩模108可以包括第一硬掩模层108A以及在第一硬掩模层108A之上的第二硬掩模层108B。第二硬掩模层108A可以相对致密。图12示出了使用与以上针对图1-8所述的类似工艺对目标层(包括半导体层104A和104B)进行图案化以限定鳍之后的实施例。由于使用了多层硬掩模108,因此可以在经图案化的目标层104中实现改善的轮廓。
附加工艺步骤可被应用于结构100以形成纳米结构晶体管器件。例如,可以在鳍周围沉积隔离区域,并然后可以使隔离区域凹陷以暴露鳍的上部。可以在鳍的上部中图案化开口,并且可以在开口中生长外延源极/漏极区域。此外,可以去除半导体层104A,并且可以对半导体层104B进行图案化以限定沟道区域。可以在沟道区域周围形成栅极结构。
图13示出了根据一些实施例的三维视图中的纳米结构晶体管的示例。纳米结构晶体管包括在衬底50(例如,半导体衬底)上的鳍之上的纳米结构55(例如,纳米片、纳米线等),其中,纳米结构55用作纳米结构晶体管的沟道区域。可以通过图案化半导体层104A来形成纳米结构55。纳米结构55可以包括p型纳米结构、n型纳米结构、或其组合。隔离区域68被设置在相邻的鳍66之间,其可以在相邻的隔离区域68之上以及从相邻的隔离区域68之间突出。尽管隔离区域68被描述/示出为与衬底50分离,但是如本文所使用的,术语“衬底”可以指代仅半导体衬底、或者半导体衬底和隔离区域的组合。此外,尽管鳍66的底部被示出为与衬底50的单个连续材料,但是鳍66的底部和/或衬底50可以包括单一材料或多种材料。在本文中,鳍66指的是在相邻的隔离区域68之间延伸的部分。
栅极电介质层96在鳍66的顶表面之上,并且沿着纳米结构55的顶表面、侧壁和底表面。栅极电极98在栅极电介质层96之上。外延源极/漏极区域90在栅极电介质层96和栅极电极98的相对侧被设置在鳍66上。
根据一些实施例,提供了半导体器件和方法。具体地,执行自对准双图案化工艺以将特征(例如,半导体鳍、栅极结构、导电线等)图案化到半导体器件中的目标层中。经图案化的特征的间距为使用光刻工艺可获得的最小间距的至少一半。在各种实施例中,在图案化工艺期间,多层氧化物被用作目标层之上的硬掩模。多层氧化物硬掩模可以包括第一氧化物层以及在第一氧化物层之上的第二氧化物层。第二氧化物层的密度可以大于第一氧化物层。使用实施例多层硬掩模可以实现优点。例如,相对致密的第二氧化物层可有助于减少图案化期间的氧化物损失,并改善CD控制。此外,在其中使用双图案化工艺来图案化半导体鳍的实施例中,还可以实现减少的缺陷(例如,掩模层中的较少弯曲)以及改善的鳍轮廓控制(例如,更均匀的轮廓)。此外,与更致密的第二氧化物层相比,较不致密的第一氧化物层由于更快的第一氧化物层的沉积时间而允许降低成本并提高产量。
在一些实施例中,一种方法包括:在目标层之上沉积硬掩模,其中,沉积硬掩模包括:沉积具有第一密度的第一硬掩模层;以及在第一硬掩模层之上沉积第二硬掩模层,第二硬掩模层具有大于第一密度的第二密度。该方法进一步包括:在硬掩模之上形成多个心轴;在多个心轴之上并沿着多个心轴的侧壁沉积间隔件层;图案化间隔件层以在多个心轴的侧壁上提供多个间隔件;在图案化间隔件层之后,去除多个心轴;将多个间隔件的图案转移到硬掩模;以及使用硬掩模作为掩模来图案化目标层。可选地,在一些实施例中,第一硬掩模层和第二硬掩模层各自包括氧化硅。可选地,在一些实施例中,第一硬掩模层包括氧化硅,并且其中,第二硬掩模层包括氮氧化硅、碳氮氧化硅、或它们的组合。可选地,在一些实施例中,沉积第二硬掩模层包括原位地沉积第二硬掩模层和第一硬掩模层。可选地,在一些实施例中,沉积第一硬掩模层包括化学气相沉积(CVD)工艺,并且其中,沉积第二硬掩模层包括与CVD工艺非原位地执行的原子层沉积(ALD)工艺。可选地,在一些实施例中,第一硬掩模层具有第一厚度,其中,第二硬掩模层具有第二厚度,并且其中,第二厚度与第一厚度之比在1:6至1:4的范围内。可选地,在一些实施例中,第二厚度在约至约的范围内,并且其中,第一厚度在约至约的范围内。可选地,在一些实施例中,目标层是半导体衬底,并且其中,使用硬掩模来图案化目标层包括:在半导体衬底中图案化半导体鳍。
在一些实施例中,一种方法包括:在目标层之上沉积第一氧化物硬掩模层;在第一氧化物硬掩模层之上沉积第二氧化物硬掩模层,其中,第二氧化物硬掩模层具有比第一氧化物硬掩模层更大的密度;在第二氧化物硬掩模层之上沉积心轴层;蚀刻心轴层以限定多个心轴;在多个心轴的侧壁上形成间隔件;去除多个心轴以在间隔件之间限定开口;使用间隔件作为掩模来图案化第一氧化物硬掩模层;以及使用第一氧化物硬掩模层作为掩模来图案化目标层。可选地,在一些实施例中,去除多个心轴在第二氧化物硬掩模层中蚀刻凹部。可选地,在一些实施例中,凹部的深度小于3nm。可选地,在一些实施例中,使用间隔件作为掩模来图案化第一氧化物硬掩模层包括:在图案化第一氧化物硬掩模层时去除第二氧化物硬掩模层。可选地,在一些实施例中,使用第一氧化物硬掩模层作为掩模来图案化目标层包括:去除第一氧化物硬掩模层的上部。可选地,在一些实施例中,沉积第二氧化物硬掩模层包括:在与沉积第一氧化物硬掩模层相同的工艺室中沉积第二氧化物硬掩模层。可选地,在一些实施例中,沉积第二氧化物硬掩模层包括:在与沉积第一氧化物硬掩模层不同的工艺室中沉积第二氧化物硬掩模层。
在一些实施例中,一种方法包括:在半导体层之上沉积第一氧化物层,以及在第一氧化物层之上沉积第二氧化物层。第二氧化物层具有比第一氧化物层更大的密度,并且第二氧化物层比第一氧化物层更薄。该方法进一步包括:在第二氧化物层之上形成多个心轴;在多个心轴的侧壁上形成间隔件;去除多个心轴以在间隔件之间限定开口,其中,去除多个心轴在第二氧化物层中蚀刻凹部;使用间隔件作为掩模来图案化第一氧化物层;以及使用第一氧化物层作为掩模来图案化半导体层。可选地,在一些实施例中,第二氧化物层的厚度与第一氧化物层的厚度之比在1:6至1:4的范围内。可选地,在一些实施例中,每个凹部的相应深度小于3nm。可选地,在一些实施例中,第二氧化物层包括氧化硅、氮氧化硅、碳氮氧化硅、或它们的组合。可选地,在一些实施例中,在去除多个心轴时,第二氧化物层完全覆盖第一氧化物层。
以上概述了若干实施例的特征,使得本领域技术人员可以更好地理解本公开的各方面。本领域技术人员应当理解,他们可以容易地使用本公开作为设计或修改其他工艺和结构以实现本文介绍的实施例的相同目的和/或实现本文介绍的实施例的相同优点的基础。本领域技术人员还应该认识到,这样的等同构造不脱离本公开的精神和范围,并且他们可以在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替换和变更。
示例1是一种形成半导体器件的方法,包括:在目标层之上沉积硬掩模,其中,沉积所述硬掩模包括:沉积具有第一密度的第一硬掩模层;以及在所述第一硬掩模层之上沉积第二硬掩模层,所述第二硬掩模层具有大于所述第一密度的第二密度;在所述硬掩模之上形成多个心轴;在所述多个心轴之上并沿着所述多个心轴的侧壁沉积间隔件层;图案化所述间隔件层以在所述多个心轴的侧壁上提供多个间隔件;在图案化所述间隔件层之后,去除所述多个心轴;将所述多个间隔件的图案转移到所述硬掩模;以及使用所述硬掩模作为掩模来图案化所述目标层。
示例2是示例1所述的方法,其中,所述第一硬掩模层和所述第二硬掩模层各自包括氧化硅。
示例3是示例1所述的方法,其中,所述第一硬掩模层包括氧化硅,并且其中,所述第二硬掩模层包括氮氧化硅、碳氮氧化硅、或它们的组合。
示例4是示例1所述的方法,其中,沉积所述第二硬掩模层包括:原位地沉积所述第二硬掩模层和所述第一硬掩模层。
示例5是示例1所述的方法,其中,沉积所述第一硬掩模层包括化学气相沉积(CVD)工艺,并且其中,沉积所述第二硬掩模层包括与所述CVD工艺非原位地执行的原子层沉积(ALD)工艺。
示例6是示例1所述的方法,其中,所述第一硬掩模层具有第一厚度,其中,所述第二硬掩模层具有第二厚度,并且其中,所述第二厚度与所述第一厚度之比在1:6至1:4的范围内。
示例8是示例6所述的方法,其中,所述目标层是半导体衬底,并且其中,使用所述硬掩模来图案化所述目标层包括:在所述半导体衬底中图案化半导体鳍。
示例9是一种形成半导体器件的方法,包括:在目标层之上沉积第一氧化物硬掩模层;在所述第一氧化物硬掩模层之上沉积第二氧化物硬掩模层,其中,所述第二氧化物硬掩模层具有比所述第一氧化物硬掩模层更大的密度;在所述第二氧化物硬掩模层之上沉积心轴层;蚀刻所述心轴层以限定多个心轴;在所述多个心轴的侧壁上形成间隔件;去除所述多个心轴以在所述间隔件之间限定开口;使用所述间隔件作为掩模来图案化所述第一氧化物硬掩模层;以及使用所述第一氧化物硬掩模层作为掩模来图案化所述目标层。
示例10是示例9所述的方法,其中,去除所述多个心轴在所述第二氧化物硬掩模层中蚀刻凹部。
示例11是示例10所述的方法,其中,所述凹部的深度小于3nm。
示例12是示例9所述的方法,其中,使用所述间隔件作为掩模来图案化所述第一氧化物硬掩模层包括:在图案化所述第一氧化物硬掩模层时去除所述第二氧化物硬掩模层。
示例13是示例9所述的方法,其中,使用所述第一氧化物硬掩模层作为掩模来图案化所述目标层包括:去除所述第一氧化物硬掩模层的上部。
示例14是示例9所述的方法,其中,沉积所述第二氧化物硬掩模层包括:在与沉积所述第一氧化物硬掩模层相同的工艺室中沉积所述第二氧化物硬掩模层。
示例15是示例9所述的方法,其中,沉积所述第二氧化物硬掩模层包括:在与沉积所述第一氧化物硬掩模层不同的工艺室中沉积所述第二氧化物硬掩模层。
示例16是一种形成半导体器件的方法,包括:在半导体层之上沉积第一氧化物层;在所述第一氧化物层之上沉积第二氧化物层,其中,所述第二氧化物层具有比所述第一氧化物层更大的密度,并且其中,所述第二氧化物层比所述第一氧化物层更薄;在所述第二氧化物层之上形成多个心轴;在所述多个心轴的侧壁上形成间隔件;去除所述多个心轴以在所述间隔件之间限定开口,其中,去除所述多个心轴在所述第二氧化物层中蚀刻凹部;使用所述间隔件作为掩模来图案化所述第一氧化物层;以及使用所述第一氧化物层作为掩模来图案化所述半导体层。
示例17是示例16所述的方法,其中,所述第二氧化物层的厚度与所述第一氧化物层的厚度之比在1:6至1:4的范围内。
示例18是示例16所述的方法,其中,每个所述凹部的相应深度小于3nm。
示例19是示例16所述的方法,其中,所述第二氧化物层包括氧化硅、氮氧化硅、碳氮氧化硅、或它们的组合。
示例20是示例16所述的方法,其中,在去除所述多个心轴时,所述第二氧化物层完全覆盖所述第一氧化物层。
Claims (10)
1.一种形成半导体器件的方法,包括:
在目标层之上沉积硬掩模,其中,沉积所述硬掩模包括:
沉积具有第一密度的第一硬掩模层;以及
在所述第一硬掩模层之上沉积第二硬掩模层,所述第二硬掩模层具有大于所述第一密度的第二密度;
在所述硬掩模之上形成多个心轴;
在所述多个心轴之上并沿着所述多个心轴的侧壁沉积间隔件层;
图案化所述间隔件层以在所述多个心轴的侧壁上提供多个间隔件;
在图案化所述间隔件层之后,去除所述多个心轴;
将所述多个间隔件的图案转移到所述硬掩模;以及
使用所述硬掩模作为掩模来图案化所述目标层。
2.根据权利要求1所述的方法,其中,所述第一硬掩模层和所述第二硬掩模层各自包括氧化硅。
3.根据权利要求1所述的方法,其中,所述第一硬掩模层包括氧化硅,并且其中,所述第二硬掩模层包括氮氧化硅、碳氮氧化硅、或它们的组合。
4.根据权利要求1所述的方法,其中,沉积所述第二硬掩模层包括:原位地沉积所述第二硬掩模层和所述第一硬掩模层。
5.根据权利要求1所述的方法,其中,沉积所述第一硬掩模层包括化学气相沉积CVD工艺,并且其中,沉积所述第二硬掩模层包括与所述CVD工艺非原位地执行的原子层沉积ALD工艺。
6.根据权利要求1所述的方法,其中,所述第一硬掩模层具有第一厚度,其中,所述第二硬掩模层具有第二厚度,并且其中,所述第二厚度与所述第一厚度之比在1:6至1:4的范围内。
8.根据权利要求6所述的方法,其中,所述目标层是半导体衬底,并且其中,使用所述硬掩模来图案化所述目标层包括:在所述半导体衬底中图案化半导体鳍。
9.一种形成半导体器件的方法,包括:
在目标层之上沉积第一氧化物硬掩模层;
在所述第一氧化物硬掩模层之上沉积第二氧化物硬掩模层,其中,所述第二氧化物硬掩模层具有比所述第一氧化物硬掩模层更大的密度;
在所述第二氧化物硬掩模层之上沉积心轴层;
蚀刻所述心轴层以限定多个心轴;
在所述多个心轴的侧壁上形成间隔件;
去除所述多个心轴以在所述间隔件之间限定开口;
使用所述间隔件作为掩模来图案化所述第一氧化物硬掩模层;以及
使用所述第一氧化物硬掩模层作为掩模来图案化所述目标层。
10.一种形成半导体器件的方法,包括:
在半导体层之上沉积第一氧化物层;
在所述第一氧化物层之上沉积第二氧化物层,其中,所述第二氧化物层具有比所述第一氧化物层更大的密度,并且其中,所述第二氧化物层比所述第一氧化物层更薄;
在所述第二氧化物层之上形成多个心轴;
在所述多个心轴的侧壁上形成间隔件;
去除所述多个心轴以在所述间隔件之间限定开口,其中,去除所述多个心轴在所述第二氧化物层中蚀刻凹部;
使用所述间隔件作为掩模来图案化所述第一氧化物层;以及
使用所述第一氧化物层作为掩模来图案化所述半导体层。
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CN115117158A (zh) * | 2022-08-31 | 2022-09-27 | 瑶芯微电子科技(上海)有限公司 | 一种具有空心栅极的vdmos及制备方法 |
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US11929254B2 (en) | 2024-03-12 |
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DE102021101467A1 (de) | 2022-03-31 |
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US11521856B2 (en) | 2022-12-06 |
US20220102142A1 (en) | 2022-03-31 |
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