KR20080112281A - 집적 회로용 ＣＤ(Ｃｒｉｔｉｃａｌ Ｄｉｍｅｎｓｉｏｎ) 제어를 위한 트림 프로세스 - Google Patents

집적 회로용 ＣＤ(Ｃｒｉｔｉｃａｌ Ｄｉｍｅｎｓｉｏｎ) 제어를 위한 트림 프로세스 Download PDF

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Publication number
KR20080112281A
KR20080112281A KR1020087024655A KR20087024655A KR20080112281A KR 20080112281 A KR20080112281 A KR 20080112281A KR 1020087024655 A KR1020087024655 A KR 1020087024655A KR 20087024655 A KR20087024655 A KR 20087024655A KR 20080112281 A KR20080112281 A KR 20080112281A
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KR
South Korea
Prior art keywords
hard mask
mask layer
layer
trimming
etching
Prior art date
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Ceased
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KR1020087024655A
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English (en)
Korean (ko)
Inventor
미르자페르 케이. 아바트체브
크루파카르 무랄리 수브라마니안
바오수오 조우
Original Assignee
마이크론 테크놀로지, 인크.
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Publication of KR20080112281A publication Critical patent/KR20080112281A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/696—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
KR1020087024655A 2006-03-09 2007-03-05 집적 회로용 ＣＤ(Ｃｒｉｔｉｃａｌ Ｄｉｍｅｎｓｉｏｎ) 제어를 위한 트림 프로세스 Ceased KR20080112281A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/372,825 2006-03-09
US11/372,825 US7662718B2 (en) 2006-03-09 2006-03-09 Trim process for critical dimension control for integrated circuits

Publications (1)

Publication Number Publication Date
KR20080112281A true KR20080112281A (ko) 2008-12-24

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KR1020087024655A Ceased KR20080112281A (ko) 2006-03-09 2007-03-05 집적 회로용 ＣＤ(Ｃｒｉｔｉｃａｌ Ｄｉｍｅｎｓｉｏｎ) 제어를 위한 트림 프로세스

Country Status (6)

Country Link
US (2) US7662718B2 (enExample)
EP (1) EP2002465A1 (enExample)
JP (1) JP2009529784A (enExample)
KR (1) KR20080112281A (enExample)
CN (1) CN101421824B (enExample)
WO (1) WO2007103343A1 (enExample)

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US9691627B2 (en) 2015-01-14 2017-06-27 Samsung Electronics Co., Ltd. Methods of forming semiconductor devices using auxiliary layers for trimming margin
KR20190063430A (ko) * 2017-11-29 2019-06-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 디바이스에서의 단대단 거리를 제어하는 방법
KR20210077569A (ko) * 2019-12-16 2021-06-25 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 실리콘 산화물-실리콘 질화물-실리콘 산화물 스택을 패터닝하는 방법 및 그에 의해 형성된 구조물

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CN101421824B (zh) 2012-04-11
US7910483B2 (en) 2011-03-22
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